From patchwork Tue Sep 12 14:42:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tianling Shen X-Patchwork-Id: 1833082 X-Patchwork-Delegate: mail@david-bauer.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=3kQod1FK; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RlRGY5ZRlz1ygM for ; Wed, 13 Sep 2023 00:45:57 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type:List-Help: Reply-To:List-Archive:List-Unsubscribe:List-Subscribe:From:List-Post:List-Id: Message-ID:MIME-Version:References:In-Reply-To:Date:Subject:To:Cc: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=YVkli2EZ/4zpnmeSDqQLzicMx1UejImZ0CoPxJyr41s=; b=3kQod1FKsJAKURCyO8n3lbNi4t AsB1xihjHM2aoSVDd92bp4ThAOoOyoxzo9ypBxHqZbMts1T0Xgf84sEF4RamgMix1Y8KXeIbXdafe lTA7axKfDN/USYYByoFY9hdvI9ij4AOB3/HSbDZU40u9FDnWBKV5DbtpuCRdRrpZQTvppuIvUYAfs 8xqpSGdrWJwL3TaJecMPDuk7FNZq3ZURU9utd7WZY0qLgnT79zS4fhIWyM8g92PLwnDnPEOU6kODn RFhr07nltzjbYKjc8naQbNpeQQcpVlnQzeoc8P+bxvD2PQ73ivC75cOIp02rvxzF8Kg+WpY8F79r+ O6itM44Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qg4by-003cBp-00; Tue, 12 Sep 2023 14:43:30 +0000 To: openwrt-devel@lists.openwrt.org Subject: [PATCH 01/12] u-boot: introduce dependencies check for swig and pyelftools Date: Tue, 12 Sep 2023 22:42:29 +0800 In-Reply-To: <20230912144240.51396-1-cnsztl@immortalwrt.org> References: <20230912144240.51396-1-cnsztl@immortalwrt.org> MIME-Version: 1.0 Message-ID: List-Id: OpenWrt Development List List-Post: X-Patchwork-Original-From: Tianling Shen via openwrt-devel From: Tianling Shen Precedence: list X-Mailman-Version: 2.1.34 X-BeenThere: openwrt-devel@lists.openwrt.org List-Subscribe: , List-Unsubscribe: , List-Archive: Reply-To: Tianling Shen List-Help: Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software. They are required by modern u-boot builds, e.g. uboot-rockchip and uboot-sunxi. Signed-off-by: Tianling Shen --- include/u-boot.mk | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/include/u-boot.mk b/include/u-boot.mk index 2b8106410f..09a73327f6 100644 --- a/include/u-boot.mk +++ b/include/u-boot.mk @@ -1,3 +1,5 @@ +include $(INCLUDE_DIR)/prereq.mk + PKG_NAME ?= u-boot ifndef PKG_SOURCE_PROTO @@ -18,6 +20,27 @@ PKG_LICENSE_FILES:=Licenses/README PKG_BUILD_PARALLEL:=1 +ifdef UBOOT_USE_BINMAN + $(eval $(call TestHostCommand,python3-pyelftools, \ + Please install the Python3 elftools module, \ + $(STAGING_DIR_HOST)/bin/python3 -c 'import elftools')) +endif + +ifdef UBOOT_USE_INTREE_DTC + $(eval $(call TestHostCommand,swig, \ + Please install the swig package, \ + swig -version)) + + $(eval $(call TestHostCommand,python3-dev, \ + Please install the python3-dev package, \ + python3.11-config --includes 2>&1 | grep 'python3', \ + python3.10-config --includes 2>&1 | grep 'python3', \ + python3.9-config --includes 2>&1 | grep 'python3', \ + python3.8-config --includes 2>&1 | grep 'python3', \ + python3.7-config --includes 2>&1 | grep 'python3', \ + python3-config --includes 2>&1 | grep -E 'python3\.([7-9]|[0-9][0-9])\.?')) +endif + export GCC_HONOUR_COPTS=s define Package/u-boot/install/default @@ -88,7 +111,9 @@ define Build/Configure/U-Boot +$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) $(UBOOT_CONFIGURE_VARS) oldconfig) endef -DTC=$(wildcard $(LINUX_DIR)/scripts/dtc/dtc) +ifndef UBOOT_USE_INTREE_DTC + DTC=$(wildcard $(LINUX_DIR)/scripts/dtc/dtc) +endif define Build/Compile/U-Boot +$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \ From patchwork Tue Sep 12 14:42:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tianling Shen X-Patchwork-Id: 1833089 X-Patchwork-Delegate: mail@david-bauer.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=ypCMjm/k; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RlRH35YkWz1ygM for ; Wed, 13 Sep 2023 00:46:23 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type:List-Help: Reply-To:List-Archive:List-Unsubscribe:List-Subscribe:From:List-Post:List-Id: Message-ID:MIME-Version:References:In-Reply-To:Date:Subject:To:Cc: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=q5IhjHqdTHdHA9kCK9qC4sDMpI9w/G7WotLZALF7qGQ=; b=ypCMjm/kCQNs+yW6Soc1nxTTar j2Qf+NFlNnvrqsLoGf9p/ijlOA3b90cX9XQJBNUtL5DS5EPpRIaAo23HKz/uvBdoWp/ZAyYcEWm61 gWkmdzjP6LJrOLyqJspNSZqz04zeAo3rgi4qr35NNPwe1CfCV75K2uPPpS8y5VSsfr6RHtKFMnbUZ MO9lEWe+iY+DF25tOxT174zTFDjK/zvk6aN8/e8/R/FWyo31/BqUU4HemdUZL/5JSfi0UjpiHkM9T YAqRm7AtlnRXHyBbjs3xmBbhXURDnJ/W9JX36ybxwOJxJulnhsWQ9kGbbpCuW5JNxP+qztoKOsNBk qlecentA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qg4bt-003cAG-2u; Tue, 12 Sep 2023 14:43:25 +0000 To: openwrt-devel@lists.openwrt.org Subject: [PATCH 02/12] uboot-rockchip: Update to 2023.07.02 Date: Tue, 12 Sep 2023 22:42:30 +0800 In-Reply-To: <20230912144240.51396-1-cnsztl@immortalwrt.org> References: <20230912144240.51396-1-cnsztl@immortalwrt.org> MIME-Version: 1.0 Message-ID: List-Id: OpenWrt Development List List-Post: X-Patchwork-Original-From: Tianling Shen via openwrt-devel From: Tianling Shen Precedence: list X-Mailman-Version: 2.1.34 X-BeenThere: openwrt-devel@lists.openwrt.org List-Subscribe: , List-Unsubscribe: , List-Archive: Reply-To: Tianling Shen List-Help: Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software. * Removed swig hacks and prebuilt of-platdata * Removed upstreamed patches - 101-rock64pro-disable-CONFIG_USE_PREBOOT.patch - 102-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R2C.patch * Reordered patches * Introduced new dependencies check * Overrided default PATH to avoid race condition (host python3 vs hostpkg python3) * Switched to use UBOOT_CUSTOMIZE_CONFIG for config update Signed-off-by: Tianling Shen --- package/boot/uboot-rockchip/Makefile | 32 +-- ...01-scripts-remove-dependency-on-swig.patch | 24 -- ...-spl-remove-dtoc-of-pdata-generation.patch | 28 --- ...8-Add-support-for-Orange-Pi-R1-Plus.patch} | 80 +++++-- ...rock64pro-disable-CONFIG_USE_PREBOOT.patch | 27 --- ...dd-support-for-Orange-Pi-R1-Plus-LT.patch} | 63 +++-- ...d-support-for-FriendlyARM-NanoPi-R2C.patch | 199 ---------------- .../of-platdata/nanopi-r2c-rk3328/dt-decl.h | 23 -- .../of-platdata/nanopi-r2c-rk3328/dt-plat.c | 155 ------------- .../nanopi-r2c-rk3328/dt-structs-gen.h | 51 ---- .../of-platdata/nanopi-r2s-rk3328/dt-decl.h | 23 -- .../of-platdata/nanopi-r2s-rk3328/dt-plat.c | 155 ------------- .../nanopi-r2s-rk3328/dt-structs-gen.h | 51 ---- .../orangepi-r1-plus-lts-rk3328/dt-decl.h | 24 -- .../orangepi-r1-plus-lts-rk3328/dt-plat.c | 170 -------------- .../dt-structs-gen.h | 55 ----- .../orangepi-r1-plus-rk3328/dt-decl.h | 24 -- .../orangepi-r1-plus-rk3328/dt-plat.c | 170 -------------- .../orangepi-r1-plus-rk3328/dt-structs-gen.h | 55 ----- .../src/of-platdata/roc-cc-rk3328/dt-decl.h | 24 -- .../src/of-platdata/roc-cc-rk3328/dt-plat.c | 189 --------------- .../roc-cc-rk3328/dt-structs-gen.h | 55 ----- .../of-platdata/rock-pi-e-rk3328/dt-decl.h | 24 -- .../of-platdata/rock-pi-e-rk3328/dt-plat.c | 189 --------------- .../rock-pi-e-rk3328/dt-structs-gen.h | 54 ----- .../src/of-platdata/rock64-rk3328/dt-decl.h | 27 --- .../src/of-platdata/rock64-rk3328/dt-plat.c | 219 ------------------ .../rock64-rk3328/dt-structs-gen.h | 63 ----- 28 files changed, 106 insertions(+), 2147 deletions(-) delete mode 100644 package/boot/uboot-rockchip/patches/001-scripts-remove-dependency-on-swig.patch delete mode 100644 package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch rename package/boot/uboot-rockchip/patches/{103-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch => 100-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch} (91%) delete mode 100644 package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch rename package/boot/uboot-rockchip/patches/{104-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch => 101-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch} (86%) delete mode 100644 package/boot/uboot-rockchip/patches/102-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R2C.patch delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-decl.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-decl.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-plat.c delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-structs-gen.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-decl.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-plat.c delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-structs-gen.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-decl.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-plat.c delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-structs-gen.h diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index cdaad7ce46..35eaf198be 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -5,13 +5,15 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2021.07 -PKG_RELEASE:=5 - -PKG_HASH:=312b7eeae44581d1362c3a3f02c28d806647756c82ba8c72241c7cdbe68ba77e +PKG_VERSION:=2023.07.02 +PKG_RELEASE:=1 +PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5 PKG_MAINTAINER:=Tobias Maedel +UBOOT_USE_BINMAN:=1 +UBOOT_USE_INTREE_DTC:=1 + include $(INCLUDE_DIR)/u-boot.mk include $(INCLUDE_DIR)/package.mk @@ -28,7 +30,6 @@ define U-Boot/rk3328/Default BUILD_SUBTARGET:=armv8 DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3328 ATF:=rk3328_bl31.elf - OF_PLATDATA:=$(1) endef define U-Boot/nanopi-r2c-rk3328 @@ -131,24 +132,15 @@ UBOOT_TARGETS := \ UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes +UBOOT_CUSTOMIZE_CONFIG := \ + --disable SPL_FIT_SIGNATURE \ + --disable TOOLS_MKEFICAPSULE \ + --set-str MKIMAGE_DTC_PATH $(PKG_BUILD_DIR)/scripts/dtc/dtc + UBOOT_MAKE_FLAGS += \ + PATH=$(STAGING_DIR_HOST)/bin:$(PATH) \ BL31=$(STAGING_DIR_IMAGE)/$(ATF) -define Build/Configure - $(call Build/Configure/U-Boot) - -ifneq ($(OF_PLATDATA),) - mkdir -p $(PKG_BUILD_DIR)/tpl/dts - mkdir -p $(PKG_BUILD_DIR)/include/generated - - $(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-plat.c $(PKG_BUILD_DIR)/tpl/dts/dt-plat.c - $(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-structs-gen.h $(PKG_BUILD_DIR)/include/generated/dt-structs-gen.h - $(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-decl.h $(PKG_BUILD_DIR)/include/generated/dt-decl.h -endif - - $(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config -endef - define Build/InstallDev $(INSTALL_DIR) $(STAGING_DIR_IMAGE) $(CP) $(PKG_BUILD_DIR)/idbloader.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-idbloader.img diff --git a/package/boot/uboot-rockchip/patches/001-scripts-remove-dependency-on-swig.patch b/package/boot/uboot-rockchip/patches/001-scripts-remove-dependency-on-swig.patch deleted file mode 100644 index 0505589385..0000000000 --- a/package/boot/uboot-rockchip/patches/001-scripts-remove-dependency-on-swig.patch +++ /dev/null @@ -1,24 +0,0 @@ -From b137ca16b54c67d76714ea5a0138741959b0dc29 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Mon, 13 Jul 2020 23:37:37 +0200 -Subject: [PATCH] scripts: remove dependency on swig - -Don't build the libfdt tool, as it has a dependency on swig (which -OpenWrt does not ship). - -This requires more hacks, as of-platdata generation does not work -without it. - -Signed-off-by: David Bauer ---- - scripts/dtc/Makefile | 2 -- - 1 file changed, 2 deletions(-) - ---- a/scripts/dtc/Makefile -+++ b/scripts/dtc/Makefile -@@ -18,5 +18,3 @@ HOSTCFLAGS_dtc-parser.tab.o := -I$(src) - # dependencies on generated files need to be listed explicitly - $(obj)/dtc-lexer.lex.o: $(obj)/dtc-parser.tab.h - --# Added for U-Boot --subdir-$(CONFIG_PYLIBFDT) += pylibfdt diff --git a/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch b/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch deleted file mode 100644 index 14bcbfb630..0000000000 --- a/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 55273cf6079ddd3b006da69f0113c2c66c03f17e Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Tue, 14 Jul 2020 22:44:22 +0200 -Subject: [PATCH] spl: remove dtoc of-pdata generation - -Remove the dtoc of-pdata generation. This generation is dependant on -libpython-dev. As OpenWrt does not ship with this dependency, use -pre-generated pdata files and remove the generation from the -build-process. - -This only affects RK3328 boards. - -Signed-off-by: David Bauer ---- - scripts/Makefile.spl | 6 ------ - 1 file changed, 6 deletions(-) - ---- a/scripts/Makefile.spl -+++ b/scripts/Makefile.spl -@@ -354,8 +354,6 @@ $(platdata-hdr) $(u-boot-spl-platdata_c) - @# of OF_PLATDATA_INST and this might change between builds. Leaving old - @# ones around is confusing and it is possible that switching the - @# setting again will use the old one instead of regenerating it. -- @rm -f $(u-boot-spl-all-platdata_c) $(u-boot-spl-all-platdata) -- $(call if_changed,dtoc) - - ifdef CONFIG_SAMSUNG - ifdef CONFIG_VAR_SIZE_SPL diff --git a/package/boot/uboot-rockchip/patches/103-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch similarity index 91% rename from package/boot/uboot-rockchip/patches/103-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch rename to package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch index ff17559c2f..487e6afda8 100644 --- a/package/boot/uboot-rockchip/patches/103-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch +++ b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch @@ -1,4 +1,4 @@ -From ff312af37d5f263f181468639aab83f645d331f1 Mon Sep 17 00:00:00 2001 +From 89afb631d965292aaf433806d8224b53d9e74036 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 20 May 2023 18:50:38 +0800 Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus @@ -27,7 +27,7 @@ Signed-off-by: Tianling Shen --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ +@@ -125,6 +125,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ rk3328-nanopi-r2c.dtb \ rk3328-nanopi-r2s.dtb \ @@ -53,24 +53,24 @@ Signed-off-by: Tianling Shen +}; + +&gpio0 { -+ u-boot,dm-spl; ++ bootph-pre-ram; +}; + +&pinctrl { -+ u-boot,dm-spl; ++ bootph-pre-ram; +}; + -+&sdmmc0m1_gpio { -+ u-boot,dm-spl; ++&sdmmc0m1_pin { ++ bootph-pre-ram; +}; + +&pcfg_pull_up_4ma { -+ u-boot,dm-spl; ++ bootph-pre-ram; +}; + +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { -+ u-boot,dm-spl; ++ bootph-pre-ram; +}; + +&gmac2io { @@ -81,12 +81,12 @@ Signed-off-by: Tianling Shen + +&spi0 { + spi_flash: spiflash@0 { -+ u-boot,dm-pre-reloc; ++ bootph-all; + }; +}; --- /dev/null +++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts -@@ -0,0 +1,359 @@ +@@ -0,0 +1,373 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Based on rk3328-nanopi-r2s.dts, which is: @@ -104,6 +104,7 @@ Signed-off-by: Tianling Shen + compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; + + aliases { ++ ethernet1 = &rtl8153; + mmc0 = &sdmmc; + }; + @@ -146,7 +147,7 @@ Signed-off-by: Tianling Shen + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&sdmmc0m1_gpio>; ++ pinctrl-0 = <&sdmmc0m1_pin>; + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-boot-on; @@ -439,6 +440,19 @@ Signed-off-by: Tianling Shen + status = "okay"; +}; + ++&usbdrd3 { ++ dr_mode = "host"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* Second port is for USB 3.0 */ ++ rtl8153: device@2 { ++ compatible = "usbbda,8153"; ++ reg = <2>; ++ }; ++}; ++ +&usb_host0_ehci { + status = "okay"; +}; @@ -463,39 +477,52 @@ Signed-off-by: Tianling Shen M: Chen-Yu Tsai --- /dev/null +++ b/configs/orangepi-r1-plus-rk3328_defconfig -@@ -0,0 +1,98 @@ +@@ -0,0 +1,114 @@ +CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_SPL_GPIO_SUPPORT=y ++CONFIG_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" ++CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y ++CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SPL_STACK=0x400000 ++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYSINFO=y ++CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb" -+CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_MISC_INIT_R=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y ++CONFIG_SPL_BSS_START_ADDR=0x2000000 ++CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_TPL_SYS_MALLOC_SIMPLE=y ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y -+CONFIG_SPL_I2C_SUPPORT=y -+CONFIG_SPL_POWER_SUPPORT=y ++CONFIG_SPL_I2C=y ++CONFIG_SPL_POWER=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y ++CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y @@ -504,11 +531,11 @@ Signed-off-by: Tianling Shen +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y @@ -526,13 +553,14 @@ Signed-off-by: Tianling Shen +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_DM_ETH=y ++CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y @@ -542,9 +570,11 @@ Signed-off-by: Tianling Shen +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y -+CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_ROCKCHIP_SPI=y ++CONFIG_SYSINFO=y +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y diff --git a/package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch b/package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch deleted file mode 100644 index 174c9ea29c..0000000000 --- a/package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 2114d68b3c755ec8043ae9e43ac8e9753e0cec84 Mon Sep 17 00:00:00 2001 -From: Marty Jones -Date: Sun, 17 Jan 2021 15:26:09 -0500 -Subject: [PATCH] rockpro64: disable CONFIG_USE_PREBOOT - -On commit https://github.com/u-boot/u-boot/commit/f81f9f0ebac596bae7f27db095f4f0272b606cc3 -CONFIG_USE_PREBOOT was enabled on the RockPro64. - -When the board is booting, U-Boot hangs as soon as it disables the USB -controller. This is a workaround until a final solution is deployed -upstream. - -Signed-off-by: Marty Jones ---- - configs/rockpro64-rk3399_defconfig | 1 - - 1 file changed, 1 deletion(-) - ---- a/configs/rockpro64-rk3399_defconfig -+++ b/configs/rockpro64-rk3399_defconfig -@@ -12,7 +12,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 - CONFIG_SPL_SPI_FLASH_SUPPORT=y - CONFIG_SPL_SPI_SUPPORT=y - CONFIG_DEBUG_UART=y --CONFIG_USE_PREBOOT=y - CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" - CONFIG_DISPLAY_BOARDINFO_LATE=y - CONFIG_MISC_INIT_R=y diff --git a/package/boot/uboot-rockchip/patches/104-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch b/package/boot/uboot-rockchip/patches/101-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch similarity index 86% rename from package/boot/uboot-rockchip/patches/104-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch rename to package/boot/uboot-rockchip/patches/101-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch index 05d569e720..56d36c74dc 100644 --- a/package/boot/uboot-rockchip/patches/104-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch +++ b/package/boot/uboot-rockchip/patches/101-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch @@ -1,4 +1,4 @@ -From 7a9326a96098bc63d2b60538f657c3a533415276 Mon Sep 17 00:00:00 2001 +From 408fd4570c0f1e6b1fe3722998394651144f2a29 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 20 May 2023 18:52:14 +0800 Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus LTS @@ -10,7 +10,6 @@ changed from DDR4 to LPDDR3. The device tree is taken from kernel v6.4-rc1. Signed-off-by: Tianling Shen - --- arch/arm/dts/Makefile | 1 + .../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 46 +++++++ @@ -24,7 +23,7 @@ Signed-off-by: Tianling Shen --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -111,6 +111,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ +@@ -126,6 +126,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-nanopi-r2c.dtb \ rk3328-nanopi-r2s.dtb \ rk3328-orangepi-r1-plus.dtb \ @@ -50,24 +49,24 @@ Signed-off-by: Tianling Shen +}; + +&gpio0 { -+ u-boot,dm-spl; ++ bootph-pre-ram; +}; + +&pinctrl { -+ u-boot,dm-spl; ++ bootph-pre-ram; +}; + -+&sdmmc0m1_gpio { -+ u-boot,dm-spl; ++&sdmmc0m1_pin { ++ bootph-pre-ram; +}; + +&pcfg_pull_up_4ma { -+ u-boot,dm-spl; ++ bootph-pre-ram; +}; + +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { -+ u-boot,dm-spl; ++ bootph-pre-ram; +}; + +&gmac2io { @@ -78,7 +77,7 @@ Signed-off-by: Tianling Shen + +&spi0 { + spi_flash: spiflash@0 { -+ u-boot,dm-pre-reloc; ++ bootph-all; + }; +}; --- /dev/null @@ -141,39 +140,52 @@ Signed-off-by: Tianling Shen M: Chen-Yu Tsai --- /dev/null +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig -@@ -0,0 +1,98 @@ +@@ -0,0 +1,114 @@ +CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_SPL_GPIO_SUPPORT=y ++CONFIG_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts" ++CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y ++CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SPL_STACK=0x400000 ++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYSINFO=y ++CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb" -+CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_MISC_INIT_R=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y ++CONFIG_SPL_BSS_START_ADDR=0x2000000 ++CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_TPL_SYS_MALLOC_SIMPLE=y ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y -+CONFIG_SPL_I2C_SUPPORT=y -+CONFIG_SPL_POWER_SUPPORT=y ++CONFIG_SPL_I2C=y ++CONFIG_SPL_POWER=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y ++CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y @@ -182,11 +194,11 @@ Signed-off-by: Tianling Shen +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y @@ -204,13 +216,14 @@ Signed-off-by: Tianling Shen +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_DM_ETH=y ++CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y @@ -220,9 +233,11 @@ Signed-off-by: Tianling Shen +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y -+CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_ROCKCHIP_SPI=y ++CONFIG_SYSINFO=y +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y diff --git a/package/boot/uboot-rockchip/patches/102-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R2C.patch b/package/boot/uboot-rockchip/patches/102-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R2C.patch deleted file mode 100644 index bc450b0dd4..0000000000 --- a/package/boot/uboot-rockchip/patches/102-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R2C.patch +++ /dev/null @@ -1,199 +0,0 @@ -From 7000a609473ffe14d32c656cdd0ff3ca0d3ecbd7 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Tue, 11 Apr 2023 18:14:49 +0800 -Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2C - -The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC -chip changed from rtl8211e to yt8521s, and otherwise identical to R2S. - -The device tree is taken from the kernel linux-next branch: -https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=004589ff9df5b75672a78b6c3c4cba93202b14c9 - -Signed-off-by: Tianling Shen -Reviewed-by: Kever Yang ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi | 3 + - arch/arm/dts/rk3328-nanopi-r2c.dts | 40 ++++++++ - board/rockchip/evb_rk3328/MAINTAINERS | 6 ++ - configs/nanopi-r2c-rk3328_defconfig | 112 +++++++++++++++++++++ - 5 files changed, 162 insertions(+) - create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi - create mode 100644 arch/arm/dts/rk3328-nanopi-r2c.dts - create mode 100644 configs/nanopi-r2c-rk3328_defconfig - ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ - - dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb \ -+ rk3328-nanopi-r2c.dtb \ - rk3328-nanopi-r2s.dtb \ - rk3328-roc-cc.dtb \ - rk3328-rock64.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi -@@ -0,0 +1,3 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+ -+#include "rk3328-nanopi-r2s-u-boot.dtsi" ---- /dev/null -+++ b/arch/arm/dts/rk3328-nanopi-r2c.dts -@@ -0,0 +1,40 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyarm.com) -+ * -+ * Copyright (c) 2021-2023 Tianling Shen -+ */ -+ -+/dts-v1/; -+#include "rk3328-nanopi-r2s.dts" -+ -+/ { -+ model = "FriendlyElec NanoPi R2C"; -+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; -+}; -+ -+&gmac2io { -+ phy-handle = <&yt8521s>; -+ tx_delay = <0x22>; -+ rx_delay = <0x12>; -+ -+ mdio { -+ /delete-node/ ethernet-phy@1; -+ -+ yt8521s: ethernet-phy@3 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <3>; -+ -+ motorcomm,clk-out-frequency-hz = <125000000>; -+ motorcomm,keep-pll-enabled; -+ motorcomm,auto-sleep-disabled; -+ -+ pinctrl-0 = <ð_phy_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; ---- a/board/rockchip/evb_rk3328/MAINTAINERS -+++ b/board/rockchip/evb_rk3328/MAINTAINERS -@@ -5,6 +5,12 @@ F: board/rockchip/evb_rk3328 - F: include/configs/evb_rk3328.h - F: configs/evb-rk3328_defconfig - -+NANOPI-R2C-RK3328 -+M: Tianling Shen -+S: Maintained -+F: configs/nanopi-r2c-rk3328_defconfig -+F: arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi -+ - NANOPI-R2S-RK3328 - M: David Bauer - S: Maintained ---- /dev/null -+++ b/configs/nanopi-r2c-rk3328_defconfig -@@ -0,0 +1,98 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_SPL_GPIO_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c" -+CONFIG_ROCKCHIP_RK3328=y -+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_TPL_LIBCOMMON_SUPPORT=y -+CONFIG_TPL_LIBGENERIC_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_DEBUG_UART_BASE=0xFF130000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 -+# CONFIG_ANDROID_BOOT_IMAGE is not set -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_MISC_INIT_R=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_TPL_SYS_MALLOC_SIMPLE=y -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_I2C_SUPPORT=y -+CONFIG_SPL_POWER_SUPPORT=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_TPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_TPL_OF_PLATDATA=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_TPL_DM=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_TPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_TPL_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_FASTBOOT_BUF_ADDR=0x800800 -+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_DM_REGULATOR=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSINFO=y -+CONFIG_SYSRESET=y -+# CONFIG_TPL_SYSRESET is not set -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC2=y -+CONFIG_USB_DWC3=y -+# CONFIG_USB_DWC3_GADGET is not set -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_DWC2_OTG=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_TPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h deleted file mode 100644 index 0919e4ed53..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c deleted file mode 100644 index e5b330c9d9..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: serial_at_ff130000 ns16550_serial - * 4: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x3a, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, - 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15, - 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0, - 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8, - 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8, - 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104, - 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114, - 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184, - 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, - 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c, - 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .sd_uhs_sdr104 = true, - .sd_uhs_sdr12 = true, - .sd_uhs_sdr25 = true, - .sd_uhs_sdr50 = true, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4b, - .vqmmc_supply = 0x1e, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 3 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x26, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* - * Node /syscon@ff100000 index 4 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h deleted file mode 100644 index b1ff08a927..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool sd_uhs_sdr104; - bool sd_uhs_sdr12; - bool sd_uhs_sdr25; - bool sd_uhs_sdr50; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; - fdt32_t vqmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-decl.h deleted file mode 100644 index 0919e4ed53..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-decl.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c deleted file mode 100644 index e5b330c9d9..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: serial_at_ff130000 ns16550_serial - * 4: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x3a, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, - 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15, - 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0, - 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8, - 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8, - 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104, - 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114, - 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184, - 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, - 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c, - 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .sd_uhs_sdr104 = true, - .sd_uhs_sdr12 = true, - .sd_uhs_sdr25 = true, - .sd_uhs_sdr50 = true, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4b, - .vqmmc_supply = 0x1e, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 3 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x26, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* - * Node /syscon@ff100000 index 4 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h deleted file mode 100644 index b1ff08a927..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool sd_uhs_sdr104; - bool sd_uhs_sdr12; - bool sd_uhs_sdr25; - bool sd_uhs_sdr50; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; - fdt32_t vqmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h deleted file mode 100644 index 75795aa6cc..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_spi); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c deleted file mode 100644 index 12081b19e0..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: serial_at_ff130000 ns16550_serial - * 4: spi_at_ff190000 rockchip_rk3328_spi - * 5: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x38, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10, - 0x10, 0x10, 0x0, 0x8c48a18a, 0x0, 0x21, 0x482, 0x15, - 0x21a, 0xff, 0x14d, 0x6, 0x1, 0x0, 0x0, 0x0, - 0x43041008, 0x64, 0x140023, 0xd0, 0x220002, 0xd4, 0x10000, 0xd8, - 0x703, 0xdc, 0x830004, 0xe0, 0x10000, 0xe4, 0x70003, 0xf4, - 0xf011f, 0x100, 0x6090b07, 0x104, 0x2020b, 0x108, 0x2030506, 0x10c, - 0x505000, 0x110, 0x3020204, 0x114, 0x1010303, 0x118, 0x2020003, 0x120, - 0x303, 0x138, 0x25, 0x180, 0x3c000f, 0x184, 0x900000, 0x190, - 0x7020000, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, 0x900090c, 0x244, - 0x101, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xb, 0x28, 0x6, 0x2c, - 0x0, 0x30, 0x3, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x45, 0x46, 0x47, 0x48}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x49, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 3 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x24, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* Node /spi@ff190000 index 4 */ -static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = { - .clocks = { - {0, {32}}, - {0, {209}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x8, 0x10, 0x9}, - .interrupts = {0x0, 0x31, 0x4}, - .pinctrl_0 = {0x2c, 0x2d, 0x2e, 0x2f}, - .pinctrl_names = "default", - .reg = {0xff190000, 0x1000}, -}; -U_BOOT_DRVINFO(spi_at_ff190000) = { - .name = "rockchip_rk3328_spi", - .plat = &dtv_spi_at_ff190000, - .plat_size = sizeof(dtv_spi_at_ff190000), - .parent_idx = -1, -}; - -/* - * Node /syscon@ff100000 index 5 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h deleted file mode 100644 index d095831531..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; -struct dtd_rockchip_rk3328_spi { - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; -}; diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h deleted file mode 100644 index 75795aa6cc..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_spi); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c deleted file mode 100644 index 90656fc306..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: serial_at_ff130000 ns16550_serial - * 4: spi_at_ff190000 rockchip_rk3328_spi - * 5: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x38, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, - 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15, - 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0, - 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8, - 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8, - 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104, - 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114, - 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184, - 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, - 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c, - 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x45, 0x46, 0x47, 0x48}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x49, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 3 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x24, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* Node /spi@ff190000 index 4 */ -static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = { - .clocks = { - {0, {32}}, - {0, {209}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x8, 0x10, 0x9}, - .interrupts = {0x0, 0x31, 0x4}, - .pinctrl_0 = {0x2c, 0x2d, 0x2e, 0x2f}, - .pinctrl_names = "default", - .reg = {0xff190000, 0x1000}, -}; -U_BOOT_DRVINFO(spi_at_ff190000) = { - .name = "rockchip_rk3328_spi", - .plat = &dtv_spi_at_ff190000, - .plat_size = sizeof(dtv_spi_at_ff190000), - .parent_idx = -1, -}; - -/* - * Node /syscon@ff100000 index 5 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h deleted file mode 100644 index d095831531..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; -struct dtd_rockchip_rk3328_spi { - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; -}; diff --git a/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-decl.h deleted file mode 100644 index 72675609cd..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-decl.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-plat.c deleted file mode 100644 index aa03298e58..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-plat.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: mmc_at_ff520000 rockchip_rk3288_dw_mshc - * 4: serial_at_ff130000 ns16550_serial - * 5: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x3a, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, - 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15, - 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0, - 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8, - 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8, - 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104, - 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114, - 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184, - 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, - 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c, - 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_mmc_highspeed = true, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .sd_uhs_sdr104 = true, - .sd_uhs_sdr12 = true, - .sd_uhs_sdr25 = true, - .sd_uhs_sdr50 = true, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4b, - .vqmmc_supply = 0x1e, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff520000 index 3 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = { - .bus_width = 0x8, - .cap_mmc_highspeed = true, - .clocks = { - {0, {319}}, - {0, {35}}, - {0, {76}}, - {0, {80}},}, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xe, 0x4}, - .max_frequency = 0x8f0d180, - .mmc_ddr_1_8v = true, - .mmc_hs200_1_8v = true, - .non_removable = true, - .pinctrl_0 = {0x4c, 0x4d, 0x4e, 0x0}, - .pinctrl_names = "default", - .reg = {0xff520000, 0x4000}, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x1c, - .vqmmc_supply = 0x1d, -}; -U_BOOT_DRVINFO(mmc_at_ff520000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff520000, - .plat_size = sizeof(dtv_mmc_at_ff520000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 4 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x26, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* - * Node /syscon@ff100000 index 5 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-structs-gen.h deleted file mode 100644 index 5b729fc57f..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_mmc_highspeed; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - bool mmc_ddr_1_8v; - bool mmc_hs200_1_8v; - bool non_removable; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool sd_uhs_sdr104; - bool sd_uhs_sdr12; - bool sd_uhs_sdr25; - bool sd_uhs_sdr50; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; - fdt32_t vqmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; diff --git a/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-decl.h deleted file mode 100644 index 72675609cd..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-decl.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-plat.c deleted file mode 100644 index f86414d5d3..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-plat.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: mmc_at_ff520000 rockchip_rk3288_dw_mshc - * 4: serial_at_ff130000 ns16550_serial - * 5: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x38, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10, - 0x10, 0x10, 0x0, 0x9028b189, 0x0, 0x21, 0x482, 0x15, - 0x222, 0xff, 0x14d, 0x3, 0x1, 0x0, 0x0, 0x0, - 0x43041001, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x20000, 0xd8, - 0x100, 0xdc, 0x3200000, 0xe0, 0x0, 0xe4, 0x90000, 0xf4, - 0xf011f, 0x100, 0x7090b06, 0x104, 0x50209, 0x108, 0x3030407, 0x10c, - 0x202006, 0x110, 0x3020204, 0x114, 0x3030202, 0x120, 0x903, 0x180, - 0x800020, 0x184, 0x0, 0x190, 0x7010001, 0x198, 0x5001100, 0x1a0, - 0xc0400003, 0x240, 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, - 0x1, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xa, 0x28, 0x6, 0x2c, - 0x0, 0x30, 0x5, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_mmc_highspeed = true, - .cap_sd_highspeed = true, - .card_detect_delay = 0xc8, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .num_slots = 0x1, - .pinctrl_0 = {0x45, 0x46, 0x47, 0x48}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .supports_sd = true, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x49, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff520000 index 3 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = { - .bus_width = 0x8, - .cap_mmc_highspeed = true, - .clocks = { - {0, {319}}, - {0, {35}}, - {0, {76}}, - {0, {80}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xe, 0x4}, - .max_frequency = 0x8f0d180, - .mmc_hs200_1_8v = true, - .non_removable = true, - .num_slots = 0x1, - .pinctrl_0 = {0x4a, 0x4b, 0x4c, 0x0}, - .pinctrl_names = "default", - .reg = {0xff520000, 0x4000}, - .supports_emmc = true, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x1c, - .vqmmc_supply = 0x1d, -}; -U_BOOT_DRVINFO(mmc_at_ff520000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff520000, - .plat_size = sizeof(dtv_mmc_at_ff520000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 4 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x24, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* - * Node /syscon@ff100000 index 5 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-structs-gen.h deleted file mode 100644 index fae089030b..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_mmc_highspeed; - bool cap_sd_highspeed; - fdt32_t card_detect_delay; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - bool mmc_hs200_1_8v; - bool non_removable; - fdt32_t num_slots; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool supports_emmc; - bool supports_sd; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; - fdt32_t vqmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; diff --git a/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-decl.h deleted file mode 100644 index a13aaea1fb..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-decl.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_spi); -extern U_BOOT_DRIVER(jedec_spi_nor); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(spi_flash); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-plat.c deleted file mode 100644 index 70a8c001a3..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-plat.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: mmc_at_ff520000 rockchip_rk3288_dw_mshc - * 4: serial_at_ff130000 ns16550_serial - * 5: spi_at_ff190000 rockchip_rk3328_spi - * 6: spiflash_at_0 jedec_spi_nor - * 7: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x3b, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10, - 0x10, 0x10, 0x0, 0x98899459, 0x0, 0x2e, 0x544, 0x15, - 0x432, 0xff, 0x320, 0x6, 0x1, 0x0, 0x1, 0x0, - 0x43041008, 0x64, 0x300054, 0xd0, 0x500002, 0xd4, 0x10000, 0xd8, - 0xe03, 0xdc, 0x43001a, 0xe0, 0x10000, 0xe4, 0xe0005, 0xf4, - 0xf011f, 0x100, 0xb141b11, 0x104, 0x3031a, 0x108, 0x3060809, 0x10c, - 0x606000, 0x110, 0x8020409, 0x114, 0x1010606, 0x118, 0x2020004, 0x120, - 0x404, 0x138, 0x58, 0x180, 0x900024, 0x184, 0x1400000, 0x190, - 0x7050002, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, 0xa020b28, 0x244, - 0x101, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xb, 0x28, 0xc, 0x2c, - 0x0, 0x30, 0x6, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_mmc_highspeed = true, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x4a, 0x4b, 0x4c, 0x4d}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4e, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff520000 index 3 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = { - .bus_width = 0x8, - .cap_mmc_highspeed = true, - .clocks = { - {0, {319}}, - {0, {35}}, - {0, {76}}, - {0, {80}},}, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xe, 0x4}, - .max_frequency = 0x8f0d180, - .mmc_hs200_1_8v = true, - .non_removable = true, - .pinctrl_0 = {0x4f, 0x50, 0x51, 0x0}, - .pinctrl_names = "default", - .reg = {0xff520000, 0x4000}, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x1e, - .vqmmc_supply = 0x1f, -}; -U_BOOT_DRVINFO(mmc_at_ff520000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff520000, - .plat_size = sizeof(dtv_mmc_at_ff520000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 4 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x27, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* Node /spi@ff190000 index 5 */ -static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = { - .clocks = { - {0, {32}}, - {0, {209}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x8, 0x10, 0x9}, - .interrupts = {0x0, 0x31, 0x4}, - .pinctrl_0 = {0x2f, 0x30, 0x31, 0x32}, - .pinctrl_names = "default", - .reg = {0xff190000, 0x1000}, -}; -U_BOOT_DRVINFO(spi_at_ff190000) = { - .name = "rockchip_rk3328_spi", - .plat = &dtv_spi_at_ff190000, - .plat_size = sizeof(dtv_spi_at_ff190000), - .parent_idx = -1, -}; - -/* - * Node /spi@ff190000/spiflash@0 index 6 - * driver jedec_spi_nor parent None - */ -static struct dtd_jedec_spi_nor dtv_spiflash_at_0 = { - .reg = {0x0}, - .spi_max_frequency = 0x2faf080, -}; -U_BOOT_DRVINFO(spiflash_at_0) = { - .name = "jedec_spi_nor", - .plat = &dtv_spiflash_at_0, - .plat_size = sizeof(dtv_spiflash_at_0), - .parent_idx = 5, -}; - -/* - * Node /syscon@ff100000 index 7 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-structs-gen.h deleted file mode 100644 index e15d848729..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_jedec_spi_nor { - fdt32_t reg[1]; - fdt32_t spi_max_frequency; -}; -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_mmc_highspeed; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - bool mmc_hs200_1_8v; - bool non_removable; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; - fdt32_t vqmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; -struct dtd_rockchip_rk3328_spi { - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; -}; From patchwork Tue Sep 12 14:42:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tianling Shen X-Patchwork-Id: 1833077 X-Patchwork-Delegate: mail@david-bauer.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=hEUBY/Ti; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RlRGM2zmRz1ygM for ; Wed, 13 Sep 2023 00:45:46 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type:List-Help: Reply-To:List-Archive:List-Unsubscribe:List-Subscribe:From:List-Post:List-Id: Message-ID:MIME-Version:References:In-Reply-To:Date:Subject:To:Cc: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9hYLs+ndF0sw6FlcL6aAnEHQR/JIy4Qfv1kC4Z7iB5E=; b=hEUBY/TiqJV4a5vX50GHAalu4+ nERfVGRpZXA9cq1m9Bmk5v6QEWLwkHR6p0SGkzlmueQUz/rcWivmW5oGgBMoEykGq0tWO8h6Jg4/O dA3MmHunZiyKT66paXr7jAEqK6bEqAUKYAQWnx4QV+lrsiB/tlbHoj3dVb2orMDp/hq6U4qtRW7xU tmKynwxsC83NXdQqPv39zjxnz46NUlejCzNw2UFMRLBSInh8KxHd8ySNiPGWacJIzAwMLsE7qjP1N S45PdgaoM22Np7cZ8beRsSLfgiorSRuqHRoJJmh6mDWw37CPEXFZrOoH+Ehfu2qX45411kPkNBZ26 7wXeP4Dg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qg4bn-003c9U-1L; Tue, 12 Sep 2023 14:43:19 +0000 To: openwrt-devel@lists.openwrt.org Subject: [PATCH 03/12] rkbin: add new TF-A package for rk35xx Date: Tue, 12 Sep 2023 22:42:31 +0800 In-Reply-To: <20230912144240.51396-1-cnsztl@immortalwrt.org> References: <20230912144240.51396-1-cnsztl@immortalwrt.org> MIME-Version: 1.0 Message-ID: List-Id: OpenWrt Development List List-Post: X-Patchwork-Original-From: Tianling Shen via openwrt-devel From: Tianling Shen Precedence: list X-Mailman-Version: 2.1.34 X-BeenThere: openwrt-devel@lists.openwrt.org List-Subscribe: , List-Unsubscribe: , List-Archive: Reply-To: Tianling Shen List-Help: Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software. Currently there's no usable mainline (open source) TF-A implementation for rk35xx SoCs, so pack the prebuilt firmware from the vendor. Signed-off-by: Tianling Shen --- package/boot/rkbin/Makefile | 47 +++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 package/boot/rkbin/Makefile diff --git a/package/boot/rkbin/Makefile b/package/boot/rkbin/Makefile new file mode 100644 index 0000000000..affdd7b4e1 --- /dev/null +++ b/package/boot/rkbin/Makefile @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2021-2023 ImmortalWrt.org + +include $(TOPDIR)/rules.mk + +PKG_NAME:=rkbin +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL=https://github.com/rockchip-linux/rkbin.git +PKG_SOURCE_DATE:=2023-07-26 +PKG_SOURCE_VERSION:=b4558da0860ca48bf1a571dd33ccba580b9abe23 +PKG_MIRROR_HASH:=5842fbcb7e217c336235573e431e427f2f745390d989f6765a6c258a5bdf1b6e + +PKG_LICENSE_FILES:=LICENSE +PKG_MAINTAINER:=Tianling Shen + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/trusted-firmware-a.mk +include $(INCLUDE_DIR)/package.mk + +define Trusted-Firmware-A/Default + NAME:=Rockchip $(1) SoCs + BUILD_TARGET:=rockchip +endef + +define Trusted-Firmware-A/rk3568 + BUILD_SUBTARGET:=armv8 + ATF:=rk35/rk3568_bl31_v1.43.elf + TPL:=rk35/rk3568_ddr_1560MHz_v1.18.bin +endef + +TFA_TARGETS:= \ + rk3568 + +define Build/Compile +endef + +define Package/trusted-firmware-a/install + $(INSTALL_DIR) $(STAGING_DIR_IMAGE) + + $(CP) $(PKG_BUILD_DIR)/bin/$(ATF) $(STAGING_DIR_IMAGE)/ + $(CP) $(PKG_BUILD_DIR)/bin/$(TPL) $(STAGING_DIR_IMAGE)/ +endef + +$(eval $(call BuildPackage/Trusted-Firmware-A)) From patchwork Tue Sep 12 14:42:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tianling Shen X-Patchwork-Id: 1833088 X-Patchwork-Delegate: mail@david-bauer.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=ClfKXls6; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RlRGv264Tz1yhm for ; Wed, 13 Sep 2023 00:46:15 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type:List-Help: Reply-To:List-Archive:List-Unsubscribe:List-Subscribe:From:List-Post:List-Id: Message-ID:MIME-Version:References:In-Reply-To:Date:Subject:To:Cc: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=5wI0gUxLOFRagY/J+KDjXdhCosMGFVZqsYqLtCLaGe0=; b=ClfKXls6sZ54YaPcvx2yFRC/IK uWvgybK+bXzjv0zGd7vnSJyZQiAa+zzVpVrDDPE2iuZjWp0OUly2SCBhVoyMndamhf1jFtZReZTD5 kD3KOwt+xsSFZGueYQxUB5cLqoYPzmF0Zjf+y6iU1UTX8A1TQwsvi+5cfIv/M3WOUaIuLmakEf9af yU42SICva/q+iXD2//7sm/kSWI8f4YuyCtv7cHUq6k34vXh76/UYtBBuxVsJbTyEo2fBa893DFWz6 6SdB4pGgo2jEf6+n2LarVkprB71Qeucs4Jtwa0XLmCySE3NeFyolRO8bbrsBq+tu3br9pdWmY5Anr IkU+iDZA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qg4c9-003cId-13; Tue, 12 Sep 2023 14:43:41 +0000 To: openwrt-devel@lists.openwrt.org Subject: [PATCH 04/12] rockchip: move image generation command to default Date: Tue, 12 Sep 2023 22:42:32 +0800 In-Reply-To: <20230912144240.51396-1-cnsztl@immortalwrt.org> References: <20230912144240.51396-1-cnsztl@immortalwrt.org> MIME-Version: 1.0 Message-ID: List-Id: OpenWrt Development List List-Post: X-Patchwork-Original-From: Tianling Shen via openwrt-devel From: Tianling Shen Precedence: list X-Mailman-Version: 2.1.34 X-BeenThere: openwrt-devel@lists.openwrt.org List-Subscribe: , List-Unsubscribe: , List-Archive: Reply-To: Tianling Shen List-Help: Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software. It's applicable for all devices so move it to default to reduce redudant code. Addtionally introduce a new variable `BOOT_SCRIPT` to allow custom boot script (if necessary). Signed-off-by: Tianling Shen --- target/linux/rockchip/image/Makefile | 2 ++ target/linux/rockchip/image/armv8.mk | 13 ------------- 2 files changed, 2 insertions(+), 13 deletions(-) diff --git a/target/linux/rockchip/image/Makefile b/target/linux/rockchip/image/Makefile index 3b118201b6..d34948f6ae 100644 --- a/target/linux/rockchip/image/Makefile +++ b/target/linux/rockchip/image/Makefile @@ -48,7 +48,9 @@ endef define Device/Default PROFILES := Default KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb + BOOT_SCRIPT := IMAGES := sysupgrade.img.gz + IMAGE/sysupgrade.img.gz = boot-common | boot-script $$(BOOT_SCRIPT) | pine64-img | gzip | append-metadata DEVICE_DTS = rockchip/$$(SOC)-$(lastword $(subst _, ,$(1))) UBOOT_DEVICE_NAME = $(lastword $(subst _, ,$(1)))-$$(SOC) endef diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index dd6a2d5bfe..608ad79ca4 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -11,7 +11,6 @@ define Device/firefly_roc-rk3328-cc SOC := rk3328 DEVICE_DTS := rockchip/rk3328-roc-cc UBOOT_DEVICE_NAME := roc-cc-rk3328 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata endef TARGET_DEVICES += firefly_roc-rk3328-cc @@ -19,7 +18,6 @@ define Device/friendlyarm_nanopc-t4 DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPC T4 SOC := rk3399 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata DEVICE_PACKAGES := kmod-brcmfmac brcmfmac-nvram-4356-sdio cypress-firmware-4356-sdio endef TARGET_DEVICES += friendlyarm_nanopc-t4 @@ -28,7 +26,6 @@ define Device/friendlyarm_nanopi-r2c DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPi R2C SOC := rk3328 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata DEVICE_PACKAGES := kmod-usb-net-rtl8152 endef TARGET_DEVICES += friendlyarm_nanopi-r2c @@ -37,7 +34,6 @@ define Device/friendlyarm_nanopi-r2s DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPi R2S SOC := rk3328 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata DEVICE_PACKAGES := kmod-usb-net-rtl8152 endef TARGET_DEVICES += friendlyarm_nanopi-r2s @@ -47,7 +43,6 @@ define Device/friendlyarm_nanopi-r4s DEVICE_MODEL := NanoPi R4S DEVICE_VARIANT := 4GB LPDDR4 SOC := rk3399 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata DEVICE_PACKAGES := kmod-r8169 endef TARGET_DEVICES += friendlyarm_nanopi-r4s @@ -56,8 +51,6 @@ define Device/pine64_rock64 DEVICE_VENDOR := Pine64 DEVICE_MODEL := Rock64 SOC := rk3328 - UBOOT_DEVICE_NAME := rock64-rk3328 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata endef TARGET_DEVICES += pine64_rock64 @@ -65,7 +58,6 @@ define Device/pine64_rockpro64 DEVICE_VENDOR := Pine64 DEVICE_MODEL := RockPro64 SOC := rk3399 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata endef TARGET_DEVICES += pine64_rockpro64 @@ -75,7 +67,6 @@ define Device/radxa_rock-pi-4a SOC := rk3399 SUPPORTED_DEVICES := radxa,rockpi4a radxa,rockpi4 UBOOT_DEVICE_NAME := rock-pi-4-rk3399 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata endef TARGET_DEVICES += radxa_rock-pi-4a @@ -83,8 +74,6 @@ define Device/radxa_rock-pi-e DEVICE_VENDOR := Radxa DEVICE_MODEL := ROCK Pi E SOC := rk3328 - UBOOT_DEVICE_NAME := rock-pi-e-rk3328 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata endef TARGET_DEVICES += radxa_rock-pi-e @@ -92,7 +81,6 @@ define Device/xunlong_orangepi-r1-plus DEVICE_VENDOR := Xunlong DEVICE_MODEL := Orange Pi R1 Plus SOC := rk3328 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata DEVICE_PACKAGES := kmod-usb-net-rtl8152 endef TARGET_DEVICES += xunlong_orangepi-r1-plus @@ -101,7 +89,6 @@ define Device/xunlong_orangepi-r1-plus-lts DEVICE_VENDOR := Xunlong DEVICE_MODEL := Orange Pi R1 Plus LTS SOC := rk3328 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata DEVICE_PACKAGES := kmod-usb-net-rtl8152 endef TARGET_DEVICES += xunlong_orangepi-r1-plus-lts From patchwork Tue Sep 12 14:42:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tianling Shen X-Patchwork-Id: 1833081 X-Patchwork-Delegate: mail@david-bauer.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=XJ7A658O; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RlRGV0psgz1ygM for ; Wed, 13 Sep 2023 00:45:54 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type:List-Help: Reply-To:List-Archive:List-Unsubscribe:List-Subscribe:From:List-Post:List-Id: Message-ID:MIME-Version:References:In-Reply-To:Date:Subject:To:Cc: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=hNRbe4O1RaN3zPrvvDO/zNLCItYdf5+NLzV5R5TWibo=; b=XJ7A658OyePSytvm6BhpTdvSe2 0bs5FpKZpNYdOzw7YTFEjhPJTmpGdgLYUdfEU8q3XrPYXcGf1V6krDcbzf81ZUWLPNS4Q3e6GNr1b tjC+bqURHpPZpS+Uk1zqqxJOh9cbGqeamFaYmXOHEw+Qg088Iv5cXCnioEtGB4+PeNyQVC+xKFbFa AOnSlNPWRzJkwSlyMfTV6QrGHQLXqowtKrhOO+QL0Decv/lLE6ujl1ArIhxk3lpW9O4GZn1HqavZl +sZJ+oHgXvtFY7QJWDCLXrUJhUJh3dyDSb28C5B5W0vWwW9E8Q7jgNaI0KDHvzXf62H8aFuAlEbbt C907DsZw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qg4c0-003cD6-1c; Tue, 12 Sep 2023 14:43:32 +0000 To: openwrt-devel@lists.openwrt.org Subject: [PATCH 05/12] rockchip: switch to kernel 6.1 Date: Tue, 12 Sep 2023 22:42:33 +0800 In-Reply-To: <20230912144240.51396-1-cnsztl@immortalwrt.org> References: <20230912144240.51396-1-cnsztl@immortalwrt.org> MIME-Version: 1.0 Message-ID: List-Id: OpenWrt Development List List-Post: X-Patchwork-Original-From: Tianling Shen via openwrt-devel From: Tianling Shen Precedence: list X-Mailman-Version: 2.1.34 X-BeenThere: openwrt-devel@lists.openwrt.org List-Subscribe: , List-Unsubscribe: , List-Archive: Reply-To: Tianling Shen List-Help: Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software. Required by the following rk3568 support. Signed-off-by: Tianling Shen --- target/linux/rockchip/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/linux/rockchip/Makefile b/target/linux/rockchip/Makefile index f17f0bdf49..42d75e3b4f 100644 --- a/target/linux/rockchip/Makefile +++ b/target/linux/rockchip/Makefile @@ -7,8 +7,7 @@ BOARDNAME:=Rockchip FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs SUBTARGETS:=armv8 -KERNEL_PATCHVER:=5.15 -KERNEL_TESTING_PATCHVER:=6.1 +KERNEL_PATCHVER:=6.1 define Target/Description Build firmware image for Rockchip SoC devices. From patchwork Tue Sep 12 14:42:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tianling Shen X-Patchwork-Id: 1833085 X-Patchwork-Delegate: mail@david-bauer.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=UPH4Pg4v; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RlRGm5pnqz1yhm for ; Wed, 13 Sep 2023 00:46:08 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type:List-Help: Reply-To:List-Archive:List-Unsubscribe:List-Subscribe:From:List-Post:List-Id: Message-ID:MIME-Version:References:In-Reply-To:Date:Subject:To:Cc: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=bydpBxwUbgtDQBzuJDF0CpwvLisioX0bQC1mm3ETfmY=; b=UPH4Pg4vjsyjgHao41hhRh7eND W4tgvwl2hhanj+frDvhrlHKmL6ZUOYcmKxRmxOW11qbyetrx338KWJQnuPRTZqApejGIMCMsSefJv CJLi9SJojxd4cyyn4XL1MChaZYZX94YmbCtQqT0zvJAC7AeTcfwEf9C5zMffFN3IPv/4XGw1XV/Ni /O0hF+Gp/oZunpP0LQQaUoT8HAISbSnuZAgQUtKsUjBX+zpb3OcdgyW281hajbm26f4kQxKHX2fbd 2Msaz13befCtPCQRlXBc/wYEisK8UCUUiAG861wLiTC7b5ZjEjAYKODh3uLll8MXHDth3+MKemLkT 0szHrU5A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qg4c3-003cES-0B; Tue, 12 Sep 2023 14:43:35 +0000 To: openwrt-devel@lists.openwrt.org Subject: [PATCH 06/12] rockchip: remove kernel 5.15 patches and config Date: Tue, 12 Sep 2023 22:42:34 +0800 In-Reply-To: <20230912144240.51396-1-cnsztl@immortalwrt.org> References: <20230912144240.51396-1-cnsztl@immortalwrt.org> MIME-Version: 1.0 Message-ID: List-Id: OpenWrt Development List List-Post: X-Patchwork-Original-From: Tianling Shen via openwrt-devel From: Tianling Shen Precedence: list X-Mailman-Version: 2.1.34 X-BeenThere: openwrt-devel@lists.openwrt.org List-Subscribe: , List-Unsubscribe: , List-Archive: Reply-To: Tianling Shen List-Help: Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software. As we switched to kernel 6.1, these files can go. Signed-off-by: Tianling Shen --- target/linux/rockchip/armv8/config-5.15 | 644 ------------------ ...kchip-add-EEPROM-node-for-NanoPi-R4S.patch | 31 - ...-rockchip-Add-FriendlyARM-NanoPi-R2C.patch | 70 -- ...ockchip-rk3328-Add-Orange-Pi-R1-Plus.patch | 407 ----------- ...hip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch | 71 -- ...-rockchip-use-system-LED-for-OpenWrt.patch | 65 -- ...dd-OF-node-for-USB-eth-on-NanoPi-R2S.patch | 24 - .../105-nanopi-r4s-sd-signalling.patch | 36 - .../patches-5.15/106-r4s-openwrt-leds.patch | 16 - ...ip-Update-LED-properties-for-Orange-.patch | 56 -- ...ip-add-LED-configuration-to-Orange-P.patch | 24 - .../109-nanopc-t4-add-led-aliases.patch | 16 - 12 files changed, 1460 deletions(-) delete mode 100644 target/linux/rockchip/armv8/config-5.15 delete mode 100644 target/linux/rockchip/patches-5.15/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch delete mode 100644 target/linux/rockchip/patches-5.15/006-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch delete mode 100644 target/linux/rockchip/patches-5.15/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch delete mode 100644 target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch delete mode 100644 target/linux/rockchip/patches-5.15/100-rockchip-use-system-LED-for-OpenWrt.patch delete mode 100644 target/linux/rockchip/patches-5.15/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch delete mode 100644 target/linux/rockchip/patches-5.15/105-nanopi-r4s-sd-signalling.patch delete mode 100644 target/linux/rockchip/patches-5.15/106-r4s-openwrt-leds.patch delete mode 100644 target/linux/rockchip/patches-5.15/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch delete mode 100644 target/linux/rockchip/patches-5.15/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch delete mode 100644 target/linux/rockchip/patches-5.15/109-nanopc-t4-add-led-aliases.patch diff --git a/target/linux/rockchip/armv8/config-5.15 b/target/linux/rockchip/armv8/config-5.15 deleted file mode 100644 index 08ce65d8ea..0000000000 --- a/target/linux/rockchip/armv8/config-5.15 +++ /dev/null @@ -1,644 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=33 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_ROCKCHIP=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARC_EMAC_CORE=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_CNP=y -CONFIG_ARM64_CRYPTO=y -CONFIG_ARM64_EPAN=y -CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_824069=y -CONFIG_ARM64_ERRATUM_826319=y -CONFIG_ARM64_ERRATUM_827319=y -CONFIG_ARM64_ERRATUM_832075=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_845719=y -CONFIG_ARM64_ERRATUM_858921=y -CONFIG_ARM64_ERRATUM_1742098=y -CONFIG_ARM64_HW_AFDBM=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PAN=y -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_PTR_AUTH=y -CONFIG_ARM64_PTR_AUTH_KERNEL=y -CONFIG_ARM64_RAS_EXTN=y -CONFIG_ARM64_SVE=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=48 -# CONFIG_ARM64_VA_BITS_39 is not set -CONFIG_ARM64_VA_BITS_48=y -CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y -# CONFIG_ARMV8_DEPRECATED is not set -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_MHU=y -CONFIG_ARM_MHU_V2=y -CONFIG_ARM_PSCI_CPUIDLE=y -CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set -CONFIG_ARM_SCPI_CPUFREQ=y -CONFIG_ARM_SCPI_POWER_DOMAIN=y -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_ARM_SMMU=y -CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y -# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set -CONFIG_ARM_SMMU_V3=y -# CONFIG_ARM_SMMU_V3_SVA is not set -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GPIO=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_BSGLIB=y -CONFIG_BLK_DEV_BSG_COMMON=y -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLK_DEV_INTEGRITY_T10=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NVME=y -CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BLOCK_COMPAT=y -CONFIG_BRCMSTB_GISB_ARB=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CHARGER_GPIO=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLK_PX30=y -CONFIG_CLK_RK3308=y -CONFIG_CLK_RK3328=y -CONFIG_CLK_RK3368=y -CONFIG_CLK_RK3399=y -CONFIG_CLK_RK3568=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=5 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -# CONFIG_CMA_SYSFS is not set -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_RK808=y -CONFIG_COMMON_CLK_ROCKCHIP=y -CONFIG_COMMON_CLK_SCPI=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTIG_ALLOC=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_ISOLATION=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRASH_CORE=y -CONFIG_CRASH_DUMP=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRC_T10DIF=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y -CONFIG_CRYPTO_CRYPTD=y -# CONFIG_CRYPTO_DEV_ROCKCHIP is not set -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SIMD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEVFREQ_GOV_PASSIVE is not set -CONFIG_DEVFREQ_GOV_PERFORMANCE=y -CONFIG_DEVFREQ_GOV_POWERSAVE=y -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -CONFIG_DEVFREQ_GOV_USERSPACE=y -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DEVMEM=y -# CONFIG_DEVPORT is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_CMA=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -CONFIG_DT_IDLE_STATES=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_DWMAC_DWC_QOS_ETH=y -CONFIG_DWMAC_GENERIC=y -CONFIG_DWMAC_ROCKCHIP=y -CONFIG_DW_WATCHDOG=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_AT24=y -CONFIG_EMAC_ROCKCHIP=y -CONFIG_ENERGY_MODEL=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FANOTIFY=y -CONFIG_FHANDLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -# CONFIG_FORTIFY_SOURCE is not set -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_FIND_FIRST_BIT=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_DWAPB=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GPIO_ROCKCHIP=y -CONFIG_GPIO_SYSCON=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HID=y -CONFIG_HID_GENERIC=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HOTPLUG_PCI=y -# CONFIG_HOTPLUG_PCI_CPCI is not set -# CONFIG_HOTPLUG_PCI_PCIE is not set -# CONFIG_HOTPLUG_PCI_SHPC is not set -CONFIG_HUGETLBFS=y -CONFIG_HUGETLB_PAGE=y -CONFIG_HWMON=y -CONFIG_HWSPINLOCK=y -CONFIG_HW_CONSOLE=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_RK3X=y -CONFIG_IIO=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INDIRECT_PIO=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_LEDS=y -CONFIG_INPUT_MATRIXKMAP=y -# CONFIG_INPUT_RK805_PWRKEY is not set -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y -CONFIG_IOMMU_DMA=y -CONFIG_IOMMU_IOVA=y -CONFIG_IOMMU_IO_PGTABLE=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -CONFIG_IOMMU_IO_PGTABLE_LPAE=y -# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set -CONFIG_IOMMU_SUPPORT=y -# CONFIG_IO_STRICT_DEVMEM is not set -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MSI_IOMMU=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JFFS2_ZLIB=y -CONFIG_JUMP_LABEL=y -CONFIG_KALLSYMS=y -CONFIG_KCMP=y -CONFIG_KEXEC_CORE=y -CONFIG_KEXEC_FILE=y -CONFIG_KSM=y -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_LIBCRC32C=y -CONFIG_LIBFDT=y -CONFIG_LOCALVERSION_AUTO=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOG_BUF_SHIFT=19 -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAGIC_SYSRQ_SERIAL=y -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_BUS_MUX=y -CONFIG_MDIO_BUS_MUX_GPIO=y -CONFIG_MDIO_BUS_MUX_MMIOREG=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_MFD_CORE=y -# CONFIG_MFD_KHADAS_MCU is not set -CONFIG_MFD_RK808=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_CQHCI=y -CONFIG_MMC_DW=y -# CONFIG_MMC_DW_BLUEFIELD is not set -# CONFIG_MMC_DW_EXYNOS is not set -# CONFIG_MMC_DW_HI3798CV200 is not set -# CONFIG_MMC_DW_K3 is not set -# CONFIG_MMC_DW_PCI is not set -CONFIG_MMC_DW_PLTFM=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_OF_ARASAN=y -CONFIG_MMC_SDHCI_OF_DWCMSHC=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MOTORCOMM_PHY=y -CONFIG_MQ_IOSCHED_DEADLINE=y -# CONFIG_MTD_CFI is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SELFTESTS=y -CONFIG_NLS=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=256 -CONFIG_NVMEM=y -CONFIG_NVMEM_ROCKCHIP_EFUSE=y -# CONFIG_NVMEM_ROCKCHIP_OTP is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_NVME_CORE=y -# CONFIG_NVME_HWMON is not set -# CONFIG_NVME_MULTIPATH is not set -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_OLD_SIGSUSPEND3=y -# CONFIG_OVERLAY_FS_XINO_AUTO is not set -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_PME=y -CONFIG_PCIE_ROCKCHIP=y -CONFIG_PCIE_ROCKCHIP_DW_HOST=y -CONFIG_PCIE_ROCKCHIP_HOST=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_STUB=y -CONFIG_PCS_XPCS=y -CONFIG_PGTABLE_LEVELS=4 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_ROCKCHIP_DP=y -# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set -CONFIG_PHY_ROCKCHIP_EMMC=y -# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set -# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set -# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set -CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_PCIE=y -CONFIG_PHY_ROCKCHIP_TYPEC=y -CONFIG_PHY_ROCKCHIP_USB=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_RK805=y -CONFIG_PINCTRL_ROCKCHIP=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PL330_DMA=y -CONFIG_PLATFORM_MHU=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_DEVFREQ=y -# CONFIG_PM_DEVFREQ_EVENT is not set -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_PPS=y -CONFIG_PREEMPT=y -CONFIG_PREEMPTION=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y -CONFIG_PRINTK_TIME=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PROC_VMCORE=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_ROCKCHIP=y -CONFIG_PWM_SYSFS=y -# CONFIG_QFMT_V2 is not set -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_QUOTA=y -CONFIG_QUOTACTL=y -CONFIG_RAID_ATTRS=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_RANDOMIZE_MODULE_REGION_FULL=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_RCU_TRACE=y -CONFIG_REALTEK_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_IRQ=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_RK808=y -CONFIG_RELOCATABLE=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_ROCKCHIP_GRF=y -CONFIG_ROCKCHIP_IODOMAIN=y -CONFIG_ROCKCHIP_IOMMU=y -CONFIG_ROCKCHIP_MBOX=y -CONFIG_ROCKCHIP_PHY=y -CONFIG_ROCKCHIP_PM_DOMAINS=y -# CONFIG_ROCKCHIP_SARADC is not set -CONFIG_ROCKCHIP_THERMAL=y -CONFIG_ROCKCHIP_TIMER=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RSEQ=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_RK808=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_NVMEM=y -# CONFIG_RUNTIME_TESTING_MENU is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_PROC_FS is not set -CONFIG_SCSI_SAS_ATTRS=y -CONFIG_SCSI_SAS_HOST_SMP=y -CONFIG_SCSI_SAS_LIBSAS=y -# CONFIG_SECURITY_DMESG_RESTRICT is not set -CONFIG_SENSORS_ARM_SCPI=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_8250_EXAR=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIO=y -CONFIG_SERIO_AMBAKMI=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SG_POOL=y -CONFIG_SLUB_DEBUG=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_ROCKCHIP=y -# CONFIG_SPI_ROCKCHIP_SFC is not set -CONFIG_SPI_SPIDEV=y -# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set -CONFIG_SQUASHFS_DECOMP_SINGLE=y -# CONFIG_SQUASHFS_EMBEDDED is not set -CONFIG_SQUASHFS_FILE_CACHE=y -# CONFIG_SQUASHFS_FILE_DIRECT is not set -CONFIG_SRAM=y -CONFIG_SRCU=y -CONFIG_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR_PER_TASK=y -CONFIG_STACKPROTECTOR_STRONG=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -CONFIG_STRICT_DEVMEM=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_SWAP is not set -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYNC_FILE=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_SYSVIPC_COMPAT=y -# CONFIG_TEXTSEARCH is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_EMULATION=y -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TRACE_CLOCK=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y -# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_TYPEC=y -# CONFIG_TYPEC_DP_ALTMODE is not set -CONFIG_TYPEC_FUSB302=y -# CONFIG_TYPEC_HD3SS3220 is not set -# CONFIG_TYPEC_MUX_PI3USB30532 is not set -# CONFIG_TYPEC_STUSB160X is not set -# CONFIG_TYPEC_TCPCI is not set -CONFIG_TYPEC_TCPM=y -# CONFIG_TYPEC_TPS6598X is not set -# CONFIG_UACCE is not set -# CONFIG_UCLAMP_TASK is not set -# CONFIG_UEVENT_HELPER is not set -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_HOST=y -CONFIG_USB_DWC3_OF_SIMPLE=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_HID=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_ULPI_BUS=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PLATFORM=y -# CONFIG_VIRTIO_MENU is not set -CONFIG_VMAP_STACK=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XARRAY_MULTI=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/rockchip/patches-5.15/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch b/target/linux/rockchip/patches-5.15/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch deleted file mode 100644 index 792028b292..0000000000 --- a/target/linux/rockchip/patches-5.15/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch +++ /dev/null @@ -1,31 +0,0 @@ -From af20b3384e8723077cc6484160b0cf4e9be321de Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Mon, 7 Jun 2021 15:45:37 +0800 -Subject: [PATCH] arm64: dts: rockchip: add EEPROM node for NanoPi R4S - -NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which -stores the MAC address. - -Signed-off-by: Tianling Shen ---- - arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -68,6 +68,15 @@ - status = "disabled"; - }; - -+&i2c2 { -+ eeprom@51 { -+ compatible = "microchip,24c02", "atmel,24c02"; -+ reg = <0x51>; -+ pagesize = <16>; -+ read-only; /* This holds our MAC */ -+ }; -+}; -+ - &i2c4 { - status = "disabled"; - }; diff --git a/target/linux/rockchip/patches-5.15/006-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch b/target/linux/rockchip/patches-5.15/006-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch deleted file mode 100644 index f58463b3d1..0000000000 --- a/target/linux/rockchip/patches-5.15/006-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 004589ff9df5b75672a78b6c3c4cba93202b14c9 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Sat, 25 Mar 2023 15:40:20 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C - -The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC -chip changed from rtl8211e to yt8521s, and otherwise identical to R2S. - -Signed-off-by: Tianling Shen -Link: https://lore.kernel.org/r/20230325074022.9818-3-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3328-nanopi-r2c.dts | 40 +++++++++++++++++++ - 2 files changed, 41 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9 - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts -@@ -0,0 +1,40 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyarm.com) -+ * -+ * Copyright (c) 2021-2023 Tianling Shen -+ */ -+ -+/dts-v1/; -+#include "rk3328-nanopi-r2s.dts" -+ -+/ { -+ model = "FriendlyElec NanoPi R2C"; -+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; -+}; -+ -+&gmac2io { -+ phy-handle = <&yt8521s>; -+ tx_delay = <0x22>; -+ rx_delay = <0x12>; -+ -+ mdio { -+ /delete-node/ ethernet-phy@1; -+ -+ yt8521s: ethernet-phy@3 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <3>; -+ -+ motorcomm,clk-out-frequency-hz = <125000000>; -+ motorcomm,keep-pll-enabled; -+ motorcomm,auto-sleep-disabled; -+ -+ pinctrl-0 = <ð_phy_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; diff --git a/target/linux/rockchip/patches-5.15/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch b/target/linux/rockchip/patches-5.15/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch deleted file mode 100644 index 053a4d0d8e..0000000000 --- a/target/linux/rockchip/patches-5.15/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch +++ /dev/null @@ -1,407 +0,0 @@ -From 51712e1d014aaaa4c6e1e7e84932d58b5c0f59ed Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sat, 3 Dec 2022 15:41:49 +0800 -Subject: [PATCH] arm64: dts: rockchip: rk3328: Add Orange Pi R1 Plus - -Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong. - -This device is similar to the NanoPi R2S, and has a 16MB -SPI NOR (mx25l12805d). The reset button is changed to -directly reset the power supply, another detail is that -both network ports have independent MAC addresses. - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20221203074149.11543-3-amadeus@jmu.edu.cn -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++ - 2 files changed, 374 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1 - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -@@ -0,0 +1,373 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Based on rk3328-nanopi-r2s.dts, which is: -+ * Copyright (c) 2020 David Bauer -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include "rk3328.dtsi" -+ -+/ { -+ model = "Xunlong Orange Pi R1 Plus"; -+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; -+ -+ aliases { -+ ethernet1 = &rtl8153; -+ mmc0 = &sdmmc; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ gmac_clk: gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "gmac_clkin"; -+ #clock-cells = <0>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -+ pinctrl-names = "default"; -+ -+ led-0 { -+ function = LED_FUNCTION_LAN; -+ color = ; -+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ led-1 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led-2 { -+ function = LED_FUNCTION_WAN; -+ color = ; -+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ vcc_sd: sdmmc-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&sdmmc0m1_pin>; -+ pinctrl-names = "default"; -+ regulator-name = "vcc_sd"; -+ regulator-boot-on; -+ vin-supply = <&vcc_io>; -+ }; -+ -+ vcc_sys: vcc-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vdd_5v_lan: vdd-5v-lan-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-0 = <&lan_vdd_pin>; -+ pinctrl-names = "default"; -+ regulator-name = "vdd_5v_lan"; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc_sys>; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&display_subsystem { -+ status = "disabled"; -+}; -+ -+&gmac2io { -+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; -+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; -+ clock_in_out = "input"; -+ phy-handle = <&rtl8211e>; -+ phy-mode = "rgmii"; -+ phy-supply = <&vcc_io>; -+ pinctrl-0 = <&rgmiim1_pins>; -+ pinctrl-names = "default"; -+ snps,aal; -+ rx_delay = <0x18>; -+ tx_delay = <0x24>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rtl8211e: ethernet-phy@1 { -+ reg = <1>; -+ pinctrl-0 = <ð_phy_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ status = "okay"; -+ -+ rk805: pmic@18 { -+ compatible = "rockchip,rk805"; -+ reg = <0x18>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk805-clkout2"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ pinctrl-0 = <&pmic_int_l>; -+ pinctrl-names = "default"; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc_sys>; -+ vcc2-supply = <&vcc_sys>; -+ vcc3-supply = <&vcc_sys>; -+ vcc4-supply = <&vcc_sys>; -+ vcc5-supply = <&vcc_io>; -+ vcc6-supply = <&vcc_sys>; -+ -+ regulators { -+ vdd_log: DCDC_REG1 { -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ -+ vdd_arm: DCDC_REG2 { -+ regulator-name = "vdd_arm"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <950000>; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_io: DCDC_REG4 { -+ regulator-name = "vcc_io"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc_18: LDO_REG1 { -+ regulator-name = "vcc_18"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc18_emmc: LDO_REG2 { -+ regulator-name = "vcc18_emmc"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_10: LDO_REG3 { -+ regulator-name = "vdd_10"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&io_domains { -+ pmuio-supply = <&vcc_io>; -+ vccio1-supply = <&vcc_io>; -+ vccio2-supply = <&vcc18_emmc>; -+ vccio3-supply = <&vcc_io>; -+ vccio4-supply = <&vcc_io>; -+ vccio5-supply = <&vcc_io>; -+ vccio6-supply = <&vcc_io>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ gmac2io { -+ eth_phy_reset_pin: eth-phy-reset-pin { -+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ leds { -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ sys_led_pin: sys-led-pin { -+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ lan { -+ lan_vdd_pin: lan-vdd-pin { -+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ disable-wp; -+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; -+ pinctrl-names = "default"; -+ vmmc-supply = <&vcc_sd>; -+ status = "okay"; -+}; -+ -+&spi0 { -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <50000000>; -+ }; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <0>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&u2phy { -+ status = "okay"; -+}; -+ -+&u2phy_host { -+ status = "okay"; -+}; -+ -+&u2phy_otg { -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb20_otg { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usbdrd3 { -+ dr_mode = "host"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* Second port is for USB 3.0 */ -+ rtl8153: device@2 { -+ compatible = "usbbda,8153"; -+ reg = <2>; -+ }; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch b/target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch deleted file mode 100644 index cedf28dc79..0000000000 --- a/target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Sat, 25 Mar 2023 15:40:22 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS - -The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with -the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise -identical to OrangePi R1 Plus. - -Signed-off-by: Tianling Shen -Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../rockchip/rk3328-orangepi-r1-plus-lts.dts | 40 +++++++++++++++++++ - 2 files changed, 41 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts -@@ -0,0 +1,40 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Copyright (c) 2016 Xunlong Software. Co., Ltd. -+ * (http://www.orangepi.org) -+ * -+ * Copyright (c) 2021-2023 Tianling Shen -+ */ -+ -+/dts-v1/; -+#include "rk3328-orangepi-r1-plus.dts" -+ -+/ { -+ model = "Xunlong Orange Pi R1 Plus LTS"; -+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; -+}; -+ -+&gmac2io { -+ phy-handle = <&yt8531c>; -+ tx_delay = <0x19>; -+ rx_delay = <0x05>; -+ -+ mdio { -+ /delete-node/ ethernet-phy@1; -+ -+ yt8531c: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ -+ motorcomm,clk-out-frequency-hz = <125000000>; -+ motorcomm,keep-pll-enabled; -+ motorcomm,auto-sleep-disabled; -+ -+ pinctrl-0 = <ð_phy_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <15000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; diff --git a/target/linux/rockchip/patches-5.15/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-5.15/100-rockchip-use-system-LED-for-OpenWrt.patch deleted file mode 100644 index 01009c5eb8..0000000000 --- a/target/linux/rockchip/patches-5.15/100-rockchip-use-system-LED-for-OpenWrt.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Fri, 10 Jul 2020 21:38:20 +0200 -Subject: [PATCH] rockchip: use system LED for OpenWrt - -Use the SYS LED on the casing for showing system status. - -This patch is kept separate from the NanoPi R2S support patch, as i plan -on submitting the device support upstream. - -Signed-off-by: David Bauer ---- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -16,6 +16,11 @@ - aliases { - ethernet1 = &rtl8153; - mmc0 = &sdmmc; -+ -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; - }; - - chosen { -@@ -49,18 +54,18 @@ - - lan_led: led-0 { - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:green:lan"; -+ label = "green:lan"; - }; - - sys_led: led-1 { - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:red:sys"; -+ label = "red:sys"; - default-state = "on"; - }; - - wan_led: led-2 { - gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:green:wan"; -+ label = "green:wan"; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -13,6 +13,11 @@ - aliases { - mmc0 = &sdmmc; - mmc1 = &emmc; -+ -+ led-boot = &power_led; -+ led-failsafe = &power_led; -+ led-running = &power_led; -+ led-upgrade = &power_led; - }; - - chosen { diff --git a/target/linux/rockchip/patches-5.15/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.15/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch deleted file mode 100644 index 2221077c97..0000000000 --- a/target/linux/rockchip/patches-5.15/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Sun, 26 Jul 2020 13:32:59 +0200 -Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S - -This adds the OF node for the USB3 ethernet adapter on the FriendlyARM -NanoPi R2S. Add the correct value for the RTL8153 LED configuration -register to match the blink behavior of the other port on the device. - -Signed-off-by: David Bauer ---- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++ - 1 file changed, 1 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -402,6 +402,7 @@ - rtl8153: device@2 { - compatible = "usbbda,8153"; - reg = <2>; -+ realtek,led-data = <0x87>; - }; - }; - diff --git a/target/linux/rockchip/patches-5.15/105-nanopi-r4s-sd-signalling.patch b/target/linux/rockchip/patches-5.15/105-nanopi-r4s-sd-signalling.patch deleted file mode 100644 index 856970738a..0000000000 --- a/target/linux/rockchip/patches-5.15/105-nanopi-r4s-sd-signalling.patch +++ /dev/null @@ -1,36 +0,0 @@ -From: David Bauer -Subject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S - -The NanoPi R4S leaves the SD card in 1.8V signalling when rebooting -while U-Boot requires the card to be in 3.3V mode. - -Remove UHS support from the SD controller so the card remains in 3.3V -mode. This reduces transfer speeds but ensures a reboot whether from -userspace or following a kernel panic is always working. - -Signed-off-by: David Bauer - ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -335,7 +335,6 @@ - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; -- sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -121,6 +121,11 @@ - status = "disabled"; - }; - -+&sdmmc { -+ /delete-property/ sd-uhs-sdr104; -+ cap-sd-highspeed; -+}; -+ - &u2phy0_host { - phy-supply = <&vdd_5v>; - }; diff --git a/target/linux/rockchip/patches-5.15/106-r4s-openwrt-leds.patch b/target/linux/rockchip/patches-5.15/106-r4s-openwrt-leds.patch deleted file mode 100644 index d7579d61e9..0000000000 --- a/target/linux/rockchip/patches-5.15/106-r4s-openwrt-leds.patch +++ /dev/null @@ -1,16 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -19,6 +19,13 @@ - model = "FriendlyElec NanoPi R4S"; - compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; - -+ aliases { -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; -+ }; -+ - /delete-node/ display-subsystem; - - gpio-leds { diff --git a/target/linux/rockchip/patches-5.15/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch b/target/linux/rockchip/patches-5.15/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch deleted file mode 100644 index b1e26d4e3e..0000000000 --- a/target/linux/rockchip/patches-5.15/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch +++ /dev/null @@ -1,56 +0,0 @@ -From d2166e3b3680bd2b206aebf1e1ce4c0d346f3c50 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Fri, 19 May 2023 12:10:52 +0800 -Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Orange Pi R1 - Plus - -Add OpenWrt's LED aliases for showing system status. -Also replace function/color with legacy label as OpenWrt relys on it -to update LED settings. - -Signed-off-by: Tianling Shen ---- - .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 17 +++++++++-------- - 1 file changed, 9 insertions(+), 8 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -@@ -17,6 +17,11 @@ - aliases { - ethernet1 = &rtl8153; - mmc0 = &sdmmc; -+ -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; - }; - - chosen { -@@ -36,22 +41,18 @@ - pinctrl-names = "default"; - - led-0 { -- function = LED_FUNCTION_LAN; -- color = ; - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -+ label = "green:lan"; - }; - -- led-1 { -- function = LED_FUNCTION_STATUS; -- color = ; -+ status_led: led-1 { - gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; -+ label = "red:status"; - }; - - led-2 { -- function = LED_FUNCTION_WAN; -- color = ; - gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; -+ label = "green:wan"; - }; - }; - diff --git a/target/linux/rockchip/patches-5.15/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch b/target/linux/rockchip/patches-5.15/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch deleted file mode 100644 index 37b59925fc..0000000000 --- a/target/linux/rockchip/patches-5.15/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch +++ /dev/null @@ -1,24 +0,0 @@ -From b46a530d12ada422b9d5b2b97059e0d3ed950b40 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Fri, 19 May 2023 12:38:04 +0800 -Subject: [PATCH] arm64: dts: rockchip: add LED configuration to Orange Pi R1 - Plus - -Add the correct value for the RTL8153 LED configuration register to -match the blink behavior of the other port on the device. - -Signed-off-by: Tianling Shen ---- - arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -@@ -362,6 +362,7 @@ - rtl8153: device@2 { - compatible = "usbbda,8153"; - reg = <2>; -+ realtek,led-data = <0x87>; - }; - }; - diff --git a/target/linux/rockchip/patches-5.15/109-nanopc-t4-add-led-aliases.patch b/target/linux/rockchip/patches-5.15/109-nanopc-t4-add-led-aliases.patch deleted file mode 100644 index 1a80dadd48..0000000000 --- a/target/linux/rockchip/patches-5.15/109-nanopc-t4-add-led-aliases.patch +++ /dev/null @@ -1,16 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts -@@ -15,6 +15,13 @@ - model = "FriendlyElec NanoPC-T4"; - compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; - -+ aliases { -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; -+ }; -+ - vcc12v0_sys: vcc12v0-sys { - compatible = "regulator-fixed"; - regulator-always-on; From patchwork Tue Sep 12 14:42:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tianling Shen X-Patchwork-Id: 1833080 X-Patchwork-Delegate: mail@david-bauer.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=yVfgE2my; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RlRGP56W1z1ygM for ; Wed, 13 Sep 2023 00:45:49 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type:List-Help: Reply-To:List-Archive:List-Unsubscribe:List-Subscribe:From:List-Post:List-Id: Message-ID:MIME-Version:References:In-Reply-To:Date:Subject:To:Cc: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=FjvP2uMrEOfvno7KE8AFvjfsazRCHc2LmvvzmCsv8YM=; b=yVfgE2my9fwUtRgQkeyxcs1XSy QFUE7P5mMDyEJMeI33XCypvImONfjCI0vHu1eYkL5vCH1liWqh//aivF4EbOiaucA6hEL4e6qEkI5 YOx4yinm4Dr66izFQLq9sZdE6uXIDlt4f+In4J/hNP3xPLTnusVuENrEUQbPK2SIuJjxJFjcJVnrl 3w3o3LvNIhvd6iBZtu0aT1/w2iZM8Nc957eUBmBm+iatSHmM0akEwkcIHQ6pdquDSgxUrnNInFaok wEDQizITtCjiXaXJVNugl7aKQwbPbuwOfZDo9AHWt/+ADGUGUP5CdN31ZPvWZV+117MbLMDhhy/iN RAndY9Pw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qg4c4-003cF4-29; Tue, 12 Sep 2023 14:43:36 +0000 To: openwrt-devel@lists.openwrt.org Subject: [PATCH 07/12] rockchip: enable drivers for rk356x Date: Tue, 12 Sep 2023 22:42:35 +0800 In-Reply-To: <20230912144240.51396-1-cnsztl@immortalwrt.org> References: <20230912144240.51396-1-cnsztl@immortalwrt.org> MIME-Version: 1.0 Message-ID: List-Id: OpenWrt Development List List-Post: X-Patchwork-Original-From: Tianling Shen via openwrt-devel From: Tianling Shen Precedence: list X-Mailman-Version: 2.1.34 X-BeenThere: openwrt-devel@lists.openwrt.org List-Subscribe: , List-Unsubscribe: , List-Archive: Reply-To: Tianling Shen List-Help: Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software. Enable all necessary drivers for the rk356x SoCs, including PHY, SCMI, SPI etc. Also backport 2 upstream patches for sdhci fixes. Signed-off-by: Tianling Shen --- target/linux/rockchip/armv8/config-6.1 | 28 ++++++--- ...-Update-DLL-and-pre-change-delay-for.patch | 60 +++++++++++++++++++ ...mshc-properly-determine-max-clock-on.patch | 52 ++++++++++++++++ 3 files changed, 131 insertions(+), 9 deletions(-) create mode 100644 target/linux/rockchip/patches-6.1/001-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay-for.patch create mode 100644 target/linux/rockchip/patches-6.1/002-v6.4-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch diff --git a/target/linux/rockchip/armv8/config-6.1 b/target/linux/rockchip/armv8/config-6.1 index e21de9a348..b997a627e4 100644 --- a/target/linux/rockchip/armv8/config-6.1 +++ b/target/linux/rockchip/armv8/config-6.1 @@ -66,6 +66,15 @@ CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y CONFIG_ARM_PSCI_FW=y # CONFIG_ARM_RK3399_DMC_DEVFREQ is not set +CONFIG_ARM_SCMI_CPUFREQ=y +CONFIG_ARM_SCMI_HAVE_SHMEM=y +CONFIG_ARM_SCMI_HAVE_TRANSPORT=y +CONFIG_ARM_SCMI_POWER_CONTROL=y +CONFIG_ARM_SCMI_POWER_DOMAIN=y +CONFIG_ARM_SCMI_PROTOCOL=y +CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y +CONFIG_ARM_SCMI_TRANSPORT_SMC=y +CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y CONFIG_ARM_SCPI_CPUFREQ=y CONFIG_ARM_SCPI_POWER_DOMAIN=y CONFIG_ARM_SCPI_PROTOCOL=y @@ -90,7 +99,6 @@ CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y CONFIG_BLK_DEV_SD=y CONFIG_BLK_MQ_PCI=y CONFIG_BLK_PM=y -# CONFIG_BOSCH_BNO055_SERIAL is not set CONFIG_BRCMSTB_GISB_ARB=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y @@ -113,7 +121,7 @@ CONFIG_CMA_ALIGNMENT=8 CONFIG_CMA_AREAS=7 # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=5 +CONFIG_CMA_SIZE_MBYTES=16 # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MIN is not set @@ -122,6 +130,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_RK808=y CONFIG_COMMON_CLK_ROCKCHIP=y +CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_SCPI=y CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 CONFIG_COMPAT_32BIT_TIME=y @@ -293,6 +302,7 @@ CONFIG_I2C_COMPAT=y CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_RK3X=y CONFIG_IIO=y +# CONFIG_IIO_SCMI is not set CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 CONFIG_INDIRECT_PIO=y CONFIG_INPUT=y @@ -301,7 +311,7 @@ CONFIG_INPUT_FF_MEMLESS=y CONFIG_INPUT_KEYBOARD=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_MATRIXKMAP=y -# CONFIG_INPUT_RK805_PWRKEY is not set +CONFIG_INPUT_RK805_PWRKEY=y CONFIG_IOMMU_API=y # CONFIG_IOMMU_DEBUGFS is not set # CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set @@ -334,7 +344,6 @@ CONFIG_KSM=y # CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set CONFIG_LEDS_GPIO=y CONFIG_LEDS_PWM=y -# CONFIG_LEDS_PWM_MULTICOLOR is not set CONFIG_LEDS_SYSCON=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_PANIC=y @@ -459,9 +468,9 @@ CONFIG_PHY_ROCKCHIP_EMMC=y # CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set # CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set CONFIG_PHY_ROCKCHIP_INNO_USB2=y -# CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY is not set +CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y CONFIG_PHY_ROCKCHIP_PCIE=y -# CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 is not set +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PHY_ROCKCHIP_USB=y CONFIG_PINCTRL=y @@ -495,10 +504,8 @@ CONFIG_PROC_VMCORE=y CONFIG_PTP_1588_CLOCK=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_PWM=y -# CONFIG_PWM_CLK is not set CONFIG_PWM_ROCKCHIP=y CONFIG_PWM_SYSFS=y -# CONFIG_PWM_XILINX is not set # CONFIG_QFMT_V2 is not set CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y @@ -518,6 +525,7 @@ CONFIG_REGMAP_I2C=y CONFIG_REGMAP_IRQ=y CONFIG_REGMAP_MMIO=y CONFIG_REGULATOR=y +CONFIG_REGULATOR_ARM_SCMI=y CONFIG_REGULATOR_FAN53555=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y @@ -525,6 +533,7 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK808=y CONFIG_RELOCATABLE=y CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SCMI=y CONFIG_RFS_ACCEL=y CONFIG_ROCKCHIP_GRF=y CONFIG_ROCKCHIP_IODOMAIN=y @@ -553,6 +562,7 @@ CONFIG_SCSI_SAS_ATTRS=y CONFIG_SCSI_SAS_HOST_SMP=y CONFIG_SCSI_SAS_LIBSAS=y # CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SENSORS_ARM_SCMI=y CONFIG_SENSORS_ARM_SCPI=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_DW=y @@ -589,7 +599,7 @@ CONFIG_SPI_DYNAMIC=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y CONFIG_SPI_ROCKCHIP=y -# CONFIG_SPI_ROCKCHIP_SFC is not set +CONFIG_SPI_ROCKCHIP_SFC=y CONFIG_SPI_SPIDEV=y # CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set CONFIG_SQUASHFS_DECOMP_SINGLE=y diff --git a/target/linux/rockchip/patches-6.1/001-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay-for.patch b/target/linux/rockchip/patches-6.1/001-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay-for.patch new file mode 100644 index 0000000000..2bb542be36 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/001-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay-for.patch @@ -0,0 +1,60 @@ +From b75a52b0dda353aeefb4830a320589a363f49579 Mon Sep 17 00:00:00 2001 +From: Shawn Lin +Date: Thu, 2 Feb 2023 08:35:16 +0800 +Subject: [PATCH] mmc: sdhci-of-dwcmshc: Update DLL and pre-change delay for + rockchip platform + +For Rockchip platform, DLL bypass bit and start bit need to be set if +DLL is not locked. And adjust pre-change delay to 0x3 for better signal +test result. + +Signed-off-by: Shawn Lin +Link: https://lore.kernel.org/r/1675298118-64243-2-git-send-email-shawn.lin@rock-chips.com +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 13 +++++++++---- + 1 file changed, 9 insertions(+), 4 deletions(-) + +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -48,6 +48,7 @@ + #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 + #define DWCMSHC_EMMC_DLL_START_POINT 16 + #define DWCMSHC_EMMC_DLL_INC 8 ++#define DWCMSHC_EMMC_DLL_BYPASS BIT(24) + #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) + #define DLL_TXCLK_TAPNUM_DEFAULT 0x10 + #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA +@@ -60,6 +61,7 @@ + #define DLL_RXCLK_NO_INVERTER 1 + #define DLL_RXCLK_INVERTER 0 + #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8 ++#define DLL_RXCLK_ORI_GATE BIT(31) + #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24) + #define DLL_CMDOUT_SRC_CLK_NEG BIT(28) + #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29) +@@ -234,9 +236,12 @@ static void dwcmshc_rk3568_set_clock(str + sdhci_writel(host, extra, reg); + + if (clock <= 52000000) { +- /* Disable DLL and reset both of sample and drive clock */ +- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); +- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK); ++ /* ++ * Disable DLL and reset both of sample and drive clock. ++ * The bypass bit and start bit need to be set if DLL is not locked. ++ */ ++ sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL); ++ sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK); + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); + sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); + /* +@@ -279,7 +284,7 @@ static void dwcmshc_rk3568_set_clock(str + } + + extra = 0x1 << 16 | /* tune clock stop en */ +- 0x2 << 17 | /* pre-change delay */ ++ 0x3 << 17 | /* pre-change delay */ + 0x3 << 19; /* post-change delay */ + sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); + diff --git a/target/linux/rockchip/patches-6.1/002-v6.4-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch b/target/linux/rockchip/patches-6.1/002-v6.4-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch new file mode 100644 index 0000000000..9d9c1b5c1c --- /dev/null +++ b/target/linux/rockchip/patches-6.1/002-v6.4-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch @@ -0,0 +1,52 @@ +From 49502408007b77ff290ce62e6218cefaeedcb31a Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Thu, 9 Mar 2023 17:03:49 -0800 +Subject: [PATCH] mmc: sdhci-of-dwcmshc: properly determine max clock on + Rockchip + +Currently .get_max_clock returns the current clock rate for cclk_emmc +on rk35xx, thus max clock gets set to whatever bootloader set it to. + +In case of u-boot, it is intentionally reset to 50 MHz if it boots +from eMMC, see mmc_deinit() in u-boot sources. As a result, HS200 and +HS400 modes are never selected by Linux, because dwcmshc_rk35xx_postinit +clears appropriate caps if host->mmc->f_max is < 52MHz + +cclk_emmc is not a fixed clock on rk35xx, so using +sdhci_pltfm_clk_get_max_clock is not appropriate here. + +Implement rk35xx_get_max_clock that returns actual max clock for cclk_emmc. + +Signed-off-by: Vasily Khoruzhick +Acked-by: Adrian Hunter +Link: https://lore.kernel.org/r/20230310010349.509132-1-anarsoul@gmail.com +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -126,6 +126,13 @@ static unsigned int dwcmshc_get_max_cloc + return pltfm_host->clock; + } + ++static unsigned int rk35xx_get_max_clock(struct sdhci_host *host) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ ++ return clk_round_rate(pltfm_host->clk, ULONG_MAX); ++} ++ + static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc, + struct mmc_request *mrq) + { +@@ -343,7 +350,7 @@ static const struct sdhci_ops sdhci_dwcm + .set_clock = dwcmshc_rk3568_set_clock, + .set_bus_width = sdhci_set_bus_width, + .set_uhs_signaling = dwcmshc_set_uhs_signaling, +- .get_max_clock = sdhci_pltfm_clk_get_max_clock, ++ .get_max_clock = rk35xx_get_max_clock, + .reset = rk35xx_sdhci_reset, + .adma_write_desc = dwcmshc_adma_write_desc, + }; From patchwork Tue Sep 12 14:42:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tianling Shen X-Patchwork-Id: 1833086 X-Patchwork-Delegate: mail@david-bauer.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=uB65Aqe4; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RlRGn1h4Dz1yp5 for ; Wed, 13 Sep 2023 00:46:09 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type:List-Help: Reply-To:List-Archive:List-Unsubscribe:List-Subscribe:From:List-Post:List-Id: Message-ID:MIME-Version:References:In-Reply-To:Date:Subject:To:Cc: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=kT3qVSSjfDzlYUAUdasFBqrkyZdF3FfUdIKpEtFud/Q=; b=uB65Aqe4ZtRlTs85QJE9N0cMLv GZ13Tp4eF5bN7PdeVmehgJraLtXbhm81LwOzN5y1zzHRBP5lEdE/Sg2NmtMzsxIbNb7kSTR81DV98 ClDQLcc+SYedlY7wt0oKcgvMFltZ6jowG9af2Usgw5ytd3zWzwYMBUfx+Ls3MEOCWfdbJFMIhAz9M SMJG3OYIZJEVzTB4gZ5drxCgRTLLDAYwM9iz9SphKEEfbjy7/VDM3NKiOyO7w6WxdYPlHDLg1AKN8 F5nhDk5Q14p8l7DAGqkLNmHNOJrU+MygsyItwZrnNnm3U2NX3KBwhT5bx939SGDflYyqkugcF/3XV ZDxN3v6g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qg4cB-003cKm-2Z; Tue, 12 Sep 2023 14:43:43 +0000 To: openwrt-devel@lists.openwrt.org Subject: [PATCH 09/12] uboot-rockchip: add NanoPi R5S support Date: Tue, 12 Sep 2023 22:42:37 +0800 In-Reply-To: <20230912144240.51396-1-cnsztl@immortalwrt.org> References: <20230912144240.51396-1-cnsztl@immortalwrt.org> MIME-Version: 1.0 Message-ID: List-Id: OpenWrt Development List List-Post: X-Patchwork-Original-From: Tianling Shen via openwrt-devel From: Tianling Shen Precedence: list X-Mailman-Version: 2.1.34 X-BeenThere: openwrt-devel@lists.openwrt.org List-Subscribe: , List-Unsubscribe: , List-Archive: Reply-To: Tianling Shen List-Help: Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software. Add support for the FriendlyARM NanoPi R5S support. Tested-by: Packet Please Signed-off-by: Tianling Shen --- package/boot/uboot-rockchip/Makefile | 23 +- ...Add-support-for-FriendlyARM-NanoPi-R.patch | 917 ++++++++++++++++++ 2 files changed, 938 insertions(+), 2 deletions(-) create mode 100644 package/boot/uboot-rockchip/patches/103-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 35eaf198be..5e55077484 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -117,6 +117,23 @@ define U-Boot/rockpro64-rk3399 pine64_rockpro64 endef + +# RK3568 boards + +define U-Boot/rk3568/Default + BUILD_SUBTARGET:=armv8 + DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3568 + ATF:=rk3568_bl31_v1.43.elf + TPL:=rk3568_ddr_1560MHz_v1.18.bin +endef + +define U-Boot/nanopi-r5s-rk3568 + $(U-Boot/rk3568/Default) + NAME:=NanoPi R5S + BUILD_DEVICES:= \ + friendlyarm_nanopi-r5s +endef + UBOOT_TARGETS := \ nanopc-t4-rk3399 \ nanopi-r4s-rk3399 \ @@ -128,7 +145,8 @@ UBOOT_TARGETS := \ orangepi-r1-plus-lts-rk3328 \ roc-cc-rk3328 \ rock64-rk3328 \ - rock-pi-e-rk3328 + rock-pi-e-rk3328 \ + nanopi-r5s-rk3568 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes @@ -139,7 +157,8 @@ UBOOT_CUSTOMIZE_CONFIG := \ UBOOT_MAKE_FLAGS += \ PATH=$(STAGING_DIR_HOST)/bin:$(PATH) \ - BL31=$(STAGING_DIR_IMAGE)/$(ATF) + BL31=$(STAGING_DIR_IMAGE)/$(ATF) \ + $(if $(TPL),ROCKCHIP_TPL=$(STAGING_DIR_IMAGE)/$(TPL)) define Build/InstallDev $(INSTALL_DIR) $(STAGING_DIR_IMAGE) diff --git a/package/boot/uboot-rockchip/patches/103-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/103-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch new file mode 100644 index 0000000000..09cafb3227 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/103-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -0,0 +1,917 @@ +From c84214aab0e4c5b2f619dd89655f27b3ae40e82b Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Tue, 30 May 2023 15:00:33 +0800 +Subject: [PATCH] rockchip: rk3568: Add support for FriendlyARM NanoPi R5S + +FriendlyARM NanoPi R5S is an open-sourced mini IoT gateway device. + +Board Specifications +- Rockchip RK3568 +- 2 or 4GB LPDDR4X +- 8GB or 16GB eMMC, SD card slot +- GbE LAN (Native) +- 2x 2.5G LAN (PCIe) +- M.2 Connector +- HDMI 2.0, MIPI DSI/CSI +- 2xUSB 3.0 Host +- USB Type C PD, 5V/9V/12V +- GPIO: 12-pin 0.5mm FPC connector + +The device tree is taken from kernel v6.4-rc1. + +Reviewed-by: Kever Yang +Signed-off-by: Tianling Shen +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 31 ++ + arch/arm/dts/rk3568-nanopi-r5s.dts | 136 +++++ + arch/arm/dts/rk3568-nanopi-r5s.dtsi | 590 +++++++++++++++++++++ + board/rockchip/evb_rk3568/MAINTAINERS | 8 + + configs/nanopi-r5s-rk3568_defconfig | 85 +++ + 6 files changed, 851 insertions(+) + create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts + create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dtsi + create mode 100644 configs/nanopi-r5s-rk3568_defconfig + +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3566-anbernic-rgxx3.dtb \ + rk3566-radxa-cm3-io.dtb \ + rk3568-evb.dtb \ ++ rk3568-nanopi-r5s.dtb \ + rk3568-rock-3a.dtb + + dtb-$(CONFIG_ROCKCHIP_RK3588) += \ +--- /dev/null ++++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi +@@ -0,0 +1,31 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2023 Tianling Shen ++ */ ++ ++#include "rk356x-u-boot.dtsi" ++ ++/ { ++ chosen { ++ stdout-path = &uart2; ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; ++ }; ++}; ++ ++&sdhci { ++ cap-mmc-highspeed; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; ++}; ++ ++&uart2 { ++ clock-frequency = <24000000>; ++ bootph-all; ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/dts/rk3568-nanopi-r5s.dts +@@ -0,0 +1,136 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include "rk3568-nanopi-r5s.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R5S"; ++ compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568"; ++ ++ aliases { ++ ethernet0 = &gmac0; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>; ++ ++ led-lan1 { ++ color = ; ++ function = LED_FUNCTION_LAN; ++ function-enumerator = <1>; ++ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-lan2 { ++ color = ; ++ function = LED_FUNCTION_LAN; ++ function-enumerator = <2>; ++ gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ power_led: led-power { ++ color = ; ++ function = LED_FUNCTION_POWER; ++ linux,default-trigger = "heartbeat"; ++ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-wan { ++ color = ; ++ function = LED_FUNCTION_WAN; ++ gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; ++ ++&gmac0 { ++ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; ++ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; ++ assigned-clock-rates = <0>, <125000000>; ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy0>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac0_miim ++ &gmac0_tx_bus2 ++ &gmac0_rx_bus2 ++ &gmac0_rgmii_clk ++ &gmac0_rgmii_bus>; ++ snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ /* Reset time is 15ms, 50ms for rtl8211f */ ++ snps,reset-delays-us = <0 15000 50000>; ++ tx_delay = <0x3c>; ++ rx_delay = <0x2f>; ++ status = "okay"; ++}; ++ ++&mdio0 { ++ rgmii_phy0: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ pinctrl-0 = <ð_phy0_reset_pin>; ++ pinctrl-names = "default"; ++ }; ++}; ++ ++&pcie2x1 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ data-lanes = <1 2>; ++ status = "okay"; ++}; ++ ++&pcie3x1 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ num-lanes = <1>; ++ num-ib-windows = <8>; ++ num-ob-windows = <8>; ++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gmac0 { ++ eth_phy0_reset_pin: eth-phy0-reset-pin { ++ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ gpio-leds { ++ lan1_led_pin: lan1-led-pin { ++ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ lan2_led_pin: lan2-led-pin { ++ rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ power_led_pin: power-led-pin { ++ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/dts/rk3568-nanopi-r5s.dtsi +@@ -0,0 +1,590 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++#include ++#include "rk3568.dtsi" ++ ++/ { ++ aliases { ++ mmc0 = &sdmmc0; ++ mmc1 = &sdhci; ++ }; ++ ++ chosen: chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ vdd_usbc: vdd-usbc-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_usbc"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <200000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_usb: vcc5v0-usb-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc5v0_usb_host: vcc5v0-usb-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_host_en>; ++ regulator-name = "vcc5v0_usb_host"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ ++ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_otg_en>; ++ regulator-name = "vcc5v0_usb_otg"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ ++ pcie30_avdd0v9: pcie30-avdd0v9-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_avdd1v8: pcie30-avdd1v8-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++}; ++ ++&combphy0 { ++ status = "okay"; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int>; ++ rockchip,system-power-controller; ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <950000>; ++ regulator-max-microvolt = <950000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ ++ }; ++}; ++ ++&i2c5 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <0>; ++ clock-output-names = "rtcic_32kout"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ wakeup-source; ++ }; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ data-lanes = <1 2>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int: pmic-int { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_usb_host_en: vcc5v0-usb-host-en { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_1v8>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ max-frequency = <150000000>; ++ no-sdio; ++ no-mmc; ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ vmmc-supply = <&vcc3v3_sd>; ++ vqmmc-supply = <&vccio_sd>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ extcon = <&usb2phy0>; ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ phy-supply = <&vcc5v0_usb_otg>; ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; +--- a/board/rockchip/evb_rk3568/MAINTAINERS ++++ b/board/rockchip/evb_rk3568/MAINTAINERS +@@ -7,6 +7,14 @@ F: configs/evb-rk3568_defconfig + F: arch/arm/dts/rk3568-evb-boot.dtsi + F: arch/arm/dts/rk3568-evb.dts + ++NANOPI-R5S ++M: Tianling Shen ++S: Maintained ++F: configs/nanopi-r5s-rk3568_defconfig ++F: arch/arm/dts/rk3568-nanopi-r5s.dts ++F: arch/arm/dts/rk3568-nanopi-r5s.dtsi ++F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi ++ + RADXA-CM3 + M: Jagan Teki + S: Maintained +--- /dev/null ++++ b/configs/nanopi-r5s-rk3568_defconfig +@@ -0,0 +1,85 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_TEXT_BASE=0x00a00000 ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_NR_DRAM_BANKS=2 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_SPL_SERIAL=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_TARGET_EVB_RK3568=y ++CONFIG_SPL_STACK=0x400000 ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y ++CONFIG_SPL_BSS_START_ADDR=0x4000000 ++CONFIG_SPL_BSS_MAX_SIZE=0x4000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SPL_DM_WARN=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_PSCI=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_ERRNO_STR=y From patchwork Tue Sep 12 14:42:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tianling Shen X-Patchwork-Id: 1833087 X-Patchwork-Delegate: mail@david-bauer.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=Pqc3XgLC; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RlRGt62H2z1ygM for ; Wed, 13 Sep 2023 00:46:14 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type:List-Help: Reply-To:List-Archive:List-Unsubscribe:List-Subscribe:From:List-Post:List-Id: Message-ID:MIME-Version:References:In-Reply-To:Date:Subject:To:Cc: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=vvkCEs5sYS+xj4Nzox4eMHoxFkJ6wjf3z7BRaa0z/4c=; b=Pqc3XgLCynsnueoSUQkCF/rMOD g2uZmgHdn09elaxGOVsTZZmtvkJNYOzcHE5a6s5MTGIV+Odwj+myYQDryzlWYMygYV8G+L9Fimq0o HosLuWHFk4txqKPlY4oS2zENkcPeYUzvGtg5DTAz+0jOCtosQH5tgfWpuBAB+rEhVUAi9ezZMd996 4mEMU5W8XisFFEadXyPsje5q1G90ZitY5CVHpJnWDyskU6bU35fQzz/XCxWCi4Q4ynm6S4PmtbnX3 O1W3yv9tx9PhLiWe0/g4mfNebr6rOweIwHu38lUzvRStlLHW5qKdri4Y3tRlqMrp+G90BxuEO/QUu NhGKmPYg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qg4cF-003cOa-1q; Tue, 12 Sep 2023 14:43:47 +0000 To: openwrt-devel@lists.openwrt.org Subject: [PATCH 10/12] rockchip: add NanoPi R5S support Date: Tue, 12 Sep 2023 22:42:38 +0800 In-Reply-To: <20230912144240.51396-1-cnsztl@immortalwrt.org> References: <20230912144240.51396-1-cnsztl@immortalwrt.org> MIME-Version: 1.0 Message-ID: List-Id: OpenWrt Development List List-Post: X-Patchwork-Original-From: Tianling Shen via openwrt-devel From: Tianling Shen Precedence: list X-Mailman-Version: 2.1.34 X-BeenThere: openwrt-devel@lists.openwrt.org List-Subscribe: , List-Unsubscribe: , List-Archive: Reply-To: Tianling Shen List-Help: Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software. Hardware -------- RockChip RK3568 ARM64 (4 cores) 2GB or 4GB LPDDR4X RAM 1x 1000 Base-T 2x 2500 Base-T 4 LEDs (LAN1 / LAN2 / WAN / POWER) 8GB eMMC on-board Micro-SD Slot M.2 Slot 2x USB 3.0 Port Installation ------------ Uncompress the OpenWrt sysupgrade and write it to a micro SD card or internal eMMC using dd. Tested-by: Packet Please Signed-off-by: Tianling Shen --- .../armv8/base-files/etc/board.d/01_leds | 5 + .../armv8/base-files/etc/board.d/02_network | 7 + .../etc/hotplug.d/net/40-net-smp-affinity | 5 + target/linux/rockchip/image/armv8.mk | 8 + ...rockchip-Add-FriendlyElec-Nanopi-R5S.patch | 754 ++++++++++ ...eate-common-dtsi-for-NanoPi-R5-serie.patch | 1226 +++++++++++++++++ ...chip-fix-gmac-support-for-NanoPi-R5S.patch | 49 + ...move-I2S1-TDM-node-for-the-NanoPi-R5.patch | 39 + ...ip-Update-LED-properties-for-NanoPi-.patch | 63 + 9 files changed, 2156 insertions(+) create mode 100644 target/linux/rockchip/patches-6.1/009-v6.4-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch create mode 100644 target/linux/rockchip/patches-6.1/010-v6.4-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-serie.patch create mode 100644 target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch create mode 100644 target/linux/rockchip/patches-6.1/012-v6.4-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-NanoPi-R5.patch create mode 100644 target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds index d82e47cf53..cfab545849 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds @@ -16,6 +16,11 @@ xunlong,orangepi-r1-plus-lts) ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth1" ;; +friendlyarm,nanopi-r5s) + ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" + ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth1" + ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth2" + ;; esac board_config_flush diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index 7ac5148275..838a107193 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -14,6 +14,9 @@ rockchip_setup_interfaces() xunlong,orangepi-r1-plus-lts) ucidef_set_interfaces_lan_wan 'eth1' 'eth0' ;; + friendlyarm,nanopi-r5s) + ucidef_set_interfaces_lan_wan 'eth1 eth2' 'eth0' + ;; *) ucidef_set_interface_lan 'eth0' ;; @@ -58,6 +61,10 @@ rockchip_setup_macs() wan_mac=$(nanopi_r4s_get_mac wan) lan_mac=$(nanopi_r4s_get_mac lan) ;; + friendlyarm,nanopi-r5s) + wan_mac=$(macaddr_generate_from_mmc_cid mmcblk1) + lan_mac=$(macaddr_add "$wan_mac" 1) + ;; xunlong,orangepi-r1-plus|\ xunlong,orangepi-r1-plus-lts) wan_mac=$(macaddr_add "$(cat /sys/class/net/eth1/address)" -1) diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity index bb119b9185..161059a87b 100644 --- a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity +++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity @@ -40,5 +40,10 @@ friendlyarm,nanopi-r4s) set_interface_core 10 "eth0" set_interface_core 20 "eth1" ;; +friendlyarm,nanopi-r5s) + set_interface_core 2 "eth0" + set_interface_core 4 "eth1" + set_interface_core 8 "eth2" + ;; esac diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 608ad79ca4..e836e3c91d 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -47,6 +47,14 @@ define Device/friendlyarm_nanopi-r4s endef TARGET_DEVICES += friendlyarm_nanopi-r4s +define Device/friendlyarm_nanopi-r5s + DEVICE_VENDOR := FriendlyARM + DEVICE_MODEL := NanoPi R5S + SOC := rk3568 + DEVICE_PACKAGES := kmod-r8169 +endef +TARGET_DEVICES += friendlyarm_nanopi-r5s + define Device/pine64_rock64 DEVICE_VENDOR := Pine64 DEVICE_MODEL := Rock64 diff --git a/target/linux/rockchip/patches-6.1/009-v6.4-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch b/target/linux/rockchip/patches-6.1/009-v6.4-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch new file mode 100644 index 0000000000..3d502a65b6 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/009-v6.4-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch @@ -0,0 +1,754 @@ +From c6629b9a6738a64507478527da6c7b83c10a6d2c Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Tue, 7 Mar 2023 22:32:40 -0800 +Subject: [PATCH] arm64: dts: rockchip: Add FriendlyElec Nanopi R5S + +FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device. + +Board Specifications +- Rockchip RK3568 +- 2 or 4GB LPDDR4X +- 8GB or 16GB eMMC, SD card slot +- GbE LAN (Native) +- 2x 2.5G LAN (PCIe) +- M.2 Connector +- HDMI 2.0, MIPI DSI/CSI +- 2xUSB 3.0 Host +- USB Type C PD, 5V/9V/12V +- GPIO: 12-pin 0.5mm FPC connector + +Based on Tianling Shen's work. + +Signed-off-by: Vasily Khoruzhick +Link: https://lore.kernel.org/r/20230308063240.107178-2-anarsoul@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 713 ++++++++++++++++++ + 2 files changed, 714 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -74,4 +74,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +@@ -0,0 +1,713 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++#include ++#include "rk3568.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R5S"; ++ compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568"; ++ ++ aliases { ++ ethernet0 = &gmac0; ++ mmc0 = &sdmmc0; ++ mmc1 = &sdhci; ++ }; ++ ++ chosen: chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>; ++ ++ led-lan1 { ++ color = ; ++ function = LED_FUNCTION_LAN; ++ function-enumerator = <1>; ++ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-lan2 { ++ color = ; ++ function = LED_FUNCTION_LAN; ++ function-enumerator = <2>; ++ gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ power_led: led-power { ++ color = ; ++ function = LED_FUNCTION_POWER; ++ linux,default-trigger = "heartbeat"; ++ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-wan { ++ color = ; ++ function = LED_FUNCTION_WAN; ++ gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ vdd_usbc: vdd-usbc-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_usbc"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <200000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_usb: vcc5v0-usb-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc5v0_usb_host: vcc5v0-usb-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_host_en>; ++ regulator-name = "vcc5v0_usb_host"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ ++ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_otg_en>; ++ regulator-name = "vcc5v0_usb_otg"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ ++ pcie30_avdd0v9: pcie30-avdd0v9-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_avdd1v8: pcie30-avdd1v8-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++}; ++ ++&combphy0 { ++ status = "okay"; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gmac0 { ++ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; ++ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; ++ assigned-clock-rates = <0>, <125000000>; ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy0>; ++ phy-mode = "rgmii-id"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac0_miim ++ &gmac0_tx_bus2 ++ &gmac0_rx_bus2 ++ &gmac0_rgmii_clk ++ &gmac0_rgmii_bus>; ++ snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ /* Reset time is 15ms, 50ms for rtl8211f */ ++ snps,reset-delays-us = <0 15000 50000>; ++ tx_delay = <0x3c>; ++ rx_delay = <0x2f>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int>; ++ rockchip,system-power-controller; ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <950000>; ++ regulator-max-microvolt = <950000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ ++ }; ++}; ++ ++&i2c5 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <0>; ++ clock-output-names = "rtcic_32kout"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ wakeup-source; ++ }; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&i2s1_8ch { ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ ++&mdio0 { ++ rgmii_phy0: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ pinctrl-0 = <ð_phy0_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pcie2x1 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ data-lanes = <1 2>; ++ status = "okay"; ++}; ++ ++&pcie3x1 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ num-lanes = <1>; ++ num-ib-windows = <8>; ++ num-ob-windows = <8>; ++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gmac0 { ++ eth_phy0_reset_pin: eth-phy0-reset-pin { ++ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ gpio-leds { ++ lan1_led_pin: lan1-led-pin { ++ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ lan2_led_pin: lan2-led-pin { ++ rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ power_led_pin: power-led-pin { ++ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int: pmic-int { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_usb_host_en: vcc5v0-usb-host-en { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_1v8>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ max-frequency = <150000000>; ++ no-sdio; ++ no-mmc; ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ vmmc-supply = <&vcc3v3_sd>; ++ vqmmc-supply = <&vccio_sd>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ extcon = <&usb2phy0>; ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ phy-supply = <&vcc5v0_usb_otg>; ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.1/010-v6.4-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-serie.patch b/target/linux/rockchip/patches-6.1/010-v6.4-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-serie.patch new file mode 100644 index 0000000000..cf9fe06ad0 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/010-v6.4-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-serie.patch @@ -0,0 +1,1226 @@ +From c8ec73b05a95d9f0969ae0f28dd8799a54fcdfc7 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Sat, 18 Mar 2023 16:37:41 +0800 +Subject: [PATCH] arm64: dts: rockchip: create common dtsi for NanoPi R5 series + +Create common dtsi for the FriendlyElec NanoPi R5 series. + +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20230318083745.6181-2-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 575 +---------------- + .../boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 596 ++++++++++++++++++ + 2 files changed, 597 insertions(+), 574 deletions(-) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi + +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +@@ -7,12 +7,7 @@ + */ + + /dts-v1/; +-#include +-#include +-#include +-#include +-#include +-#include "rk3568.dtsi" ++#include "rk3568-nanopi-r5s.dtsi" + + / { + model = "FriendlyElec NanoPi R5S"; +@@ -20,23 +15,6 @@ + + aliases { + ethernet0 = &gmac0; +- mmc0 = &sdmmc0; +- mmc1 = &sdhci; +- }; +- +- chosen: chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- hdmi-con { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; + }; + + gpio-leds { +@@ -71,130 +49,6 @@ + gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + }; + }; +- +- vdd_usbc: vdd-usbc-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_usbc"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- vcc3v3_sys: vcc3v3-sys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vdd_usbc>; +- }; +- +- vcc5v0_sys: vcc5v0-sys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vdd_usbc>; +- }; +- +- vcc3v3_pcie: vcc3v3-pcie-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_pcie"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <200000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_usb: vcc5v0-usb-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_usb"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vdd_usbc>; +- }; +- +- vcc5v0_usb_host: vcc5v0-usb-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_usb_host_en>; +- regulator-name = "vcc5v0_usb_host"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc5v0_usb>; +- }; +- +- vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_usb_otg_en>; +- regulator-name = "vcc5v0_usb_otg"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc5v0_usb>; +- }; +- +- pcie30_avdd0v9: pcie30-avdd0v9-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "pcie30_avdd0v9"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- vin-supply = <&vcc3v3_sys>; +- }; +- +- pcie30_avdd1v8: pcie30-avdd1v8-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "pcie30_avdd1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc3v3_sys>; +- }; +-}; +- +-&combphy0 { +- status = "okay"; +-}; +- +-&combphy1 { +- status = "okay"; +-}; +- +-&combphy2 { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_cpu>; + }; + + &gmac0 { +@@ -219,292 +73,6 @@ + status = "okay"; + }; + +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&hdmi { +- avdd-0v9-supply = <&vdda0v9_image>; +- avdd-1v8-supply = <&vcca1v8_image>; +- status = "okay"; +-}; +- +-&hdmi_in { +- hdmi_in_vp0: endpoint { +- remote-endpoint = <&vp0_out_hdmi>; +- }; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- vdd_cpu: regulator@1c { +- compatible = "tcs,tcs4525"; +- reg = <0x1c>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1150000>; +- regulator-ramp-delay = <2300>; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- rk809: pmic@20 { +- compatible = "rockchip,rk809"; +- reg = <0x20>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- #clock-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int>; +- rockchip,system-power-controller; +- vcc1-supply = <&vcc3v3_sys>; +- vcc2-supply = <&vcc3v3_sys>; +- vcc3-supply = <&vcc3v3_sys>; +- vcc4-supply = <&vcc3v3_sys>; +- vcc5-supply = <&vcc3v3_sys>; +- vcc6-supply = <&vcc3v3_sys>; +- vcc7-supply = <&vcc3v3_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc3v3_sys>; +- wakeup-source; +- +- regulators { +- vdd_logic: DCDC_REG1 { +- regulator-name = "vdd_logic"; +- regulator-always-on; +- regulator-boot-on; +- regulator-init-microvolt = <900000>; +- regulator-initial-mode = <0x2>; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: DCDC_REG2 { +- regulator-name = "vdd_gpu"; +- regulator-always-on; +- regulator-init-microvolt = <900000>; +- regulator-initial-mode = <0x2>; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-initial-mode = <0x2>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vdd_npu: DCDC_REG4 { +- regulator-name = "vdd_npu"; +- regulator-init-microvolt = <900000>; +- regulator-initial-mode = <0x2>; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v8: DCDC_REG5 { +- regulator-name = "vcc_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdda0v9_image: LDO_REG1 { +- regulator-name = "vdda0v9_image"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <950000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdda_0v9: LDO_REG2 { +- regulator-name = "vdda_0v9"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdda0v9_pmu: LDO_REG3 { +- regulator-name = "vdda0v9_pmu"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <900000>; +- }; +- }; +- +- vccio_acodec: LDO_REG4 { +- regulator-name = "vccio_acodec"; +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vccio_sd: LDO_REG5 { +- regulator-name = "vccio_sd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v3_pmu: LDO_REG6 { +- regulator-name = "vcc3v3_pmu"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcca_1v8: LDO_REG7 { +- regulator-name = "vcca_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcca1v8_pmu: LDO_REG8 { +- regulator-name = "vcca1v8_pmu"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcca1v8_image: LDO_REG9 { +- regulator-name = "vcca1v8_image"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v3: SWITCH_REG1 { +- regulator-name = "vcc_3v3"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v3_sd: SWITCH_REG2 { +- regulator-name = "vcc3v3_sd"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- +- }; +-}; +- +-&i2c5 { +- status = "okay"; +- +- hym8563: rtc@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- #clock-cells = <0>; +- clock-output-names = "rtcic_32kout"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hym8563_int>; +- wakeup-source; +- }; +-}; +- +-&i2s0_8ch { +- status = "okay"; +-}; +- +-&i2s1_8ch { +- rockchip,trcm-sync-tx-only; +- status = "okay"; +-}; +- + &mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; +@@ -568,146 +136,5 @@ + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +- +- hym8563 { +- hym8563_int: hym8563-int { +- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- pmic { +- pmic_int: pmic-int { +- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb { +- vcc5v0_usb_host_en: vcc5v0-usb-host-en { +- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pmu_io_domains { +- pmuio1-supply = <&vcc3v3_pmu>; +- pmuio2-supply = <&vcc3v3_pmu>; +- vccio1-supply = <&vccio_acodec>; +- vccio3-supply = <&vccio_sd>; +- vccio4-supply = <&vcc_1v8>; +- vccio5-supply = <&vcc_3v3>; +- vccio6-supply = <&vcc_1v8>; +- vccio7-supply = <&vcc_3v3>; +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcca_1v8>; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- max-frequency = <200000000>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; +- status = "okay"; +-}; +- +-&sdmmc0 { +- max-frequency = <150000000>; +- no-sdio; +- no-mmc; +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- disable-wp; +- vmmc-supply = <&vcc3v3_sd>; +- vqmmc-supply = <&vccio_sd>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <1>; +- rockchip,hw-tshut-polarity = <0>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host0_xhci { +- extcon = <&usb2phy0>; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; + }; + +-&usb_host1_xhci { +- status = "okay"; +-}; +- +-&usb2phy0 { +- status = "okay"; +-}; +- +-&usb2phy0_host { +- phy-supply = <&vcc5v0_usb_host>; +- status = "okay"; +-}; +- +-&usb2phy0_otg { +- status = "okay"; +-}; +- +-&usb2phy1 { +- status = "okay"; +-}; +- +-&usb2phy1_host { +- phy-supply = <&vcc5v0_usb_otg>; +- status = "okay"; +-}; +- +-&usb2phy1_otg { +- status = "okay"; +-}; +- +-&vop { +- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; +- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +- status = "okay"; +-}; +- +-&vop_mmu { +- status = "okay"; +-}; +- +-&vp0 { +- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { +- reg = ; +- remote-endpoint = <&hdmi_in_vp0>; +- }; +-}; +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi +@@ -0,0 +1,596 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++#include ++#include "rk3568.dtsi" ++ ++/ { ++ aliases { ++ mmc0 = &sdmmc0; ++ mmc1 = &sdhci; ++ }; ++ ++ chosen: chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ vdd_usbc: vdd-usbc-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_usbc"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <200000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_usb: vcc5v0-usb-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc5v0_usb_host: vcc5v0-usb-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_host_en>; ++ regulator-name = "vcc5v0_usb_host"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ ++ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_otg_en>; ++ regulator-name = "vcc5v0_usb_otg"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ ++ pcie30_avdd0v9: pcie30-avdd0v9-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_avdd1v8: pcie30-avdd1v8-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++}; ++ ++&combphy0 { ++ status = "okay"; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int>; ++ rockchip,system-power-controller; ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <950000>; ++ regulator-max-microvolt = <950000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ ++ }; ++}; ++ ++&i2c5 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <0>; ++ clock-output-names = "rtcic_32kout"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ wakeup-source; ++ }; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&i2s1_8ch { ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ data-lanes = <1 2>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int: pmic-int { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_usb_host_en: vcc5v0-usb-host-en { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_1v8>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ max-frequency = <150000000>; ++ no-sdio; ++ no-mmc; ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ vmmc-supply = <&vcc3v3_sd>; ++ vqmmc-supply = <&vccio_sd>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ extcon = <&usb2phy0>; ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ phy-supply = <&vcc5v0_usb_otg>; ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch b/target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch new file mode 100644 index 0000000000..47f76d54e7 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch @@ -0,0 +1,49 @@ +From 31425b1fadb2040b359e52ffc24c049a78d56c96 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Sat, 18 Mar 2023 16:37:44 +0800 +Subject: [PATCH] arm64: dts: rockchip: fix gmac support for NanoPi R5S + +- Changed phy-mode to rgmii. + +- Fixed pull type in pinctrl for gmac0. + +- Removed duplicate properties in mdio node. + These properties are defined in the gmac0 node already. + +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20230318083745.6181-5-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++----- + 1 file changed, 2 insertions(+), 5 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +@@ -57,7 +57,7 @@ + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; +- phy-mode = "rgmii-id"; ++ phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 +@@ -79,9 +79,6 @@ + reg = <1>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; +- reset-assert-us = <10000>; +- reset-deassert-us = <50000>; +- reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + }; + }; + +@@ -115,7 +112,7 @@ + &pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { +- rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; ++ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + diff --git a/target/linux/rockchip/patches-6.1/012-v6.4-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-NanoPi-R5.patch b/target/linux/rockchip/patches-6.1/012-v6.4-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-NanoPi-R5.patch new file mode 100644 index 0000000000..48021b226a --- /dev/null +++ b/target/linux/rockchip/patches-6.1/012-v6.4-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-NanoPi-R5.patch @@ -0,0 +1,39 @@ +From 975e9bbad11950fc8276f1fa260d8bf2c341aa41 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Sat, 18 Mar 2023 16:37:45 +0800 +Subject: [PATCH] arm64: dts: rockchip: remove I2S1 TDM node for the NanoPi R5 + series + +This is for the audio output which does not exist on the boards. +Also disable regulator-always-on for vccio_acodec since it's only +used by the audio output. + +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20230318083745.6181-6-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 6 ------ + 1 file changed, 6 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi +@@ -330,7 +330,6 @@ + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; +- regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + +@@ -441,11 +440,6 @@ + status = "okay"; + }; + +-&i2s1_8ch { +- rockchip,trcm-sync-tx-only; +- status = "okay"; +-}; +- + &pcie30phy { + data-lanes = <1 2>; + status = "okay"; diff --git a/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch b/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch new file mode 100644 index 0000000000..8339ef5dbc --- /dev/null +++ b/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch @@ -0,0 +1,63 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Tue Jun 20 16:45:27 2023 +0800 +Subject: [PATCH] arm64: dts: rockchip: Update LED properties for NanoPi R5 + series + +Add OpenWrt's LED aliases for showing system status. +Also replace function/color with legacy label as OpenWrt relys on it +to update LED settings. + +Signed-off-by: Tianling Shen +--- + +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +@@ -23,29 +23,22 @@ + pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>; + + led-lan1 { +- color = ; +- function = LED_FUNCTION_LAN; +- function-enumerator = <1>; ++ label = "green:lan1"; + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + }; + + led-lan2 { +- color = ; +- function = LED_FUNCTION_LAN; +- function-enumerator = <2>; ++ label = "green:lan2"; + gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; + }; + + power_led: led-power { +- color = ; +- function = LED_FUNCTION_POWER; +- linux,default-trigger = "heartbeat"; ++ label = "red:power"; + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + }; + + led-wan { +- color = ; +- function = LED_FUNCTION_WAN; ++ label = "green:wan"; + gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + }; + }; +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi +@@ -18,6 +18,11 @@ + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdhci; ++ ++ led-boot = &power_led; ++ led-failsafe = &power_led; ++ led-running = &power_led; ++ led-upgrade = &power_led; + }; + + chosen: chosen { From patchwork Tue Sep 12 14:42:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tianling Shen X-Patchwork-Id: 1833084 X-Patchwork-Delegate: mail@david-bauer.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=4rxDZJUm; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RlRGm4FCSz1ygM for ; Wed, 13 Sep 2023 00:46:08 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type:List-Help: Reply-To:List-Archive:List-Unsubscribe:List-Subscribe:From:List-Post:List-Id: Message-ID:MIME-Version:References:In-Reply-To:Date:Subject:To:Cc: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Xipbjc+gViB1Cs6oCyVWLo13TCWmwxTFelW/golvzmU=; b=4rxDZJUmmHiHrlDuTqtnriT8iJ BxBNGft41sQ2+m8/GbROKbNhhjGwK7GJ3BqDR/ZE+UgGExy/3b9L1ySCowz35TXsE+++cAajx0zMe Ec2x/4qa2Z2qsucRRJpMBdTbQw5/EiJU6dNujiOQAGMdFirAxANGlwuiUWHfP0Bjiliet5FO5bsX1 gJBrXVk61bRuBQ8RuL6GHcf/K/PCG6Toa6xWsDEzarjPAz64GcLgb9PAP2cAr0KXQ93uFDsg5XeoI 7xasoIgy0G8r0oyZBvlGbEXvKidtzv2JjNCNjCvbyVLSljOTv8tFHNu1FkASxqjDIW39sLKd5nDMA x+fZs8lQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qg4cE-003cMP-0G; Tue, 12 Sep 2023 14:43:46 +0000 To: openwrt-devel@lists.openwrt.org Subject: [PATCH 11/12] uboot-rockchip: add NanoPi R5C support Date: Tue, 12 Sep 2023 22:42:39 +0800 In-Reply-To: <20230912144240.51396-1-cnsztl@immortalwrt.org> References: <20230912144240.51396-1-cnsztl@immortalwrt.org> MIME-Version: 1.0 Message-ID: List-Id: OpenWrt Development List List-Post: X-Patchwork-Original-From: Tianling Shen via openwrt-devel From: Tianling Shen Precedence: list X-Mailman-Version: 2.1.34 X-BeenThere: openwrt-devel@lists.openwrt.org List-Subscribe: , List-Unsubscribe: , List-Archive: Reply-To: Tianling Shen List-Help: Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software. Add support for the FriendlyARM NanoPi R5C. Signed-off-by: Tianling Shen --- package/boot/uboot-rockchip/Makefile | 8 + ...Add-support-for-FriendlyARM-NanoPi-R.patch | 269 ++++++++++++++++++ 2 files changed, 277 insertions(+) create mode 100644 package/boot/uboot-rockchip/patches/104-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 5e55077484..1dad3c1e1c 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -127,6 +127,13 @@ define U-Boot/rk3568/Default TPL:=rk3568_ddr_1560MHz_v1.18.bin endef +define U-Boot/nanopi-r5c-rk3568 + $(U-Boot/rk3568/Default) + NAME:=NanoPi R5C + BUILD_DEVICES:= \ + friendlyarm_nanopi-r5c +endef + define U-Boot/nanopi-r5s-rk3568 $(U-Boot/rk3568/Default) NAME:=NanoPi R5S @@ -146,6 +153,7 @@ UBOOT_TARGETS := \ roc-cc-rk3328 \ rock64-rk3328 \ rock-pi-e-rk3328 \ + nanopi-r5c-rk3568 \ nanopi-r5s-rk3568 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes diff --git a/package/boot/uboot-rockchip/patches/104-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/104-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch new file mode 100644 index 0000000000..d1a5197e7d --- /dev/null +++ b/package/boot/uboot-rockchip/patches/104-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -0,0 +1,269 @@ +From 41538742491c46100f570680c02fbdd0d2b6b880 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Tue, 30 May 2023 15:00:33 +0800 +Subject: [PATCH] rockchip: rk3568: Add support for FriendlyARM NanoPi R5C + +FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device. + +Specification: +- Rockchip RK3568 +- 1/4GB LPDDR4X RAM +- 8/32GB eMMC +- SD card slot +- M.2 Connector +- 2x USB 3.0 Port +- 2x 2500 Base-T (PCIe, r8125) +- HDMI 2.0 +- MIPI DSI/CSI +- USB Type C 5V + +The device tree is taken from kernel v6.4-rc1. + +Reviewed-by: Kever Yang +Signed-off-by: Tianling Shen +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi | 3 + + arch/arm/dts/rk3568-nanopi-r5c.dts | 112 +++++++++++++++++++++ + board/rockchip/evb_rk3568/MAINTAINERS | 7 ++ + configs/nanopi-r5c-rk3568_defconfig | 85 ++++++++++++++++ + 5 files changed, 208 insertions(+) + create mode 100644 arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3568-nanopi-r5c.dts + create mode 100644 configs/nanopi-r5c-rk3568_defconfig + +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3566-anbernic-rgxx3.dtb \ + rk3566-radxa-cm3-io.dtb \ + rk3568-evb.dtb \ ++ rk3568-nanopi-r5c.dtb \ + rk3568-nanopi-r5s.dtb \ + rk3568-rock-3a.dtb + +--- /dev/null ++++ b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi +@@ -0,0 +1,3 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++ ++#include "rk3568-nanopi-r5s-u-boot.dtsi" +--- /dev/null ++++ b/arch/arm/dts/rk3568-nanopi-r5c.dts +@@ -0,0 +1,112 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include "rk3568-nanopi-r5s.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R5C"; ++ compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568"; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&reset_button_pin>; ++ ++ button-reset { ++ debounce-interval = <50>; ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; ++ label = "reset"; ++ linux,code = ; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>; ++ ++ led-lan { ++ color = ; ++ function = LED_FUNCTION_LAN; ++ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ power_led: led-power { ++ color = ; ++ function = LED_FUNCTION_POWER; ++ linux,default-trigger = "heartbeat"; ++ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-wan { ++ color = ; ++ function = LED_FUNCTION_WAN; ++ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-wlan { ++ color = ; ++ function = LED_FUNCTION_WLAN; ++ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; ++ ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie20_reset_pin>; ++ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pcie3x1 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gpio-leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ power_led_pin: power-led-pin { ++ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wlan_led_pin: wlan-led-pin { ++ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie20_reset_pin: pcie20-reset-pin { ++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ rockchip-key { ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; +--- a/board/rockchip/evb_rk3568/MAINTAINERS ++++ b/board/rockchip/evb_rk3568/MAINTAINERS +@@ -7,6 +7,13 @@ F: configs/evb-rk3568_defconfig + F: arch/arm/dts/rk3568-evb-boot.dtsi + F: arch/arm/dts/rk3568-evb.dts + ++NANOPI-R5C ++M: Tianling Shen ++S: Maintained ++F: configs/nanopi-r5c-rk3568_defconfig ++F: arch/arm/dts/rk3568-nanopi-r5c.dts ++F: arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi ++ + NANOPI-R5S + M: Tianling Shen + S: Maintained +--- /dev/null ++++ b/configs/nanopi-r5c-rk3568_defconfig +@@ -0,0 +1,85 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_TEXT_BASE=0x00a00000 ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_NR_DRAM_BANKS=2 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_SPL_SERIAL=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_TARGET_EVB_RK3568=y ++CONFIG_SPL_STACK=0x400000 ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y ++CONFIG_SPL_BSS_START_ADDR=0x4000000 ++CONFIG_SPL_BSS_MAX_SIZE=0x4000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SPL_DM_WARN=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_PSCI=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_ERRNO_STR=y From patchwork Tue Sep 12 14:42:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tianling Shen X-Patchwork-Id: 1833079 X-Patchwork-Delegate: mail@david-bauer.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=LhecGeA6; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RlRGM3qCLz1yp5 for ; Wed, 13 Sep 2023 00:45:47 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type:List-Help: Reply-To:List-Archive:List-Unsubscribe:List-Subscribe:From:List-Post:List-Id: Message-ID:MIME-Version:References:In-Reply-To:Date:Subject:To:Cc: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=XlchwTcM2w1NjhMyV8jdCPQ3uudhRaE4tMgXxcKAwk4=; b=LhecGeA6fBf7/0i3mFlB2VuFKJ 2C4ij+vHnABys9kaPou2vpahF7Vc7pW+IO8b6dO1qdz1maOK1D1nd+Z8FZya/bnAb7B2MTE5laW3i pY+6pFaFjMf1TJk0riTr8SsQQY1IVXxu+UZjHSowqMG7hOTiGzONdIlMlYwa725tEnQ01+FtmPeVV BPegJqPWukU23xt+elMf0D3BaTlCnWkRganQrpW3Pe1ZDbGLUdZqiMtpC4kYZ4PKyiaTrqlUQ56nw +35VMB3xKlt3Yr2mP5EpzfGB5WYgQZyF2uJu6H8hN77SxUaJVeZ10QvyP+2aCgAuWEClWadtZY3Jl xDt2w4Nw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qg4cH-003cQF-0c; Tue, 12 Sep 2023 14:43:49 +0000 To: openwrt-devel@lists.openwrt.org Subject: [PATCH 12/12] rockchip: add NanoPi R5C support Date: Tue, 12 Sep 2023 22:42:40 +0800 In-Reply-To: <20230912144240.51396-1-cnsztl@immortalwrt.org> References: <20230912144240.51396-1-cnsztl@immortalwrt.org> MIME-Version: 1.0 Message-ID: List-Id: OpenWrt Development List List-Post: X-Patchwork-Original-From: Tianling Shen via openwrt-devel From: Tianling Shen Precedence: list X-Mailman-Version: 2.1.34 X-BeenThere: openwrt-devel@lists.openwrt.org List-Subscribe: , List-Unsubscribe: , List-Archive: Reply-To: Tianling Shen List-Help: Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software. Hardware -------- RockChip RK3568 ARM64 (4 cores) 1GB or 4GB LPDDR4X RAM 2x 2500 Base-T 4 LEDs (LAN / WAN / WIFI / POWER) 1 Button (Reset) 8GB or 32GB eMMC on-board Micro-SD Slot M.2 Slot 2x USB 3.0 Port Installation ------------ Uncompress the OpenWrt sysupgrade and write it to a micro SD card or internal eMMC using dd. Signed-off-by: Tianling Shen --- .../armv8/base-files/etc/board.d/01_leds | 4 + .../armv8/base-files/etc/board.d/02_network | 4 + .../etc/hotplug.d/net/40-net-smp-affinity | 4 + target/linux/rockchip/image/armv8.mk | 8 + ...-rockchip-Add-FriendlyARM-NanoPi-R5C.patch | 152 ++++++++++++++++++ ...-fix-button-reset-pin-for-nanopi-r5c.patch | 37 +++++ ...ip-Update-LED-properties-for-NanoPi-.patch | 34 ++++ 7 files changed, 243 insertions(+) create mode 100644 target/linux/rockchip/patches-6.1/013-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch create mode 100644 target/linux/rockchip/patches-6.1/014-v6.4-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r5c.patch diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds index cfab545849..3741f02f0d 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds @@ -16,6 +16,10 @@ xunlong,orangepi-r1-plus-lts) ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth1" ;; +friendlyarm,nanopi-r5c) + ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1" + ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0" + ;; friendlyarm,nanopi-r5s) ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth1" diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index 838a107193..b36701d38a 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -14,6 +14,9 @@ rockchip_setup_interfaces() xunlong,orangepi-r1-plus-lts) ucidef_set_interfaces_lan_wan 'eth1' 'eth0' ;; + friendlyarm,nanopi-r5c) + ucidef_set_interfaces_lan_wan 'eth0' 'eth1' + ;; friendlyarm,nanopi-r5s) ucidef_set_interfaces_lan_wan 'eth1 eth2' 'eth0' ;; @@ -61,6 +64,7 @@ rockchip_setup_macs() wan_mac=$(nanopi_r4s_get_mac wan) lan_mac=$(nanopi_r4s_get_mac lan) ;; + friendlyarm,nanopi-r5c|\ friendlyarm,nanopi-r5s) wan_mac=$(macaddr_generate_from_mmc_cid mmcblk1) lan_mac=$(macaddr_add "$wan_mac" 1) diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity index 161059a87b..84064d4f8b 100644 --- a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity +++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity @@ -40,6 +40,10 @@ friendlyarm,nanopi-r4s) set_interface_core 10 "eth0" set_interface_core 20 "eth1" ;; +friendlyarm,nanopi-r5c) + set_interface_core 2 "eth0" + set_interface_core 4 "eth1" + ;; friendlyarm,nanopi-r5s) set_interface_core 2 "eth0" set_interface_core 4 "eth1" diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index e836e3c91d..9ca6f83454 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -47,6 +47,14 @@ define Device/friendlyarm_nanopi-r4s endef TARGET_DEVICES += friendlyarm_nanopi-r4s +define Device/friendlyarm_nanopi-r5c + DEVICE_VENDOR := FriendlyARM + DEVICE_MODEL := NanoPi R5C + SOC := rk3568 + DEVICE_PACKAGES := kmod-r8169 kmod-rtw88 rtl8822ce-firmware wpad-basic-wolfssl +endef +TARGET_DEVICES += friendlyarm_nanopi-r5c + define Device/friendlyarm_nanopi-r5s DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPi R5S diff --git a/target/linux/rockchip/patches-6.1/013-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch b/target/linux/rockchip/patches-6.1/013-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch new file mode 100644 index 0000000000..0465d80cba --- /dev/null +++ b/target/linux/rockchip/patches-6.1/013-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch @@ -0,0 +1,152 @@ +From 05620031408ac6cfc6d5c048431827e49aa0ade1 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Sat, 18 Mar 2023 16:37:43 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R5C + +FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device. + +Specification: +- Rockchip RK3568 +- 1/4GB LPDDR4X RAM +- 8/32GB eMMC +- SD card slot +- M.2 Connector +- 2x USB 3.0 Port +- 2x 2500 Base-T (PCIe, r8125) +- HDMI 2.0 +- MIPI DSI/CSI +- USB Type C 5V + +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20230318083745.6181-4-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3568-nanopi-r5c.dts | 112 ++++++++++++++++++ + 2 files changed, 113 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -74,5 +74,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts +@@ -0,0 +1,112 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include "rk3568-nanopi-r5s.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R5C"; ++ compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568"; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&reset_button_pin>; ++ ++ button-reset { ++ debounce-interval = <50>; ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; ++ label = "reset"; ++ linux,code = ; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>; ++ ++ led-lan { ++ color = ; ++ function = LED_FUNCTION_LAN; ++ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ power_led: led-power { ++ color = ; ++ function = LED_FUNCTION_POWER; ++ linux,default-trigger = "heartbeat"; ++ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-wan { ++ color = ; ++ function = LED_FUNCTION_WAN; ++ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-wlan { ++ color = ; ++ function = LED_FUNCTION_WLAN; ++ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; ++ ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie20_reset_pin>; ++ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pcie3x1 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gpio-leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ power_led_pin: power-led-pin { ++ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wlan_led_pin: wlan-led-pin { ++ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie20_reset_pin: pcie20-reset-pin { ++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ rockchip-key { ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.1/014-v6.4-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r5c.patch b/target/linux/rockchip/patches-6.1/014-v6.4-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r5c.patch new file mode 100644 index 0000000000..0e59f0275b --- /dev/null +++ b/target/linux/rockchip/patches-6.1/014-v6.4-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r5c.patch @@ -0,0 +1,37 @@ +From 5325593377f07de31f7e473a9677a28a04c891f3 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Thu, 11 May 2023 00:18:50 +0800 +Subject: [PATCH] arm64: dts: rockchip: fix button reset pin for nanopi r5c + +The reset pin was wrongly assigned due to a copy/paste error, +fix it to match actual gpio pin. + +While at it, remove a blank line from nanopi r5s dts. + +Fixes: 05620031408a ("arm64: dts: rockchip: Add FriendlyARM NanoPi R5C") +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20230510161850.4866-1-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 1 - + 2 files changed, 1 insertion(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts +@@ -106,7 +106,7 @@ + + rockchip-key { + reset_button_pin: reset-button-pin { +- rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +@@ -134,4 +134,3 @@ + }; + }; + }; +- diff --git a/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch b/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch index 8339ef5dbc..64dc433a30 100644 --- a/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch +++ b/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch @@ -11,6 +11,40 @@ to update LED settings. Signed-off-by: Tianling Shen --- +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts +@@ -32,27 +32,22 @@ + pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>; + + led-lan { +- color = ; +- function = LED_FUNCTION_LAN; ++ label = "green:lan"; + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + }; + + power_led: led-power { +- color = ; +- function = LED_FUNCTION_POWER; +- linux,default-trigger = "heartbeat"; ++ label = "red:power"; + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + + led-wan { +- color = ; +- function = LED_FUNCTION_WAN; ++ label = "green:wan"; + gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + }; + + led-wlan { +- color = ; +- function = LED_FUNCTION_WLAN; ++ label = "green:wlan"; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + }; + }; --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts @@ -23,29 +23,22 @@