From patchwork Wed Sep 6 17:50:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edwin Lu X-Patchwork-Id: 1830501 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=Ke0iImw1; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Rgqfj1QTWz1yh5 for ; Thu, 7 Sep 2023 03:50:53 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0B8FB38555A3 for ; Wed, 6 Sep 2023 17:50:51 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by sourceware.org (Postfix) with ESMTPS id D015D3858430 for ; Wed, 6 Sep 2023 17:50:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D015D3858430 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-68a42d06d02so116693b3a.0 for ; Wed, 06 Sep 2023 10:50:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1694022636; x=1694627436; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z6bsBywsqMHHZFHUpVGUvbYj4rxpQ4gVg/6ANrBvX4s=; b=Ke0iImw1vzJHijk/rjAZbN0sdzOuESEr0IRb6/1ENTzhuoPstuZqeLPwjO9ZwQPLAS 540RW8UlNMtQMdVjPTwmlwZMw1xogFYwrJMl96Y+y3UIMMlGmbp+sORObwpo/FioHSrS gLdiMdC0TAt3mVDGPLC4JsDkFnVwPSUWur8ZTqBSXLiodAnitPHkh6Xnbpey3D9P84kK uHF33WRfTtqOVvNnBdQowG2WrQuMN2Lc8NrEdfyjdthuULP1Gi0AxF1+Ckp4kPsGvEXS +4TRAYkdrU84u+06V5Nlc7n2AZpQji2B1cq9SEhtUyrSHcMmjB3P5CWYrLKfw3rhfKdh 9obQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1694022636; x=1694627436; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z6bsBywsqMHHZFHUpVGUvbYj4rxpQ4gVg/6ANrBvX4s=; b=UlkkprVgyvPG5KD1TgHMmtp+fb1p60DFXG+Scfs6TilXO7DfXyuz+ug54qOsULtb5Z kyna3FpJC/wxxEQ0GlqYqyJG69KSoTIt2pYW63G9xg2ipadEtDEIDkEsHzeLYwMCHnKC 0f5tBZ3t1diiSZaps8CV7llmGe2Y1mr/lnwjgVrmqSGAkiuM825F16/TgKvS/kUWe2B5 RJmrtnjCcoGQDM761YfoVDrTxzktNy1Q5pipD0x8t1KQzvtqO7dVRqmgcEezYn6W58oq aZ8JxV4IuWoSYEbMD+qUWeAayb3Y21/qUWxDAwseJxSUYwuOR88LhCe2DiiuEdmPrlCL 9s/A== X-Gm-Message-State: AOJu0YyKXZMS1TP13/N82d05u3bpDxFN3P+m9wBAQ2t5GlSjP1HCsbeq GPzYby7yhnIPEIkUYGFEJiBB7xNx1p0C7pWYEiE= X-Google-Smtp-Source: AGHT+IFyxX+aOhErmZbZPYu1udwVJQtQcfEwyHpQeun/eXsGvtCJSFDJgZ7noJZjtLF+zAW5owjjmA== X-Received: by 2002:a05:6a20:8f20:b0:134:d4d3:f0a8 with SMTP id b32-20020a056a208f2000b00134d4d3f0a8mr17091111pzk.3.1694022635780; Wed, 06 Sep 2023 10:50:35 -0700 (PDT) Received: from ewlu.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id f8-20020aa782c8000000b00687a4b70d1esm11017428pfn.218.2023.09.06.10.50.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 10:50:35 -0700 (PDT) From: Edwin Lu To: gcc-patches@gcc.gnu.org Subject: [PATCH 1/5] RISC-V: Update Types for Vector Instructions Date: Wed, 6 Sep 2023 10:50:19 -0700 Message-ID: <20230906175025.935887-2-ewlu@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230906175025.935887-1-ewlu@rivosinc.com> References: <20230906175025.935887-1-ewlu@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gnu-toolchain@rivosinc.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds types to vector instructions that were added after or were missed by the original patch https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html gcc/ChangeLog: * config/riscv/autovec-opt.md: Update types * config/riscv/autovec.md: likewise Signed-off-by: Edwin Lu --- gcc/config/riscv/autovec-opt.md | 42 ++++++++++++++++++++++----------- gcc/config/riscv/autovec.md | 28 +++++++++++++++------- 2 files changed, 47 insertions(+), 23 deletions(-) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 1ca5ce97193..6cc1a01629c 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -728,7 +728,8 @@ (define_insn_and_split "*cond_abs" gen_int_mode (GET_MODE_NUNITS (mode), Pmode), const0_rtx)); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine vlmax neg and UNSPEC_VCOPYSIGN (define_insn_and_split "*copysign_neg" @@ -746,7 +747,8 @@ (define_insn_and_split "*copysign_neg" riscv_vector::emit_vlmax_insn (code_for_pred_ncopysign (mode), riscv_vector::BINARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine sign_extend/zero_extend(vf2) and vcond_mask (define_insn_and_split "*cond_" @@ -765,7 +767,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine sign_extend/zero_extend(vf4) and vcond_mask (define_insn_and_split "*cond_" @@ -784,7 +787,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine sign_extend/zero_extend(vf8) and vcond_mask (define_insn_and_split "*cond_" @@ -803,7 +807,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine trunc(vf2) + vcond_mask (define_insn_and_split "*cond_trunc" @@ -823,7 +828,8 @@ (define_insn_and_split "*cond_trunc" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine FP sign_extend/zero_extend(vf2) and vcond_mask (define_insn_and_split "*cond_extend" @@ -842,7 +848,8 @@ (define_insn_and_split "*cond_extend" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine FP trunc(vf2) + vcond_mask (define_insn_and_split "*cond_trunc" @@ -862,7 +869,8 @@ (define_insn_and_split "*cond_trunc" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(FP->INT) + vcond_mask (define_insn_and_split "*cond_" @@ -882,7 +890,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(INT->FP) + vcond_mask (define_insn_and_split "*cond_" @@ -902,7 +911,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(FP->2xINT) + vcond_mask (define_insn_and_split "*cond_" @@ -922,7 +932,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(INT->2xFP) + vcond_mask (define_insn_and_split "*cond_" @@ -942,7 +953,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(2xFP->INT) + vcond_mask (define_insn_and_split "*cond_" @@ -962,7 +974,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(2xINT->FP) + vcond_mask (define_insn_and_split "*cond_2" @@ -982,4 +995,5 @@ (define_insn_and_split "*cond_2" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 0f9d1fe2c8e..047a66b238f 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -558,6 +558,7 @@ (define_insn_and_split "@vcond_mask_" riscv_vector::MERGE_OP, operands); DONE; } + [(set_attr "type" "vector")] ) ;; ------------------------------------------------------------------------- @@ -645,7 +646,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred_vf4 (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vext")]) (define_insn_and_split "2" [(set (match_operand:VOEXTI 0 "register_operand") @@ -659,7 +661,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred_vf8 (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vext")]) ;; ------------------------------------------------------------------------- ;; ---- [INT] Truncation @@ -815,7 +818,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vfcvtftoi")]) ;; ------------------------------------------------------------------------- ;; ---- [FP<-INT] Conversions @@ -837,7 +841,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands); DONE; -}) +} +[(set_attr "type" "vfcvtitof")]) ;; ========================================================================= ;; == Widening/narrowing Conversions @@ -862,7 +867,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred_widen (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vfwcvtftoi")]) ;; ------------------------------------------------------------------------- ;; ---- [FP<-INT] Widening Conversions @@ -883,7 +889,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred_widen (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vfwcvtitof")]) ;; ------------------------------------------------------------------------- ;; ---- [INT<-FP] Narrowing Conversions @@ -904,7 +911,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred_narrow (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vfncvtftoi")]) ;; ------------------------------------------------------------------------- ;; ---- [FP<-INT] Narrowing Conversions @@ -925,7 +933,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred_narrow (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands); DONE; -}) +} +[(set_attr "type" "vfncvtitof")]) ;; ========================================================================= ;; == Unary arithmetic @@ -986,7 +995,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vector")]) ;; ------------------------------------------------------------------------------- ;; - [FP] Square root From patchwork Wed Sep 6 17:50:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edwin Lu X-Patchwork-Id: 1830502 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=LIXDhLIw; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Rgqfm4PNRz1yh5 for ; Thu, 7 Sep 2023 03:50:56 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2B301385DC2F for ; Wed, 6 Sep 2023 17:50:54 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by sourceware.org (Postfix) with ESMTPS id 7F9D0385828E for ; Wed, 6 Sep 2023 17:50:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7F9D0385828E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-68a3cae6d94so119821b3a.0 for ; Wed, 06 Sep 2023 10:50:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1694022637; x=1694627437; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BbDp4nJdvtiTJzMSVizKyoXp8V6r0wLrapWu9pynrzg=; b=LIXDhLIwSBGWTgh3uEHIiDhDFWg4dZ9Tdl07EonHUp9BVYkdbJrBMo3O0YC5v4lcxq by8+A9WtF6XRxIhZy8JdObR00z3kkvOulLdhODcDmdTMnoBlgE0bq6YrGeehiCLqZ9RZ Lqsm/xb8U6MG4jgCTIVjReucOs33Fs6qKMWHFFv5/+E2Ug5sHI09jfh0kVoNTf7yk0qV RJ8T0ZnQO/EkBK+8T1OjP068A3COm74F+IODiEEp23vBGHQvOcX82YZlj7I6NtxULJyL g+WFuFx4tFteFVSQZ/N+yZVG6RBjyUQTA0/ljkS1yrzXpFur1GOZQXZCSEcS0RckALhz 2DeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1694022637; x=1694627437; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BbDp4nJdvtiTJzMSVizKyoXp8V6r0wLrapWu9pynrzg=; b=iCmOP/jR2KBa6cUUsjB1peo0Yq9TC78qL6Tl6RSDqhShqINK0EvWqLHE4eenzVtX6G HKKJxzWeVjIV4oDnwMTZzCcdQ+T4MDhs8ZfFH8CgMSVDz9CwJJRMs4XEP8DW6cI82v2w fmfp+0uWUPjsFFbcxiPqkuUbpBGtAJIAJxm78sj4JqSfjZ/1nMqiFTN/blucxdAybaIL x+2v9/3dPdGVbxD91fC62MId1w3KidkvJWvPxHPUYDRL+gJwP8l70DCdUkyIw8cXTS5Y a8zoDtSVTiAOO5HaXm77KHa1lxoaJpPUvz/GoZ5YjCNMxM52qegCauSDRXViJC+y65qV uhRQ== X-Gm-Message-State: AOJu0YxmI0bRbbeA1wAieiS7c7IJ51lC6smzSIe4qn9GOR9NfGOmuIUW KwkDqrRd7Z04C1eFEfPtqSSD9fP/S/l2isjX3fQ= X-Google-Smtp-Source: AGHT+IHsqzUGuO2Wl8KeWiEVqFU4SrBr0D7KfUYlnFtoDuUsEw260xGKw/89UJMyMdtZusJCFAhchQ== X-Received: by 2002:a05:6a00:23c2:b0:68a:3fbb:3985 with SMTP id g2-20020a056a0023c200b0068a3fbb3985mr20921975pfc.20.1694022637068; Wed, 06 Sep 2023 10:50:37 -0700 (PDT) Received: from ewlu.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id f8-20020aa782c8000000b00687a4b70d1esm11017428pfn.218.2023.09.06.10.50.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 10:50:36 -0700 (PDT) From: Edwin Lu To: gcc-patches@gcc.gnu.org Subject: [PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions Date: Wed, 6 Sep 2023 10:50:20 -0700 Message-ID: <20230906175025.935887-3-ewlu@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230906175025.935887-1-ewlu@rivosinc.com> References: <20230906175025.935887-1-ewlu@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gnu-toolchain@rivosinc.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds types to the untyped zc instructions. Creates a new type "csr" for these instructions for now. gcc/ChangeLog: * config/riscv/riscv.md: Add "csr" type * config/riscv/zc.md: Update types Signed-off-by: Edwin Lu --- gcc/config/riscv/riscv.md | 3 +- gcc/config/riscv/zc.md | 102 +++++++++++++++++++------------------- 2 files changed, 54 insertions(+), 51 deletions(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index d80b6938f84..6684ad89cff 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -312,6 +312,7 @@ (define_attr "ext_enabled" "no,yes" ;; condmove conditional moves ;; cbo cache block instructions ;; crypto cryptography instructions +;; csr code size reduction instructions ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. ;; rdvlenb vector byte length vlenb csrr read ;; rdvl vector length vl csrr read @@ -421,7 +422,7 @@ (define_attr "type" mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip, rotate,clmul,min,max,minu,maxu,clz,ctz,cpop, - atomic,condmove,cbo,crypto,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl, + atomic,condmove,cbo,crypto,csr,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl, vlde,vste,vldm,vstm,vlds,vsts, vldux,vldox,vstux,vstox,vldff,vldr,vstr, vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff, diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md index 77b28adde95..86f1afd66cb 100644 --- a/gcc/config/riscv/zc.md +++ b/gcc/config/riscv/zc.md @@ -27,7 +27,7 @@ (define_insn "@gpr_multi_pop_up_to_ra_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_pop_up_to_s0_" [(set (reg:X SP_REGNUM) @@ -41,7 +41,7 @@ (define_insn "@gpr_multi_pop_up_to_s0_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_pop_up_to_s1_" [(set (reg:X SP_REGNUM) @@ -58,7 +58,7 @@ (define_insn "@gpr_multi_pop_up_to_s1_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s1}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_pop_up_to_s2_" [(set (reg:X SP_REGNUM) @@ -78,7 +78,7 @@ (define_insn "@gpr_multi_pop_up_to_s2_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s2}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_pop_up_to_s3_" [(set (reg:X SP_REGNUM) @@ -101,7 +101,7 @@ (define_insn "@gpr_multi_pop_up_to_s3_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s3}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_pop_up_to_s4_" [(set (reg:X SP_REGNUM) @@ -127,7 +127,7 @@ (define_insn "@gpr_multi_pop_up_to_s4_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s4}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_pop_up_to_s5_" [(set (reg:X SP_REGNUM) @@ -156,7 +156,7 @@ (define_insn "@gpr_multi_pop_up_to_s5_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s5}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_pop_up_to_s6_" [(set (reg:X SP_REGNUM) @@ -188,7 +188,7 @@ (define_insn "@gpr_multi_pop_up_to_s6_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s6}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_pop_up_to_s7_" [(set (reg:X SP_REGNUM) @@ -223,7 +223,7 @@ (define_insn "@gpr_multi_pop_up_to_s7_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s7}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_pop_up_to_s8_" [(set (reg:X SP_REGNUM) @@ -261,7 +261,7 @@ (define_insn "@gpr_multi_pop_up_to_s8_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s8}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_pop_up_to_s9_" [(set (reg:X SP_REGNUM) @@ -302,7 +302,7 @@ (define_insn "@gpr_multi_pop_up_to_s9_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s9}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_pop_up_to_s11_" [(set (reg:X SP_REGNUM) @@ -349,7 +349,7 @@ (define_insn "@gpr_multi_pop_up_to_s11_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s11}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popret_up_to_ra_" [(set (reg:X SP_REGNUM) @@ -362,7 +362,7 @@ (define_insn "@gpr_multi_popret_up_to_ra_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popret_up_to_s0_" [(set (reg:X SP_REGNUM) @@ -378,7 +378,7 @@ (define_insn "@gpr_multi_popret_up_to_s0_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popret_up_to_s1_" [(set (reg:X SP_REGNUM) @@ -397,7 +397,7 @@ (define_insn "@gpr_multi_popret_up_to_s1_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s1}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popret_up_to_s2_" [(set (reg:X SP_REGNUM) @@ -419,7 +419,7 @@ (define_insn "@gpr_multi_popret_up_to_s2_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s2}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popret_up_to_s3_" [(set (reg:X SP_REGNUM) @@ -444,7 +444,7 @@ (define_insn "@gpr_multi_popret_up_to_s3_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s3}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popret_up_to_s4_" [(set (reg:X SP_REGNUM) @@ -472,7 +472,7 @@ (define_insn "@gpr_multi_popret_up_to_s4_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s4}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popret_up_to_s5_" [(set (reg:X SP_REGNUM) @@ -503,7 +503,7 @@ (define_insn "@gpr_multi_popret_up_to_s5_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s5}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popret_up_to_s6_" [(set (reg:X SP_REGNUM) @@ -537,7 +537,7 @@ (define_insn "@gpr_multi_popret_up_to_s6_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s6}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popret_up_to_s7_" [(set (reg:X SP_REGNUM) @@ -574,7 +574,7 @@ (define_insn "@gpr_multi_popret_up_to_s7_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s7}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popret_up_to_s8_" [(set (reg:X SP_REGNUM) @@ -614,7 +614,7 @@ (define_insn "@gpr_multi_popret_up_to_s8_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s8}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popret_up_to_s9_" [(set (reg:X SP_REGNUM) @@ -657,7 +657,7 @@ (define_insn "@gpr_multi_popret_up_to_s9_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s9}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popret_up_to_s11_" [(set (reg:X SP_REGNUM) @@ -706,7 +706,7 @@ (define_insn "@gpr_multi_popret_up_to_s11_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s11}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popretz_up_to_ra_" [(set (reg:X SP_REGNUM) @@ -722,7 +722,7 @@ (define_insn "@gpr_multi_popretz_up_to_ra_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popretz_up_to_s0_" [(set (reg:X SP_REGNUM) @@ -741,7 +741,7 @@ (define_insn "@gpr_multi_popretz_up_to_s0_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popretz_up_to_s1_" [(set (reg:X SP_REGNUM) @@ -763,7 +763,7 @@ (define_insn "@gpr_multi_popretz_up_to_s1_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s1}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popretz_up_to_s2_" [(set (reg:X SP_REGNUM) @@ -788,7 +788,7 @@ (define_insn "@gpr_multi_popretz_up_to_s2_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s2}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popretz_up_to_s3_" [(set (reg:X SP_REGNUM) @@ -816,7 +816,7 @@ (define_insn "@gpr_multi_popretz_up_to_s3_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s3}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popretz_up_to_s4_" [(set (reg:X SP_REGNUM) @@ -847,7 +847,7 @@ (define_insn "@gpr_multi_popretz_up_to_s4_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s4}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popretz_up_to_s5_" [(set (reg:X SP_REGNUM) @@ -881,7 +881,7 @@ (define_insn "@gpr_multi_popretz_up_to_s5_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s5}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popretz_up_to_s6_" [(set (reg:X SP_REGNUM) @@ -918,7 +918,7 @@ (define_insn "@gpr_multi_popretz_up_to_s6_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s6}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popretz_up_to_s7_" [(set (reg:X SP_REGNUM) @@ -958,7 +958,7 @@ (define_insn "@gpr_multi_popretz_up_to_s7_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s7}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popretz_up_to_s8_" [(set (reg:X SP_REGNUM) @@ -1001,7 +1001,7 @@ (define_insn "@gpr_multi_popretz_up_to_s8_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s8}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popretz_up_to_s9_" [(set (reg:X SP_REGNUM) @@ -1047,7 +1047,7 @@ (define_insn "@gpr_multi_popretz_up_to_s9_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s9}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_popretz_up_to_s11_" [(set (reg:X SP_REGNUM) @@ -1099,7 +1099,7 @@ (define_insn "@gpr_multi_popretz_up_to_s11_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s11}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_push_up_to_ra_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1110,7 +1110,7 @@ (define_insn "@gpr_multi_push_up_to_ra_" (match_operand 0 "stack_push_up_to_ra_operand" "I")))] "TARGET_ZCMP" "cm.push {ra}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_push_up_to_s0_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1124,7 +1124,7 @@ (define_insn "@gpr_multi_push_up_to_s0_" (match_operand 0 "stack_push_up_to_s0_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_push_up_to_s1_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1141,7 +1141,7 @@ (define_insn "@gpr_multi_push_up_to_s1_" (match_operand 0 "stack_push_up_to_s1_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s1}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_push_up_to_s2_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1161,7 +1161,7 @@ (define_insn "@gpr_multi_push_up_to_s2_" (match_operand 0 "stack_push_up_to_s2_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s2}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_push_up_to_s3_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1184,7 +1184,7 @@ (define_insn "@gpr_multi_push_up_to_s3_" (match_operand 0 "stack_push_up_to_s3_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s3}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_push_up_to_s4_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1210,7 +1210,7 @@ (define_insn "@gpr_multi_push_up_to_s4_" (match_operand 0 "stack_push_up_to_s4_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s4}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_push_up_to_s5_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1239,7 +1239,7 @@ (define_insn "@gpr_multi_push_up_to_s5_" (match_operand 0 "stack_push_up_to_s5_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s5}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_push_up_to_s6_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1271,7 +1271,7 @@ (define_insn "@gpr_multi_push_up_to_s6_" (match_operand 0 "stack_push_up_to_s6_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s6}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_push_up_to_s7_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1306,7 +1306,7 @@ (define_insn "@gpr_multi_push_up_to_s7_" (match_operand 0 "stack_push_up_to_s7_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s7}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_push_up_to_s8_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1344,7 +1344,7 @@ (define_insn "@gpr_multi_push_up_to_s8_" (match_operand 0 "stack_push_up_to_s8_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s8}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_push_up_to_s9_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1385,7 +1385,7 @@ (define_insn "@gpr_multi_push_up_to_s9_" (match_operand 0 "stack_push_up_to_s9_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s9}, %0" -) +[(set_attr "type" "csr")]) (define_insn "@gpr_multi_push_up_to_s11_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1432,7 +1432,7 @@ (define_insn "@gpr_multi_push_up_to_s11_" (match_operand 0 "stack_push_up_to_s11_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s11}, %0" -) +[(set_attr "type" "csr")]) ;; ZCMP mv (define_insn "*mva01s" @@ -1443,7 +1443,8 @@ (define_insn "*mva01s" "TARGET_ZCMP && (REGNO (operands[2]) != REGNO (operands[0]))" { return (REGNO (operands[0]) == A0_REGNUM)?"cm.mva01s\t%1,%3":"cm.mva01s\t%3,%1"; } - [(set_attr "mode" "")]) + [(set_attr "mode" "") + (set_attr "type" "csr")]) (define_insn "*mvsa01" [(set (match_operand:X 0 "zcmp_mv_sreg_operand" "=r") @@ -1454,4 +1455,5 @@ (define_insn "*mvsa01" && (REGNO (operands[0]) != REGNO (operands[2])) && (REGNO (operands[1]) != REGNO (operands[3]))" { return (REGNO (operands[1]) == A0_REGNUM)?"cm.mvsa01\t%0,%2":"cm.mvsa01\t%2,%0"; } - [(set_attr "mode" "")]) + [(set_attr "mode" "") + (set_attr "type" "csr")]) From patchwork Wed Sep 6 17:50:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edwin Lu X-Patchwork-Id: 1830504 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=bCUrMPe9; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RgqgG3k8rz1yh5 for ; Thu, 7 Sep 2023 03:51:22 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BAAF13839DDF for ; Wed, 6 Sep 2023 17:51:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by sourceware.org (Postfix) with ESMTPS id 52B223858023 for ; Wed, 6 Sep 2023 17:50:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 52B223858023 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-68becf931d0so96426b3a.3 for ; Wed, 06 Sep 2023 10:50:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1694022638; x=1694627438; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aZvJDF5Im77YKsudS3oXPtKABu43nwre6qoWtOd+UFE=; b=bCUrMPe9XjncN+9wHgD5Zfkl4UZltkwpNcYV5tc7OU+5SBmy6XVexd0maBH06s9qsd Z21zZD+FPxhQVSVp4IidS8xwPanjVz9lQxHdYhhOEFxIeM5YQuaFdfehnBsJsB/Q60kj 8NWU/uCKWGznqkUiS20HY4wpV9rI8jsMj/UgKbq5FUovlJBSwp0Y0I7/R/iPLVIEEehq rurSreVGXxIbnK91uoal5iEeuBGnxzN+pn/sTWBAke1S8OR+E9HTAscTYtjZKCuavqXv PAIQixR/CgTX8csIPxANJd7PeQOFFP7mYAFjIN229jQ8TVMepdt56/ZDCYCgAAPZhJ+r Ap4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1694022638; x=1694627438; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aZvJDF5Im77YKsudS3oXPtKABu43nwre6qoWtOd+UFE=; b=Ebo/heLZYOMTop6DxWYD+ILkL1O1Zlvny53EauIpCMy6tEJLkyVTi+bwZwG8eYDHA7 rqqtBhvqmW81bd/uFGYPBOUffJEHj0VW7JThOAe8KJAYeJXvJFmaFtrIUakgJXfBxuze N8vZxpSYajT8I1HnqkyOMXg5sHpZGVcIWWh7CF9jfT2Z4CjcrhtSlqn9UbeQB3eDiGEv g39UFMaWHA54JPdAt4KglaVOZaiI2lJ3zZOfzhpG3fY0axRCpXWDRzsxeIGNqjJLD6kL EvsqKtvtH95SDS7eVWUzyZ/33XnpeSU8+mNvhGq3eY92DuKKZVMFvVJ6cQ5Ha+pRzmwL JaIQ== X-Gm-Message-State: AOJu0Yw+Wa9zop1i4peltuKetJON4Risk+puCnnoxQ9VZndPzqMCfvsC rLZ+drI4dYr6tFB8ObG1b7xFZuxDWty2K5fnEp8= X-Google-Smtp-Source: AGHT+IFbPS/x8bKQUjJ93QVsjJme0ewr2Um9Ph4/vjjuFjf59axwq99r8Cr/x0Pum2I+nHz1GtX+zg== X-Received: by 2002:a05:6a20:e123:b0:153:8183:2917 with SMTP id kr35-20020a056a20e12300b0015381832917mr2849583pzb.21.1694022638232; Wed, 06 Sep 2023 10:50:38 -0700 (PDT) Received: from ewlu.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id f8-20020aa782c8000000b00687a4b70d1esm11017428pfn.218.2023.09.06.10.50.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 10:50:37 -0700 (PDT) From: Edwin Lu To: gcc-patches@gcc.gnu.org Subject: [PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions Date: Wed, 6 Sep 2023 10:50:21 -0700 Message-ID: <20230906175025.935887-4-ewlu@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230906175025.935887-1-ewlu@rivosinc.com> References: <20230906175025.935887-1-ewlu@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gnu-toolchain@rivosinc.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch creates a new "zicond" type and updates all zicond instructions with that type. gcc/ChangeLog: * config/riscv/riscv.md: Add "zicond" type * config/riscv/zicond.md: Update types Signed-off-by: Edwin Lu --- gcc/config/riscv/riscv.md | 5 +++-- gcc/config/riscv/zicond.md | 8 ++++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 6684ad89cff..c329f55db43 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -313,6 +313,7 @@ (define_attr "ext_enabled" "no,yes" ;; cbo cache block instructions ;; crypto cryptography instructions ;; csr code size reduction instructions +;; zicond zicond instructions ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. ;; rdvlenb vector byte length vlenb csrr read ;; rdvl vector length vl csrr read @@ -422,8 +423,8 @@ (define_attr "type" mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip, rotate,clmul,min,max,minu,maxu,clz,ctz,cpop, - atomic,condmove,cbo,crypto,csr,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl, - vlde,vste,vldm,vstm,vlds,vsts, + atomic,condmove,cbo,crypto,csr,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm, + vsetvl, vlde,vste,vldm,vstm,vlds,vsts, vldux,vldox,vstux,vstox,vldff,vldr,vstr, vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff, vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax, diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md index 1721e1011ea..0269bd14399 100644 --- a/gcc/config/riscv/zicond.md +++ b/gcc/config/riscv/zicond.md @@ -30,7 +30,7 @@ (define_insn "*czero.." (const_int 0)))] "TARGET_ZICOND" "czero.\t%0,%2,%1" -) +[(set_attr "type" "zicond")]) (define_insn "*czero.." [(set (match_operand:GPR 0 "register_operand" "=r") @@ -40,7 +40,7 @@ (define_insn "*czero.." (match_operand:GPR 2 "register_operand" "r")))] "TARGET_ZICOND" "czero.\t%0,%2,%1" -) +[(set_attr "type" "zicond")]) ;; Special optimization under eq/ne in primitive semantics (define_insn "*czero.eqz..opt1" @@ -51,7 +51,7 @@ (define_insn "*czero.eqz..opt1" (match_operand:GPR 3 "register_operand" "r")))] "TARGET_ZICOND && rtx_equal_p (operands[1], operands[2])" "czero.eqz\t%0,%3,%1" -) +[(set_attr "type" "zicond")]) (define_insn "*czero.nez..opt2" [(set (match_operand:GPR 0 "register_operand" "=r") @@ -61,7 +61,7 @@ (define_insn "*czero.nez..opt2" (match_operand:GPR 3 "register_operand" "1")))] "TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])" "czero.eqz\t%0,%2,%1" -) +[(set_attr "type" "zicond")]) ;; Combine creates this form in some cases (particularly the coremark ;; CRC loop. From patchwork Wed Sep 6 17:50:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edwin Lu X-Patchwork-Id: 1830503 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=vRZChc/s; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Rgqfv3VXmz1yh5 for ; Thu, 7 Sep 2023 03:51:03 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C1E7C386545A for ; Wed, 6 Sep 2023 17:50:59 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by sourceware.org (Postfix) with ESMTPS id D25A63858439 for ; Wed, 6 Sep 2023 17:50:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D25A63858439 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pg1-x535.google.com with SMTP id 41be03b00d2f7-564b6276941so110881a12.3 for ; Wed, 06 Sep 2023 10:50:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1694022639; x=1694627439; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sokeNtOleIgwngJvumHf116fKgYi1huOZOaHd0KctAQ=; b=vRZChc/s9HTZl59Bn5XP+eKXePC+6AZOv3apcPTE/Ziz8YjoXllag+ePr8EyKdRD/O znuf7W/0EbfHtpV4q+MM7CfgM+RvO42JdQK4Z1oq0JC0nVaC/LfziZMYa4ZlT7dxRO0V Zp+uHlZ4J6tbBuyP7EPPsOpnmHtWc2C1xEbgXUrEqUKr2LbwQS4II6hbL1hzJGP8R0IC yL9KNLNl0nCAta474BG6wCltWS5eTU/PVn8PDuSsbZiaqBLHGx0Y0dFG5m168gaRxmWF tSP1uqKTGXhjD+M1RVGXmz3euens+69AfxNnfP6jLwk/71qLk8VnepV+B4awcmGLQcPS Tp+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1694022639; x=1694627439; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sokeNtOleIgwngJvumHf116fKgYi1huOZOaHd0KctAQ=; b=Y4YZB31MVYqyd95QGBuXoBUidp0TahgJIK6u5hwIJuBuqkttiCPfGLT6MGNtsZoseY HBAcx/bbAVQndxiYSIWep1UHYiKh6SvqOv6s6GII4gn5Ibf35Q9Oj9CMcKiegXXLd+wd LMM5fcxLyq81dQRLC+XkeAWkGzdREgN5jGn2spbfhGjqn6EaaJXJuUV5UVWQgqz9lMaE KJRGUHlkTbVVFhNIUfdlQdIJnSmxa5DnEs3YhIwvW5tpblP5sZ8oXcrpOiJliq21HGeX jo9JjC+dbgoqKdJ+q5RgdRQhBB2FJNQehRIgwNJ2rbLwHvYeYz7+k/kkqdVzP7FKQhSu 2kvA== X-Gm-Message-State: AOJu0YxDWut2HNSIhS2JoNOHmx5/BMo0hpd3execuphbZ/hUveWIyXtD uJidG3lelPR/hbYWmr03AQOi7cB80+Ep9kntT9o= X-Google-Smtp-Source: AGHT+IE7Qcdqo93nNHPI0fwH47V5SYI9vU7NHBPuD0LoHB0RkcODrXKQ9xalDhSoez2roSvlQBQAHw== X-Received: by 2002:a05:6a20:3ca6:b0:145:47af:57d8 with SMTP id b38-20020a056a203ca600b0014547af57d8mr22111174pzj.2.1694022639665; Wed, 06 Sep 2023 10:50:39 -0700 (PDT) Received: from ewlu.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id f8-20020aa782c8000000b00687a4b70d1esm11017428pfn.218.2023.09.06.10.50.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 10:50:39 -0700 (PDT) From: Edwin Lu To: gcc-patches@gcc.gnu.org Subject: [PATCH 4/5] RISC-V: Update Types for RISC-V Instructions Date: Wed, 6 Sep 2023 10:50:22 -0700 Message-ID: <20230906175025.935887-5-ewlu@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230906175025.935887-1-ewlu@rivosinc.com> References: <20230906175025.935887-1-ewlu@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gnu-toolchain@rivosinc.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds types to riscv instructions that were added or were missed by the original patch https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html gcc/ChangeLog: * config/riscv/riscv.md: Update types Signed-off-by: Edwin Lu --- gcc/config/riscv/riscv.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index c329f55db43..c1cecd27815 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2223,6 +2223,7 @@ (define_insn "movsidf2_low_rv32" "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA" "fmv.x.w\t%0,%1" [(set_attr "move_type" "fmove") + (set_attr "type" "fmove") (set_attr "mode" "DF")]) @@ -2235,6 +2236,7 @@ (define_insn "movsidf2_high_rv32" "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA" "fmvh.x.d\t%0,%1" [(set_attr "move_type" "fmove") + (set_attr "type" "fmove") (set_attr "mode" "DF")]) (define_insn "movdfsisi3_rv32" @@ -2247,6 +2249,7 @@ (define_insn "movdfsisi3_rv32" "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA" "fmvp.d.x\t%0,%2,%1" [(set_attr "move_type" "fmove") + (set_attr "type" "fmove") (set_attr "mode" "DF")]) (define_split From patchwork Wed Sep 6 17:50:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edwin Lu X-Patchwork-Id: 1830505 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=VGnwAQJd; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Rgqgl5VqHz1yh5 for ; Thu, 7 Sep 2023 03:51:47 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D0B5E385703A for ; Wed, 6 Sep 2023 17:51:45 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by sourceware.org (Postfix) with ESMTPS id 182573857725 for ; Wed, 6 Sep 2023 17:50:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 182573857725 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-68e369ba5f8so90222b3a.2 for ; Wed, 06 Sep 2023 10:50:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1694022642; x=1694627442; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KZADUiyHRXPLif/+6c3X45kWcmfASOAs0U5BsxEAfYM=; b=VGnwAQJdddheYD2mCv4KplFm3xw2pqkHq+uE0HzZxC0MZ4k0S0nlpHiBtxDQUEFddp fk3US6uUFGku7WukowBVcuZ5v/LDYqUYOVxQiU8D86lhyqvs1YoPAQjfV+PWFs1FRtlU OS4XtpyuNu5HhGbzDWhAU21P+15yprtsi8VmOzuVz7ZIm+VpEo8dN9ir85ko1BFgwNrj 6gQMExspypw5rj89omiNNFy8c5Wm+hxpwVgWKhgJJx+Yh/pFvvomhFgwt11IB0tLY8om iTz4CSsFeyasDsHsACpkbdA85hGGS/8Ca4/kPdG4nkxL0EMiObrNTyTt7xcodgizwYPG 3YEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1694022642; x=1694627442; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KZADUiyHRXPLif/+6c3X45kWcmfASOAs0U5BsxEAfYM=; b=cr+RmIBrGazjd/2zbznpM98RsIE9Ulw8VgJGxRW2jL1DMTYTrWNVQ/O15hH4IiUaML 4VPL6y4R+LgG64IxpYw6GEQyceCqaMGwnbzylRtwKs2UAxHUnBI3BfViq5ASNhP31jyy cJs2X4EZ8G9OJgTGvp8jpAmSfIr0moCtVB+L2BAGUuYg+Hoh+ogEuREc2dLlOLEL5ao8 ywJ2B2+pRRk/jMFsP+D1QBiu8OxQqrXxpvAbOTi+6ZRcTRzvK5jefwAwOCz/UQexaBD6 dK6ioAXRkgf/+RwAMkfyghRj+nQZMgVn3KWqH4sZXHt31fREZYB3Gp6gbdc9Cdju4VAm BFng== X-Gm-Message-State: AOJu0YxPJTrXKh/M9PjZX5qBNsvxAbH6dyFZbYIaDwY2PoJq6h7JFdJB z8pHdDkMsXKn9Vnc7Vrl/EHiwmZwRjzaMpwYy58= X-Google-Smtp-Source: AGHT+IFQslFUirZxDwVWb0s8RPGeKWBYZ5wHRw1iNfzdlTdTWMf+6Ty9+0ZuDLG7m3es0aVZwxGFkA== X-Received: by 2002:a05:6a20:1057:b0:14d:e780:4007 with SMTP id gt23-20020a056a20105700b0014de7804007mr14118880pzc.42.1694022642099; Wed, 06 Sep 2023 10:50:42 -0700 (PDT) Received: from ewlu.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id f8-20020aa782c8000000b00687a4b70d1esm11017428pfn.218.2023.09.06.10.50.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 10:50:41 -0700 (PDT) From: Edwin Lu To: gcc-patches@gcc.gnu.org Subject: [PATCH 5/5] RISC-V: Remove Assert Protecting Types Date: Wed, 6 Sep 2023 10:50:23 -0700 Message-ID: <20230906175025.935887-6-ewlu@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230906175025.935887-1-ewlu@rivosinc.com> References: <20230906175025.935887-1-ewlu@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gnu-toolchain@rivosinc.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch turns on the assert which ensures every instruction has type that is not TYPE_UNKNOWN. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert Signed-off-by: Edwin Lu --- gcc/config/riscv/riscv.cc | 2 -- 1 file changed, 2 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index ef63079de8e..f0576351cda 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7330,11 +7330,9 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, int more) if (get_attr_type (insn) == TYPE_GHOST) return 0; -#if 0 /* If we ever encounter an insn with an unknown type, trip an assert so we can find and fix this problem. */ gcc_assert (get_attr_type (insn) != TYPE_UNKNOWN); -#endif return more - 1; }