From patchwork Fri Sep 1 05:45:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lehua Ding X-Patchwork-Id: 1828640 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RcRq50hx4z1ygY for ; Fri, 1 Sep 2023 15:46:24 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BA17438582A9 for ; Fri, 1 Sep 2023 05:46:22 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by sourceware.org (Postfix) with ESMTPS id 0DEA0385842E for ; Fri, 1 Sep 2023 05:46:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0DEA0385842E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1693547155t5hd4yu6 Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 01 Sep 2023 13:45:54 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: KzokuMsy9J0r+qmuyuB1uEbwwMpie+L0PJ0gxPcgjE22R2bJQXVzaPq/xAPCy 3xQD2p+zKChj9Abh9pOaxLLB4HrEjk6ewmgUYws3x24aiRaXFCpmlxpPBGJiW/N0B4U1UyZ 6cYmPEyzrkwGl1wdsDb5gSYDiJv6MvJQsuV5X3cUKOWllz1Hq5cZIqoJ++khsycZrurq1Sg Z5kWgmtoyFnSarBON8GGlCTq96FJ+6WCBOFK68vEKTRWzaEdaWB8oL/tPCmvD8RgPZ/HkMz 3QsgvXLuYgOGFwOckPTta3jbtJh+qSW3qNAZ3Zdmymrew77P4aHgjEQPXcHff/7ZJrH5hlx iiYjvjoTWDoZboRup+ZpO61ilZICSOqK6aRvXqS3/VakxougU4hfmNo+Z/gUDvM6Lq7nyBp 4WO6KXiZX8o= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 8267531306622387483 From: Lehua Ding To: gcc-patches@gcc.gnu.org, rdapp.gcc@gmail.com Subject: [PATCH 1/4] RISC-V: Adjust expand_cond_len_{unary,binop,op} api Date: Fri, 1 Sep 2023 13:45:48 +0800 Message-Id: <20230901054551.1953049-2-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20230901054551.1953049-1-lehua.ding@rivai.ai> References: <20230901054551.1953049-1-lehua.ding@rivai.ai> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, juzhe.zhong@rivai.ai Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch change expand_cond_len_{unary,binop}'s argument `rtx_code code` to `unsigned icode` and use the icode directly to determine whether the rounding_mode operand is required. gcc/ChangeLog: * config/riscv/autovec.md: Adjust. * config/riscv/riscv-protos.h (expand_cond_len_unop): Ditto. (expand_cond_len_binop): Ditto. * config/riscv/riscv-v.cc (needs_fp_rounding): Ditto. (expand_cond_len_op): Ditto. (expand_cond_len_unop): Ditto. (expand_cond_len_binop): Ditto. (expand_cond_len_ternop): Ditto. --- gcc/config/riscv/autovec.md | 18 +++++++++++------ gcc/config/riscv/riscv-protos.h | 4 ++-- gcc/config/riscv/riscv-v.cc | 34 +++++++++++++++++++-------------- 3 files changed, 34 insertions(+), 22 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index ebe1b10aa12..006e174ebd5 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1551,7 +1551,8 @@ (match_operand 5 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_unop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_unop (icode, operands); DONE; }) @@ -1588,7 +1589,8 @@ (match_operand 5 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_unop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_unop (icode, operands); DONE; }) @@ -1627,7 +1629,8 @@ (match_operand 6 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_binop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_binop (icode, operands); DONE; }) @@ -1667,7 +1670,8 @@ (match_operand 6 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_binop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_binop (icode, operands); DONE; }) @@ -1707,7 +1711,8 @@ (match_operand 6 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_binop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_binop (icode, operands); DONE; }) @@ -1745,7 +1750,8 @@ (match_operand 6 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_binop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_binop (icode, operands); DONE; }) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index e145ee6c69b..dd7aa360ec5 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -426,8 +426,8 @@ bool neg_simm5_p (rtx); bool has_vi_variant_p (rtx_code, rtx); void expand_vec_cmp (rtx, rtx_code, rtx, rtx); bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool); -void expand_cond_len_unop (rtx_code, rtx *); -void expand_cond_len_binop (rtx_code, rtx *); +void expand_cond_len_unop (unsigned, rtx *); +void expand_cond_len_binop (unsigned, rtx *); void expand_reduction (rtx_code, rtx *, rtx, reduction_type = reduction_type::UNORDERED); #endif diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 6228ff3d92e..89ac4743f40 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -245,6 +245,12 @@ public: always Pmode. */ if (mode == VOIDmode) mode = Pmode; + else + /* Early assertion ensures same mode since maybe_legitimize_operand + will check this. */ + gcc_assert (GET_MODE (ops[opno]) == VOIDmode + || GET_MODE (ops[opno]) == mode); + add_input_operand (ops[opno], mode); } @@ -291,6 +297,7 @@ public: if (m_insn_flags & FRM_DYN_P) add_rounding_mode_operand (FRM_DYN); + gcc_assert (insn_data[(int) icode].n_operands == m_opno); expand (icode, any_mem_p); } @@ -2951,17 +2958,20 @@ expand_load_store (rtx *ops, bool is_load) /* Return true if the operation is the floating-point operation need FRM. */ static bool -needs_fp_rounding (rtx_code code, machine_mode mode) +needs_fp_rounding (unsigned icode, machine_mode mode) { if (!FLOAT_MODE_P (mode)) return false; - return code != SMIN && code != SMAX && code != NEG && code != ABS; + + return icode != maybe_code_for_pred (SMIN, mode) + && icode != maybe_code_for_pred (SMAX, mode) + && icode != maybe_code_for_pred (NEG, mode) + && icode != maybe_code_for_pred (ABS, mode); } /* Subroutine to expand COND_LEN_* patterns. */ static void -expand_cond_len_op (rtx_code code, unsigned icode, insn_flags op_type, rtx *ops, - rtx len) +expand_cond_len_op (unsigned icode, insn_flags op_type, rtx *ops, rtx len) { rtx dest = ops[0]; rtx mask = ops[1]; @@ -2980,7 +2990,7 @@ expand_cond_len_op (rtx_code code, unsigned icode, insn_flags op_type, rtx *ops, else insn_flags |= TU_POLICY_P | MU_POLICY_P; - if (needs_fp_rounding (code, mode)) + if (needs_fp_rounding (icode, mode)) insn_flags |= FRM_DYN_P; if (is_vlmax_len) @@ -2991,7 +3001,7 @@ expand_cond_len_op (rtx_code code, unsigned icode, insn_flags op_type, rtx *ops, /* Expand unary ops COND_LEN_*. */ void -expand_cond_len_unop (rtx_code code, rtx *ops) +expand_cond_len_unop (unsigned icode, rtx *ops) { rtx dest = ops[0]; rtx mask = ops[1]; @@ -2999,15 +3009,13 @@ expand_cond_len_unop (rtx_code code, rtx *ops) rtx merge = ops[3]; rtx len = ops[4]; - machine_mode mode = GET_MODE (dest); - insn_code icode = code_for_pred (code, mode); rtx cond_ops[] = {dest, mask, merge, src}; - expand_cond_len_op (code, icode, UNARY_OP_P, cond_ops, len); + expand_cond_len_op (icode, UNARY_OP_P, cond_ops, len); } /* Expand binary ops COND_LEN_*. */ void -expand_cond_len_binop (rtx_code code, rtx *ops) +expand_cond_len_binop (unsigned icode, rtx *ops) { rtx dest = ops[0]; rtx mask = ops[1]; @@ -3016,10 +3024,8 @@ expand_cond_len_binop (rtx_code code, rtx *ops) rtx merge = ops[4]; rtx len = ops[5]; - machine_mode mode = GET_MODE (dest); - insn_code icode = code_for_pred (code, mode); rtx cond_ops[] = {dest, mask, merge, src1, src2}; - expand_cond_len_op (code, icode, BINARY_OP_P, cond_ops, len); + expand_cond_len_op (icode, BINARY_OP_P, cond_ops, len); } /* Prepare insn_code for gather_load/scatter_store according to @@ -3191,7 +3197,7 @@ expand_cond_len_ternop (unsigned icode, rtx *ops) rtx len = ops[6]; rtx cond_ops[] = {dest, mask, src1, src2, src3, merge}; - expand_cond_len_op (UNSPEC, icode, TERNARY_OP_P, cond_ops, len); + expand_cond_len_op (icode, TERNARY_OP_P, cond_ops, len); } /* Expand reduction operations. */ From patchwork Fri Sep 1 05:45:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lehua Ding X-Patchwork-Id: 1828641 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; 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dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1693547158trhf8bun Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 01 Sep 2023 13:45:57 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: hJ5650VbgwAzlOTkkeLOCypHzw/nt18Tz3V/TjSIT+zbvVXjFC66jwmqd0TGf Rk+aro4cnF0UFTqWHhEMQtaIaQ4V3FikSDUS0+48KopIJ3u5IC20/hUx+JyFd0YEz4HjacW XDdTu0DEHlYUyHOKKZbJw5ExmQjStvF+zpnjgN0+lDejic2aZnQokLvpMEXSog5vfxzVe9a PfSd3kY5rhRrP+HWwhfo1ahwWfDavmlxWnntDgMlnL+NFGhcwogPlRRoauvUewVFPHHo+0d /rIdroXupKbLzSWHSAKmkeIiiVXB0N/GPSqogr428WfOXbinZslDBXS6nCyvksNG4LqRNdN f3EXT2c0Aq6JEu1D8ZH/mCDxiIVlOt0bo8lcn4wem1OhVKIQJe6rw1me39e1k6dBfOZZC1s LcB0LrjcRc4= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 8901118218865622983 From: Lehua Ding To: gcc-patches@gcc.gnu.org, rdapp.gcc@gmail.com Subject: [PATCH 2/4] RISC-V: Add conditional autovec convert(INT<->INT) patterns Date: Fri, 1 Sep 2023 13:45:49 +0800 Message-Id: <20230901054551.1953049-3-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20230901054551.1953049-1-lehua.ding@rivai.ai> References: <20230901054551.1953049-1-lehua.ding@rivai.ai> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, juzhe.zhong@rivai.ai Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" gcc/ChangeLog: * config/riscv/autovec-opt.md (*cond_): New combine pattern. (*cond_): Ditto. (*cond_): Ditto. (*cond_trunc): Ditto. * config/riscv/autovec.md (2): Adjust. (2): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/narrow-3.c: Adjust. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c: New test. --- gcc/config/riscv/autovec-opt.md | 77 +++++++++++++++++++ gcc/config/riscv/autovec.md | 37 ++++----- .../riscv/rvv/autovec/binop/narrow-3.c | 2 +- .../rvv/autovec/cond/cond_convert_int2int-1.h | 47 +++++++++++ .../rvv/autovec/cond/cond_convert_int2int-2.h | 46 +++++++++++ .../cond/cond_convert_int2int-rv32-1.c | 17 ++++ .../cond/cond_convert_int2int-rv32-2.c | 16 ++++ .../cond/cond_convert_int2int-rv64-1.c | 16 ++++ .../cond/cond_convert_int2int-rv64-2.c | 16 ++++ .../autovec/cond/cond_convert_int2int_run-1.c | 31 ++++++++ .../autovec/cond/cond_convert_int2int_run-2.c | 30 ++++++++ 11 files changed, 311 insertions(+), 24 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 92590776c3e..6796239d82d 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -747,3 +747,80 @@ riscv_vector::BINARY_OP, operands); DONE; }) + +;; Combine sign_extend/zero_extend(vf2) and vcond_mask +(define_insn_and_split "*cond_" + [(set (match_operand:VWEXTI 0 "register_operand") + (if_then_else:VWEXTI + (match_operand: 1 "register_operand") + (any_extend:VWEXTI (match_operand: 2 "register_operand")) + (match_operand:VWEXTI 3 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_vf2 (, mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; + riscv_vector::expand_cond_len_unop (icode, ops); + DONE; +}) + +;; Combine sign_extend/zero_extend(vf4) and vcond_mask +(define_insn_and_split "*cond_" + [(set (match_operand:VQEXTI 0 "register_operand") + (if_then_else:VQEXTI + (match_operand: 1 "register_operand") + (any_extend:VQEXTI (match_operand: 2 "register_operand")) + (match_operand:VQEXTI 3 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_vf4 (, mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; + riscv_vector::expand_cond_len_unop (icode, ops); + DONE; +}) + +;; Combine sign_extend/zero_extend(vf8) and vcond_mask +(define_insn_and_split "*cond_" + [(set (match_operand:VOEXTI 0 "register_operand") + (if_then_else:VOEXTI + (match_operand: 1 "register_operand") + (any_extend:VOEXTI (match_operand: 2 "register_operand")) + (match_operand:VOEXTI 3 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_vf8 (, mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; + riscv_vector::expand_cond_len_unop (icode, ops); + DONE; +}) + +;; Combine trunc(vf2) + vcond_mask +(define_insn_and_split "*cond_trunc" + [(set (match_operand: 0 "register_operand") + (if_then_else: + (match_operand: 1 "register_operand") + (truncate: + (match_operand:VWEXTI 2 "register_operand")) + (match_operand: 3 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_trunc (mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; + riscv_vector::expand_cond_len_unop (icode, ops); + DONE; +}) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 006e174ebd5..4859805b8f7 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -633,22 +633,28 @@ [(set_attr "type" "vext") (set_attr "mode" "")]) -(define_expand "2" +(define_insn_and_split "2" [(set (match_operand:VQEXTI 0 "register_operand") (any_extend:VQEXTI (match_operand: 1 "register_operand")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] { insn_code icode = code_for_pred_vf4 (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); DONE; }) -(define_expand "2" +(define_insn_and_split "2" [(set (match_operand:VOEXTI 0 "register_operand") (any_extend:VOEXTI (match_operand: 1 "register_operand")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] { insn_code icode = code_for_pred_vf8 (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); @@ -687,13 +693,8 @@ "TARGET_VECTOR" { rtx half = gen_reg_rtx (mode); - rtx opshalf[] = {half, operands[1]}; - insn_code icode = code_for_pred_trunc (mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, opshalf); - - rtx ops[] = {operands[0], half}; - icode = code_for_pred_trunc (mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ops); + emit_insn (gen_trunc2 (half, operands[1])); + emit_insn (gen_trunc2 (operands[0], half)); DONE; }) @@ -707,19 +708,9 @@ (match_operand:VOEXTI 1 "register_operand")))] "TARGET_VECTOR" { - rtx half = gen_reg_rtx (mode); - rtx opshalf[] = {half, operands[1]}; - insn_code icode = code_for_pred_trunc (mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, opshalf); - rtx quarter = gen_reg_rtx (mode); - rtx opsquarter[] = {quarter, half}; - icode = code_for_pred_trunc (mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, opsquarter); - - rtx ops[] = {operands[0], quarter}; - icode = code_for_pred_trunc (mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ops); + emit_insn (gen_trunc2 (quarter, operands[1])); + emit_insn (gen_trunc2 (operands[0], quarter)); DONE; }) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c index 3b288466394..315d2de0a8b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c @@ -27,5 +27,5 @@ TEST_ALL () -/* { dg-final { scan-assembler-times {\tvnsra\.wx} 4 } } */ +/* { dg-final { scan-assembler-times {\tvnsra\.wx} 8 } } */ /* { dg-final { scan-assembler-times {\tvnsrl\.wx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h new file mode 100644 index 00000000000..c8ef6df399d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h @@ -0,0 +1,47 @@ +#include + +#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \ + void __attribute__ ((noipa)) \ + test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \ + OLD_TYPE *__restrict a, \ + NEW_TYPE *__restrict b, \ + OLD_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + r[i] = pred[i] ? (NEW_TYPE) a[i] : b[i]; \ + } \ + } + +/* INT -> wider-INT */ +#define TEST_ALL_X2X_WIDER(T) \ + T (uint8_t, uint16_t) \ + T (uint8_t, uint32_t) \ + T (uint8_t, uint64_t) \ + T (int8_t, int16_t) \ + T (int8_t, int32_t) \ + T (int8_t, int64_t) \ + T (uint16_t, uint32_t) \ + T (uint16_t, uint64_t) \ + T (int16_t, int32_t) \ + T (int16_t, int64_t) \ + T (uint32_t, uint64_t) \ + T (int32_t, int64_t) + +/* INT -> narrower-INT */ +#define TEST_ALL_X2X_NARROWER(T) \ + T (uint16_t, uint8_t) \ + T (int16_t, int8_t) \ + T (uint32_t, uint8_t) \ + T (int32_t, int8_t) \ + T (uint64_t, uint8_t) \ + T (int64_t, int8_t) \ + T (uint32_t, uint16_t) \ + T (int32_t, int16_t) \ + T (uint64_t, uint16_t) \ + T (int64_t, int16_t) \ + T (uint64_t, uint32_t) \ + T (int64_t, int32_t) + +TEST_ALL_X2X_WIDER (DEF_LOOP) +TEST_ALL_X2X_NARROWER (DEF_LOOP) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h new file mode 100644 index 00000000000..f53c1b3fde9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h @@ -0,0 +1,46 @@ +#include + +#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \ + void __attribute__ ((noipa)) \ + test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \ + OLD_TYPE *__restrict a, NEW_TYPE b, \ + OLD_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + r[i] = pred[i] ? (NEW_TYPE) a[i] : b; \ + } \ + } + +/* INT -> wider-INT */ +#define TEST_ALL_X2X_WIDER(T) \ + T (uint8_t, uint16_t) \ + T (uint8_t, uint32_t) \ + T (uint8_t, uint64_t) \ + T (int8_t, int16_t) \ + T (int8_t, int32_t) \ + T (int8_t, int64_t) \ + T (uint16_t, uint32_t) \ + T (uint16_t, uint64_t) \ + T (int16_t, int32_t) \ + T (int16_t, int64_t) \ + T (uint32_t, uint64_t) \ + T (int32_t, int64_t) + +/* INT -> narrower-INT */ +#define TEST_ALL_X2X_NARROWER(T) \ + T (uint16_t, uint8_t) \ + T (int16_t, int8_t) \ + T (uint32_t, uint8_t) \ + T (int32_t, int8_t) \ + T (uint64_t, uint8_t) \ + T (int64_t, int8_t) \ + T (uint32_t, uint16_t) \ + T (int32_t, int16_t) \ + T (uint64_t, uint16_t) \ + T (int64_t, int16_t) \ + T (uint64_t, uint32_t) \ + T (int64_t, int32_t) + +TEST_ALL_X2X_WIDER (DEF_LOOP) +TEST_ALL_X2X_NARROWER (DEF_LOOP) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c new file mode 100644 index 00000000000..8c07e427560 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_int2int-1.h" + +/* { dg-final { scan-assembler-times {\tvzext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ + +/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */ +/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */ + +/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c new file mode 100644 index 00000000000..74490cdc055 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_int2int-2.h" + +/* { dg-final { scan-assembler-times {\tvzext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ + +/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */ +/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */ + +/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c new file mode 100644 index 00000000000..00357966ba6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_int2int-1.h" + +/* { dg-final { scan-assembler-times {\tvzext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ + +/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */ +/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */ + +/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c new file mode 100644 index 00000000000..3c4ad9c4f66 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_int2int-2.h" + +/* { dg-final { scan-assembler-times {\tvzext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ + +/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */ +/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */ + +/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c new file mode 100644 index 00000000000..04f24168a38 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_int2int-1.h" + +#define N 99 + +#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \ + { \ + NEW_TYPE r[N], b[N]; \ + OLD_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + b[i] = (i % 9) * (i % 7 + 1); \ + pred[i] = (i % 7 < 4); \ + asm volatile("" ::: "memory"); \ + } \ + test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b[i])) \ + __builtin_abort (); \ + } + +int +main () +{ + TEST_ALL_X2X_WIDER (TEST_LOOP) + TEST_ALL_X2X_NARROWER (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c new file mode 100644 index 00000000000..7a6897bf029 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_int2int-2.h" + +#define N 99 + +#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \ + { \ + NEW_TYPE r[N], b = 189; \ + OLD_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + pred[i] = (i % 7 < 4); \ + asm volatile("" ::: "memory"); \ + } \ + test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b)) \ + __builtin_abort (); \ + } + +int +main () +{ + TEST_ALL_X2X_WIDER (TEST_LOOP) + TEST_ALL_X2X_NARROWER (TEST_LOOP) + return 0; +} From patchwork Fri Sep 1 05:45:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lehua Ding X-Patchwork-Id: 1828642 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RcRqj49Tyz1yfm for ; Fri, 1 Sep 2023 15:46:57 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DFA4F388202B for ; Fri, 1 Sep 2023 05:46:50 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id 68EC33858438 for ; Fri, 1 Sep 2023 05:46:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 68EC33858438 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1693547161t2emc6kc Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 01 Sep 2023 13:46:01 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: 3wTaVWsEHF+Iss2I8/q6BCSC36u4YriowLKAjYWbHpxuJpi5/PxSrsnIqyZ8R r+68sq14jbxxf1GQ93Cb7f/Ws+ayqvAc/zVY/lX4F5bo+AjeAdzFdUetPadA9XsDCnxqH0X Ifh5foTMJAAelMgPpMaxiS2FaNT91Qq2kSlXZzNP1ghrCUJ2ffzOmWHdTV2+ZJOWxJChi6p o+MLHCNDjIMFArXdgEdH5SMcxNqow00DTgJOjFlFdgZ8cOSqYXQSElb30dVR94+tUQxjDNN 8Kai1XR0HHmdPX0caaRn1n15euilZEM82V6C8svEs88F5ePag8kBpRFxhdQkI3AES041hYL 9mDVf55qRc0HdAoSrVwlDIC6R9giDyfYwP3VkolJK5EDtVXMVLPXo960bDvPjEMIVFB8LLT r6zfOcH71RQ= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 15014173632097126983 From: Lehua Ding To: gcc-patches@gcc.gnu.org, rdapp.gcc@gmail.com Subject: [PATCH 3/4] RISC-V: Add conditional autovec convert(FP<->FP) patterns Date: Fri, 1 Sep 2023 13:45:50 +0800 Message-Id: <20230901054551.1953049-4-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20230901054551.1953049-1-lehua.ding@rivai.ai> References: <20230901054551.1953049-1-lehua.ding@rivai.ai> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, juzhe.zhong@rivai.ai Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" gcc/ChangeLog: * config/riscv/autovec-opt.md (*cond_extend): New combine pattern. (*cond_trunc): Ditto. * config/riscv/autovec.md: Adjust. * config/riscv/riscv-v.cc (needs_fp_rounding): Add FP extend. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c: New test. --- gcc/config/riscv/autovec-opt.md | 39 +++++++++++++++++++ gcc/config/riscv/autovec.md | 13 ++----- gcc/config/riscv/riscv-v.cc | 4 +- .../autovec/cond/cond_convert_float2float-1.h | 29 ++++++++++++++ .../autovec/cond/cond_convert_float2float-2.h | 28 +++++++++++++ .../cond/cond_convert_float2float-rv32-1.c | 9 +++++ .../cond/cond_convert_float2float-rv32-2.c | 9 +++++ .../cond/cond_convert_float2float-rv64-1.c | 9 +++++ .../cond/cond_convert_float2float-rv64-2.c | 9 +++++ .../cond/cond_convert_float2float_run-1.c | 31 +++++++++++++++ .../cond/cond_convert_float2float_run-2.c | 30 ++++++++++++++ 11 files changed, 199 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 6796239d82d..ef468bb9df7 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -824,3 +824,42 @@ riscv_vector::expand_cond_len_unop (icode, ops); DONE; }) + +;; Combine FP sign_extend/zero_extend(vf2) and vcond_mask +(define_insn_and_split "*cond_extend" + [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand") + (if_then_else:VWEXTF_ZVFHMIN + (match_operand: 1 "register_operand") + (float_extend:VWEXTF_ZVFHMIN (match_operand: 2 "register_operand")) + (match_operand:VWEXTF_ZVFHMIN 3 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_extend (mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; + riscv_vector::expand_cond_len_unop (icode, ops); + DONE; +}) + +;; Combine FP trunc(vf2) + vcond_mask +(define_insn_and_split "*cond_trunc" + [(set (match_operand: 0 "register_operand") + (if_then_else: + (match_operand: 1 "register_operand") + (float_truncate: + (match_operand:VWEXTF_ZVFHMIN 2 "register_operand")) + (match_operand: 3 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_trunc (mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; + riscv_vector::expand_cond_len_unop (icode, ops); + DONE; +}) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 4859805b8f7..a4ac688e373 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -742,13 +742,8 @@ "TARGET_VECTOR && (TARGET_ZVFHMIN || TARGET_ZVFH)" { rtx dblw = gen_reg_rtx (mode); - insn_code icode = code_for_pred_extend (mode); - rtx ops1[] = {dblw, operands[1]}; - riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ops1); - - icode = code_for_pred_extend (mode); - rtx ops2[] = {operands[0], dblw}; - riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ops2); + emit_insn (gen_extend2 (dblw, operands[1])); + emit_insn (gen_extend2 (operands[0], dblw)); DONE; }) @@ -791,9 +786,7 @@ insn_code icode = code_for_pred_rod_trunc (mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, opshalf); - rtx ops[] = {operands[0], half}; - icode = code_for_pred_trunc (mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, ops); + emit_insn (gen_trunc2 (operands[0], half)); DONE; }) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 89ac4743f40..0f414663620 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -2966,7 +2966,9 @@ needs_fp_rounding (unsigned icode, machine_mode mode) return icode != maybe_code_for_pred (SMIN, mode) && icode != maybe_code_for_pred (SMAX, mode) && icode != maybe_code_for_pred (NEG, mode) - && icode != maybe_code_for_pred (ABS, mode); + && icode != maybe_code_for_pred (ABS, mode) + /* narrower-FP -> FP */ + && icode != maybe_code_for_pred_extend (mode); } /* Subroutine to expand COND_LEN_* patterns. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h new file mode 100644 index 00000000000..4742d926af6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h @@ -0,0 +1,29 @@ +#include + +#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \ + void __attribute__ ((noipa)) \ + test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \ + OLD_TYPE *__restrict a, \ + NEW_TYPE *__restrict b, \ + OLD_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + r[i] = pred[i] ? (NEW_TYPE) a[i] : b[i]; \ + } \ + } + +/* FP -> wider-FP */ +#define TEST_ALL_F2F_WIDER(T) \ + T (_Float16, float) \ + T (_Float16, double) \ + T (float, double) + +/* FP -> narrower-FP */ +#define TEST_ALL_F2F_NARROWER(T) \ + T (float, _Float16) \ + T (double, _Float16) \ + T (double, float) + +TEST_ALL_F2F_WIDER (DEF_LOOP) +TEST_ALL_F2F_NARROWER (DEF_LOOP) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h new file mode 100644 index 00000000000..b084eaae19d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h @@ -0,0 +1,28 @@ +#include + +#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \ + void __attribute__ ((noipa)) \ + test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \ + OLD_TYPE *__restrict a, NEW_TYPE b, \ + OLD_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + r[i] = pred[i] ? (NEW_TYPE) a[i] : b; \ + } \ + } + +/* FP -> wider-FP */ +#define TEST_ALL_F2F_WIDER(T) \ + T (_Float16, float) \ + T (_Float16, double) \ + T (float, double) + +/* FP -> narrower-FP */ +#define TEST_ALL_F2F_NARROWER(T) \ + T (float, _Float16) \ + T (double, _Float16) \ + T (double, float) + +TEST_ALL_F2F_WIDER (DEF_LOOP) +TEST_ALL_F2F_NARROWER (DEF_LOOP) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c new file mode 100644 index 00000000000..e0d9eaa4173 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2float-1.h" + +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c new file mode 100644 index 00000000000..8d963b0397b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2float-2.h" + +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c new file mode 100644 index 00000000000..9841fdd7f79 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2float-1.h" + +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c new file mode 100644 index 00000000000..03ee19fa9e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2float-2.h" + +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c new file mode 100644 index 00000000000..407bbc27c2f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2float-1.h" + +#define N 99 + +#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \ + { \ + NEW_TYPE r[N], b[N]; \ + OLD_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + b[i] = (i % 9) * (i % 7 + 1); \ + pred[i] = (i % 7 < 4); \ + asm volatile("" ::: "memory"); \ + } \ + test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b[i])) \ + __builtin_abort (); \ + } + +int +main () +{ + TEST_ALL_F2F_WIDER (TEST_LOOP) + TEST_ALL_F2F_NARROWER (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c new file mode 100644 index 00000000000..05d217da625 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2float-2.h" + +#define N 99 + +#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \ + { \ + NEW_TYPE r[N], b = 18.02; \ + OLD_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + pred[i] = (i % 7 < 4); \ + asm volatile("" ::: "memory"); \ + } \ + test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b)) \ + __builtin_abort (); \ + } + +int +main () +{ + TEST_ALL_F2F_WIDER (TEST_LOOP) + TEST_ALL_F2F_NARROWER (TEST_LOOP) + return 0; +} From patchwork Fri Sep 1 05:45:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lehua Ding X-Patchwork-Id: 1828643 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RcRqm342tz1yfm for ; Fri, 1 Sep 2023 15:47:00 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 189A6385483D for ; Fri, 1 Sep 2023 05:46:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by sourceware.org (Postfix) with ESMTPS id 5D1A7385843E for ; Fri, 1 Sep 2023 05:46:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5D1A7385843E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1693547164thxs3nam Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 01 Sep 2023 13:46:04 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: Oyw7ngegtIrjB1iCNtT60Jedpj7MNK175YzyURZPZvb/P+UYMU7ss6P+MhhtY YVJNrgbAeWcPLVcMMCDYoK3QJKQ/vbKsBucI10jywSxTe3Uf1YXZV5MpdyEahqsERmmtG4u 0OjJ4I4qBOoliIpOHkoxj7c620F2ipiPSbNB+NPkbWiFBQ4pzlJH8QVLbS7V4jPpol1hALU +S+2nGxSn8SEeEKZramFdAg9HwwF7glNmM9CNBQ6stUZ1cOmnU4xNbk0E7Cxr+wZD1lcJ/e vKa30tPkSrhHTanRlfxY/TUm3TqD/XpqUYuAIp4cbZZMAPQTSYh6P12xJdLJrj5mJqDzawD ux6/1cXD0EmI/EXIyL+6V/7a2LUPvLL+rgXBFnIBVvzf8RycGMeZbiAVfZasMgUqPRwXgMJ X-QQ-GoodBg: 2 X-BIZMAIL-ID: 11705499047295237168 From: Lehua Ding To: gcc-patches@gcc.gnu.org, rdapp.gcc@gmail.com Subject: [PATCH 4/4] RISC-V: Add conditional autovec convert(INT<->FP) patterns Date: Fri, 1 Sep 2023 13:45:51 +0800 Message-Id: <20230901054551.1953049-5-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20230901054551.1953049-1-lehua.ding@rivai.ai> References: <20230901054551.1953049-1-lehua.ding@rivai.ai> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, juzhe.zhong@rivai.ai Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" gcc/ChangeLog: * config/riscv/autovec-opt.md (*cond_): New combine pattern. (*cond_): Ditto. (*cond_): Ditto. (*cond_): Ditto. (*cond_): Ditto. (*cond_2): Ditto. * config/riscv/autovec.md (2): Adjust. (2): Adjust. (2): Adjust. (2): Adjust. (2): Adjust. (2): Adjust. * config/riscv/riscv-v.cc (needs_fp_rounding): Add INT->FP extend. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c: New test. --- gcc/config/riscv/autovec-opt.md | 120 ++++++++++++++++++ gcc/config/riscv/autovec.md | 42 ++++-- gcc/config/riscv/riscv-v.cc | 5 +- .../autovec/cond/cond_convert_float2int-1.h | 51 ++++++++ .../autovec/cond/cond_convert_float2int-2.h | 50 ++++++++ .../cond/cond_convert_float2int-rv32-1.c | 15 +++ .../cond/cond_convert_float2int-rv32-2.c | 15 +++ .../cond/cond_convert_float2int-rv64-1.c | 15 +++ .../cond/cond_convert_float2int-rv64-2.c | 15 +++ .../cond/cond_convert_float2int_run-1.c | 32 +++++ .../cond/cond_convert_float2int_run-2.c | 31 +++++ .../autovec/cond/cond_convert_int2float-1.h | 45 +++++++ .../autovec/cond/cond_convert_int2float-2.h | 44 +++++++ .../cond/cond_convert_int2float-rv32-1.c | 13 ++ .../cond/cond_convert_int2float-rv32-2.c | 13 ++ .../cond/cond_convert_int2float-rv64-1.c | 13 ++ .../cond/cond_convert_int2float-rv64-2.c | 13 ++ .../cond/cond_convert_int2float_run-1.c | 32 +++++ .../cond/cond_convert_int2float_run-2.c | 31 +++++ 19 files changed, 582 insertions(+), 13 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index ef468bb9df7..1ca5ce97193 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -863,3 +863,123 @@ riscv_vector::expand_cond_len_unop (icode, ops); DONE; }) + +;; Combine convert(FP->INT) + vcond_mask +(define_insn_and_split "*cond_" + [(set (match_operand: 0 "register_operand") + (if_then_else: + (match_operand: 1 "register_operand") + (any_fix: + (match_operand:VF 2 "register_operand")) + (match_operand: 3 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred (, mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; + riscv_vector::expand_cond_len_unop (icode, ops); + DONE; +}) + +;; Combine convert(INT->FP) + vcond_mask +(define_insn_and_split "*cond_" + [(set (match_operand:VF 0 "register_operand") + (if_then_else:VF + (match_operand: 1 "register_operand") + (any_float:VF + (match_operand: 2 "register_operand")) + (match_operand:VF 3 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred (, mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; + riscv_vector::expand_cond_len_unop (icode, ops); + DONE; +}) + +;; Combine convert(FP->2xINT) + vcond_mask +(define_insn_and_split "*cond_" + [(set (match_operand:VWCONVERTI 0 "register_operand") + (if_then_else:VWCONVERTI + (match_operand: 1 "register_operand") + (any_fix:VWCONVERTI + (match_operand: 2 "register_operand")) + (match_operand:VWCONVERTI 3 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_widen (, mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; + riscv_vector::expand_cond_len_unop (icode, ops); + DONE; +}) + +;; Combine convert(INT->2xFP) + vcond_mask +(define_insn_and_split "*cond_" + [(set (match_operand:VF 0 "register_operand") + (if_then_else:VF + (match_operand: 1 "register_operand") + (any_float:VF + (match_operand: 2 "register_operand")) + (match_operand:VF 3 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_widen (, mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; + riscv_vector::expand_cond_len_unop (icode, ops); + DONE; +}) + +;; Combine convert(2xFP->INT) + vcond_mask +(define_insn_and_split "*cond_" + [(set (match_operand: 0 "register_operand") + (if_then_else: + (match_operand: 1 "register_operand") + (any_fix: + (match_operand:VF 2 "register_operand")) + (match_operand: 3 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_narrow (, mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; + riscv_vector::expand_cond_len_unop (icode, ops); + DONE; +}) + +;; Combine convert(2xINT->FP) + vcond_mask +(define_insn_and_split "*cond_2" + [(set (match_operand: 0 "register_operand") + (if_then_else: + (match_operand: 1 "register_operand") + (any_float: + (match_operand:VWCONVERTI 2 "register_operand")) + (match_operand: 3 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_narrow (, mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; + riscv_vector::expand_cond_len_unop (icode, ops); + DONE; +}) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index a4ac688e373..35e98a6f3f7 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -803,11 +803,14 @@ ;; - vfcvt.rtz.x.f.v ;; ------------------------------------------------------------------------- -(define_expand "2" +(define_insn_and_split "2" [(set (match_operand: 0 "register_operand") (any_fix: (match_operand:VF 1 "register_operand")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] { insn_code icode = code_for_pred (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); @@ -822,11 +825,14 @@ ;; - vfcvt.f.x.v ;; ------------------------------------------------------------------------- -(define_expand "2" +(define_insn_and_split "2" [(set (match_operand:VF 0 "register_operand") (any_float:VF (match_operand: 1 "register_operand")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] { insn_code icode = code_for_pred (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands); @@ -844,11 +850,14 @@ ;; - vfwcvt.rtz.xu.f.v ;; - vfwcvt.rtz.x.f.v ;; ------------------------------------------------------------------------- -(define_expand "2" +(define_insn_and_split "2" [(set (match_operand:VWCONVERTI 0 "register_operand") (any_fix:VWCONVERTI (match_operand: 1 "register_operand")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] { insn_code icode = code_for_pred_widen (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); @@ -862,11 +871,14 @@ ;; - vfwcvt.f.xu.v ;; - vfwcvt.f.x.v ;; ------------------------------------------------------------------------- -(define_expand "2" +(define_insn_and_split "2" [(set (match_operand:VF 0 "register_operand") (any_float:VF (match_operand: 1 "register_operand")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] { insn_code icode = code_for_pred_widen (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); @@ -880,11 +892,14 @@ ;; - vfncvt.rtz.xu.f.v ;; - vfncvt.rtz.x.f.v ;; ------------------------------------------------------------------------- -(define_expand "2" +(define_insn_and_split "2" [(set (match_operand: 0 "register_operand") (any_fix: (match_operand:VF 1 "register_operand")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] { insn_code icode = code_for_pred_narrow (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); @@ -898,11 +913,14 @@ ;; - vfncvt.f.xu.w ;; - vfncvt.f.x.w ;; ------------------------------------------------------------------------- -(define_expand "2" +(define_insn_and_split "2" [(set (match_operand: 0 "register_operand") (any_float: (match_operand:VWCONVERTI 1 "register_operand")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] { insn_code icode = code_for_pred_narrow (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 0f414663620..cdb459f2a47 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -2968,7 +2968,10 @@ needs_fp_rounding (unsigned icode, machine_mode mode) && icode != maybe_code_for_pred (NEG, mode) && icode != maybe_code_for_pred (ABS, mode) /* narrower-FP -> FP */ - && icode != maybe_code_for_pred_extend (mode); + && icode != maybe_code_for_pred_extend (mode) + /* narrower-INT -> FP */ + && icode != maybe_code_for_pred_widen (FLOAT, mode) + && icode != maybe_code_for_pred_widen (UNSIGNED_FLOAT, mode); } /* Subroutine to expand COND_LEN_* patterns. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h new file mode 100644 index 00000000000..2df68aa2d1e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h @@ -0,0 +1,51 @@ +#include + +#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \ + void __attribute__ ((noipa)) \ + test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \ + OLD_TYPE *__restrict a, \ + NEW_TYPE *__restrict b, \ + OLD_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + r[i] = pred[i] ? (NEW_TYPE) a[i] : b[i]; \ + } \ + } + +/* FP -> INT */ +#define TEST_ALL_F2X_SAME(T) \ + T (_Float16, uint16_t) \ + T (_Float16, int16_t) \ + T (float, uint32_t) \ + T (float, int32_t) \ + T (double, uint64_t) \ + T (double, int64_t) + +/* FP -> wider-INT */ +#define TEST_ALL_F2X_WIDER(T) \ + T (_Float16, uint32_t) \ + T (_Float16, int32_t) \ + T (_Float16, uint64_t) \ + T (_Float16, int64_t) \ + T (float, uint64_t) \ + T (float, int64_t) + +/* FP -> narrower-INT */ +#define TEST_ALL_F2X_NARROWER(T) \ + T (_Float16, uint8_t) \ + T (_Float16, int8_t) \ + T (float, uint8_t) \ + T (float, int8_t) \ + T (float, uint16_t) \ + T (float, int16_t) \ + T (double, uint8_t) \ + T (double, int8_t) \ + T (double, uint16_t) \ + T (double, int16_t) \ + T (double, uint32_t) \ + T (double, int32_t) + +TEST_ALL_F2X_SAME (DEF_LOOP) +TEST_ALL_F2X_WIDER (DEF_LOOP) +TEST_ALL_F2X_NARROWER (DEF_LOOP) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h new file mode 100644 index 00000000000..9735141faa1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h @@ -0,0 +1,50 @@ +#include + +#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \ + void __attribute__ ((noipa)) \ + test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \ + OLD_TYPE *__restrict a, NEW_TYPE b, \ + OLD_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + r[i] = pred[i] ? (NEW_TYPE) a[i] : b; \ + } \ + } + +/* FP -> INT */ +#define TEST_ALL_F2X_SAME(T) \ + T (_Float16, uint16_t) \ + T (_Float16, int16_t) \ + T (float, uint32_t) \ + T (float, int32_t) \ + T (double, uint64_t) \ + T (double, int64_t) + +/* FP -> wider-INT */ +#define TEST_ALL_F2X_WIDER(T) \ + T (_Float16, uint32_t) \ + T (_Float16, int32_t) \ + T (_Float16, uint64_t) \ + T (_Float16, int64_t) \ + T (float, uint64_t) \ + T (float, int64_t) + +/* FP -> narrower-INT */ +#define TEST_ALL_F2X_NARROWER(T) \ + T (_Float16, uint8_t) \ + T (_Float16, int8_t) \ + T (float, uint8_t) \ + T (float, int8_t) \ + T (float, uint16_t) \ + T (float, int16_t) \ + T (double, uint8_t) \ + T (double, int8_t) \ + T (double, uint16_t) \ + T (double, int16_t) \ + T (double, uint32_t) \ + T (double, int32_t) + +TEST_ALL_F2X_SAME (DEF_LOOP) +TEST_ALL_F2X_WIDER (DEF_LOOP) +TEST_ALL_F2X_NARROWER (DEF_LOOP) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c new file mode 100644 index 00000000000..0702b60c551 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2int-1.h" + +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ + +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c new file mode 100644 index 00000000000..6eeed28ee6b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2int-2.h" + +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ + +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c new file mode 100644 index 00000000000..43f7150fa0b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2int-1.h" + +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ + +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c new file mode 100644 index 00000000000..e4a1b175d9f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2int-2.h" + +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ + +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c new file mode 100644 index 00000000000..65b54bb3c83 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_float2int-1.h" + +#define N 99 + +#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \ + { \ + NEW_TYPE r[N], b[N]; \ + OLD_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + b[i] = (i % 9) * (i % 7 + 1); \ + pred[i] = (i % 7 < 4); \ + asm volatile("" ::: "memory"); \ + } \ + test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b[i])) \ + __builtin_abort (); \ + } + +int +main () +{ + TEST_ALL_F2X_SAME (TEST_LOOP) + TEST_ALL_F2X_WIDER (TEST_LOOP) + TEST_ALL_F2X_NARROWER (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c new file mode 100644 index 00000000000..030ea2c1964 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_float2int-2.h" + +#define N 99 + +#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \ + { \ + NEW_TYPE r[N], b = 192; \ + OLD_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + pred[i] = (i % 7 < 4); \ + asm volatile("" ::: "memory"); \ + } \ + test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b)) \ + __builtin_abort (); \ + } + +int +main () +{ + TEST_ALL_F2X_SAME (TEST_LOOP) + TEST_ALL_F2X_WIDER (TEST_LOOP) + TEST_ALL_F2X_NARROWER (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h new file mode 100644 index 00000000000..5b0baeece41 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h @@ -0,0 +1,45 @@ +#include + +#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \ + void __attribute__ ((noipa)) \ + test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \ + OLD_TYPE *__restrict a, \ + NEW_TYPE *__restrict b, \ + OLD_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + r[i] = pred[i] ? (NEW_TYPE) a[i] : b[i]; \ + } \ + } + +/* INT -> FP */ +#define TEST_ALL_X2F_SAME(T) \ + T (uint16_t, _Float16) \ + T (int16_t, _Float16) \ + T (uint32_t, float) \ + T (int32_t, float) \ + T (uint64_t, double) \ + T (int64_t, double) + +/* INT -> wider-FP */ +#define TEST_ALL_X2F_WIDER(T) \ + T (uint16_t, float) \ + T (int16_t, float) \ + T (uint16_t, double) \ + T (int16_t, double) \ + T (uint32_t, double) \ + T (int32_t, double) + +/* INT -> narrower-FP */ +#define TEST_ALL_X2F_NARROWER(T) \ + T (uint32_t, _Float16) \ + T (int32_t, _Float16) \ + T (uint64_t, _Float16) \ + T (int64_t, _Float16) \ + T (uint64_t, float) \ + T (int64_t, float) + +TEST_ALL_X2F_SAME (DEF_LOOP) +TEST_ALL_X2F_WIDER (DEF_LOOP) +TEST_ALL_X2F_NARROWER (DEF_LOOP) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h new file mode 100644 index 00000000000..2177c946de8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h @@ -0,0 +1,44 @@ +#include + +#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \ + void __attribute__ ((noipa)) \ + test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \ + OLD_TYPE *__restrict a, NEW_TYPE b, \ + OLD_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + r[i] = pred[i] ? (NEW_TYPE) a[i] : b; \ + } \ + } + +/* INT -> FP */ +#define TEST_ALL_X2F_SAME(T) \ + T (uint16_t, _Float16) \ + T (int16_t, _Float16) \ + T (uint32_t, float) \ + T (int32_t, float) \ + T (uint64_t, double) \ + T (int64_t, double) + +/* INT -> wider-FP */ +#define TEST_ALL_X2F_WIDER(T) \ + T (uint16_t, float) \ + T (int16_t, float) \ + T (uint16_t, double) \ + T (int16_t, double) \ + T (uint32_t, double) \ + T (int32_t, double) + +/* INT -> narrower-FP */ +#define TEST_ALL_X2F_NARROWER(T) \ + T (uint32_t, _Float16) \ + T (int32_t, _Float16) \ + T (uint64_t, _Float16) \ + T (int64_t, _Float16) \ + T (uint64_t, float) \ + T (int64_t, float) + +TEST_ALL_X2F_SAME (DEF_LOOP) +TEST_ALL_X2F_WIDER (DEF_LOOP) +TEST_ALL_X2F_NARROWER (DEF_LOOP) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c new file mode 100644 index 00000000000..fbb1a28791d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_int2float-2.h" + +/* { dg-final { scan-assembler-times {\tvfcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ + +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */ + +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.xu\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c new file mode 100644 index 00000000000..fbb1a28791d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_int2float-2.h" + +/* { dg-final { scan-assembler-times {\tvfcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ + +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */ + +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.xu\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c new file mode 100644 index 00000000000..2f85c819709 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_int2float-1.h" + +/* { dg-final { scan-assembler-times {\tvfcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ + +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */ + +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.xu\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c new file mode 100644 index 00000000000..2f4fdd728bb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_int2float-2.h" + +/* { dg-final { scan-assembler-times {\tvfcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ + +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */ + +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.xu\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c new file mode 100644 index 00000000000..10bc06757c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_int2float-1.h" + +#define N 99 + +#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \ + { \ + NEW_TYPE r[N], b[N]; \ + OLD_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + b[i] = (i % 9) * (i % 7 + 1); \ + pred[i] = (i % 7 < 4); \ + asm volatile("" ::: "memory"); \ + } \ + test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b[i])) \ + __builtin_abort (); \ + } + +int +main () +{ + TEST_ALL_X2F_SAME (TEST_LOOP) + TEST_ALL_X2F_WIDER (TEST_LOOP) + TEST_ALL_X2F_NARROWER (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c new file mode 100644 index 00000000000..08d27e6dca1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_int2float-2.h" + +#define N 99 + +#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \ + { \ + NEW_TYPE r[N], b = 192.12; \ + OLD_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + pred[i] = (i % 7 < 4); \ + asm volatile("" ::: "memory"); \ + } \ + test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b)) \ + __builtin_abort (); \ + } + +int +main () +{ + TEST_ALL_X2F_SAME (TEST_LOOP) + TEST_ALL_X2F_WIDER (TEST_LOOP) + TEST_ALL_X2F_NARROWER (TEST_LOOP) + return 0; +}