From patchwork Thu Aug 24 11:40:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandr Shubin X-Patchwork-Id: 1825347 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=E9F6QyTs; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RWh501mgZz1yh2 for ; Thu, 24 Aug 2023 21:41:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241046AbjHXLlZ (ORCPT ); Thu, 24 Aug 2023 07:41:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241085AbjHXLlE (ORCPT ); Thu, 24 Aug 2023 07:41:04 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A650E1989; Thu, 24 Aug 2023 04:41:01 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2bcd7a207f7so33276241fa.3; Thu, 24 Aug 2023 04:41:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1692877259; x=1693482059; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9nwRtV/1CUIsDQRncajks7sdUUomDHsC1aZqElEGA1E=; b=E9F6QyTsqQAhwasiXnFYVaLH225TZNaejk8bGOFZ5+RZkk/CnavPGjy+nLqLpzKRHP FQiG3M466AiV78D64IEAGt26505Gf1TiFNv1XTkt73z22hTn/FOsZNrnJUBMeyAeMxiv MDjAfuo30APWp9aXkdF4aE8nxUH3Mv3Fmro5BXdQeB2PmJ3C4fnFNKzgXkVqJ4BnGXja t9Ey2teJxgEokNzIZKI6rBW6vZEgyvHkLE6uLgTCrNY589ji5a2Vn1fFCxNcfC13XhmR inA8xza3l/G+ZLTPD7AL3d5W0IJuzLYOU+e0VJouK5CoTg5AZsb8+FW7raOY5JkAweEx Y7YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692877259; x=1693482059; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9nwRtV/1CUIsDQRncajks7sdUUomDHsC1aZqElEGA1E=; b=RsZaz0fxPY6TFFKvuxKh4Yv/jG/5YQp7p2d2q0H2qnzpUtx43uFOkJuMhIX/HS5c1c 8UvysrsoZcdwLbLwhI94dqnWxbmhU79+/etMOnW+5/CRmmSpDHozgunyr+hfIcZPlUyq UovTMGKVvFEJK8rFhG2ZO6Q0t6YjRl7DHvcW2W4hj/7RabG1h1yFGRxYXkD55dRGuCWJ jOVuuUWHcoIGguZulVlhN2GIeHMX28wC9RROLGlZ703EfRqe29W0AJmCr6QFwAxbvwpG HMZ0ut42zPAxSI2Me0A6/l2X+caVHPqL/p3tpjeQSSZtEUFPUyLc900GBDd3ov80Pgf+ 9WNQ== X-Gm-Message-State: AOJu0Yw5x+Y4ScdEc9eK5vxRc0zDi+m+NBplVu2KoQ9inrDiIV/OWbGH cFdseW/RjD9/Q34Cv/QLl+TEskkH7BLgI+Y= X-Google-Smtp-Source: AGHT+IHxwe4Az2unTJJA9wSBaJpXO+z7BFt7KWn0VRDlv4aIkQOws7xlJBxUgLktAONf3kWq/rKMMw== X-Received: by 2002:a2e:3a06:0:b0:2bb:afad:ffdb with SMTP id h6-20020a2e3a06000000b002bbafadffdbmr12231574lja.28.1692877259355; Thu, 24 Aug 2023 04:40:59 -0700 (PDT) Received: from localhost.localdomain (mail.pulsar-telecom.ru. [94.181.180.60]) by smtp.gmail.com with ESMTPSA id o17-20020a2e0c51000000b002ba053e1f9bsm534568ljd.35.2023.08.24.04.40.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 04:40:58 -0700 (PDT) From: Aleksandr Shubin To: linux-kernel@vger.kernel.org Cc: Aleksandr Shubin , Conor Dooley , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Cristian Ciocaltea , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: [PATCH v6 1/3] dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM controller Date: Thu, 24 Aug 2023 14:40:25 +0300 Message-Id: <20230824114038.891493-2-privatesub2@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230824114038.891493-1-privatesub2@gmail.com> References: <20230824114038.891493-1-privatesub2@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Allwinner's D1, T113-S3 and R329 SoCs have a new pwm controller witch is different from the previous pwm-sun4i. The D1 and T113 are identical in terms of peripherals, they differ only in the architecture of the CPU core, and even share the majority of their DT. Because of that, using the same compatible makes sense. The R329 is a different SoC though, and should have a different compatible string added, especially as there is a difference in the number of channels. D1 and T113s SoCs have one PWM controller with 8 channels. R329 SoC has two PWM controllers in both power domains, one of them has 9 channels (CPUX one) and the other has 6 (CPUS one). Add a device tree binding for them. Signed-off-by: Aleksandr Shubin Reviewed-by: Conor Dooley --- .../bindings/pwm/allwinner,sun20i-pwm.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml new file mode 100644 index 000000000000..a65324e9b138 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner D1, T113-S3 and R329 PWM + +maintainers: + - Aleksandr Shubin + +properties: + compatible: + oneOf: + - const: allwinner,sun20i-d1-pwm + - items: + - const: allwinner,sun20i-r329-pwm + - const: allwinner,sun20i-d1-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: Bus clock + - description: 24 MHz oscillator + - description: APB0 clock + + clock-names: + items: + - const: bus + - const: hosc + - const: apb0 + + resets: + maxItems: 1 + + allwinner,pwm-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [6, 9] + +allOf: + - $ref: pwm.yaml# + + - if: + properties: + compatible: + contains: + const: allwinner,sun20i-r329-pwm + + then: + required: + - allwinner,pwm-channels + + else: + properties: + allwinner,pwm-channels: false + +unevaluatedProperties: false + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + - resets + +examples: + - | + #include + #include + + pwm: pwm@2000c00 { + compatible = "allwinner,sun20i-d1-pwm"; + reg = <0x02000c00 0x400>; + clocks = <&ccu CLK_BUS_PWM>, <&dcxo>, <&ccu CLK_APB0>; + clock-names = "bus", "hosc", "apb0"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <0x3>; + }; + +... From patchwork Thu Aug 24 11:40:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandr Shubin X-Patchwork-Id: 1825345 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=g8WIHyOj; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RWh4z3wfBz1yZs for ; Thu, 24 Aug 2023 21:41:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241089AbjHXLl0 (ORCPT ); Thu, 24 Aug 2023 07:41:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241091AbjHXLlP (ORCPT ); Thu, 24 Aug 2023 07:41:15 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8CB31987; Thu, 24 Aug 2023 04:41:12 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2bcde83ce9fso22608451fa.1; Thu, 24 Aug 2023 04:41:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1692877271; x=1693482071; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mWIKE8j/3QkR8emVgnBh9q3nwWi/TLYvS5Bk43r9b1A=; b=g8WIHyOjZOhCYDrde2e0Ylqehak+2wI34E6N3LtNyGcBQRQoAcQjNCzSsGXhsuCK4q 3UpXnbBFILBuCmJXtZNmHG6rIDvsjNXk+Zaa7WsZgtef+/nVFzCrSLbGq/aRhIl5lzgi HbGODQVD1JVVjnHIQDEZCcFIyZeCa6SMxjd9U7WzFSQKicQhN5dAq72xxCwt2SLGpFRm +Gu4fjP6PqIM+B2BhvvRNvNlvBjjbxCG5aC68HmJ8zJGRTDY0gKXVvm25Iffr3+fVjOJ SxhzMB+talVvBeMl1j+AV7easVKw0eB5PjGaUbLhgsnrzS9UI4pTp+zmxLLFfahAlM/G MJ+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692877271; x=1693482071; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mWIKE8j/3QkR8emVgnBh9q3nwWi/TLYvS5Bk43r9b1A=; b=Z9VEoO4ANGaHAwCrnBYCPfvSSxdif44moRtvSuxaPrXPewdxF15grUKMF4IpzGvvIK qer+d2Q4Ea1RpfKy9TlAc1NDHl+aV8rjAipkWUL0K4TXCYJ+To++INbQ6k4R18P38Rfo 1NQIbDFws6Or24JZMH9R0n1PZL3nhMxnn6zbbRdLg01sp+3GIEVpBluVHi95A65SO8nW uzEYUuNW5HaEOGMXKabuNzu5ByeJ5+12dhWbIjuFYdEZiDpWspwZX0D0b1irIJVJ549O 3EWsZQYz3FFGSLOWQB/v8UnJm8YbxG/Jx1blk/y/5OLCP6DJkFfnKOAW5pEZzD33Uy1G gi4A== X-Gm-Message-State: AOJu0YytrWYoVNv0G3F13vruPZ2nPJs1DsboR14VwEyWjKWypO+Q3Yz5 b1erab05zOFeDGcx+41oMn9X9taipandctM= X-Google-Smtp-Source: AGHT+IEok6ypWPk2unFTxmMcLOLxQJhyjEgrb8E444a0oNagLFuI0pLK/dMrIbEHugPcx813xUWN2A== X-Received: by 2002:a05:651c:1052:b0:2bc:c466:60e9 with SMTP id x18-20020a05651c105200b002bcc46660e9mr7645259ljm.49.1692877270467; Thu, 24 Aug 2023 04:41:10 -0700 (PDT) Received: from localhost.localdomain (mail.pulsar-telecom.ru. [94.181.180.60]) by smtp.gmail.com with ESMTPSA id o17-20020a2e0c51000000b002ba053e1f9bsm534568ljd.35.2023.08.24.04.41.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 04:41:10 -0700 (PDT) From: Aleksandr Shubin To: linux-kernel@vger.kernel.org Cc: Aleksandr Shubin , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Cristian Ciocaltea , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: [PATCH v6 2/3] pwm: Add Allwinner's D1/T113-S3/R329 SoCs PWM support Date: Thu, 24 Aug 2023 14:40:26 +0300 Message-Id: <20230824114038.891493-3-privatesub2@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230824114038.891493-1-privatesub2@gmail.com> References: <20230824114038.891493-1-privatesub2@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Allwinner's D1, T113-S3 and R329 SoCs have a quite different PWM controllers with ones supported by pwm-sun4i driver. This patch adds a PWM controller driver for Allwinner's D1, T113-S3 and R329 SoCs. The main difference between these SoCs is the number of channels defined by the DT property. Signed-off-by: Aleksandr Shubin --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sun20i.c | 328 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 339 insertions(+) create mode 100644 drivers/pwm/pwm-sun20i.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 8df861b1f4a3..05c48a36969e 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -594,6 +594,16 @@ config PWM_SUN4I To compile this driver as a module, choose M here: the module will be called pwm-sun4i. +config PWM_SUN20I + tristate "Allwinner D1/T113s/R329 PWM support" + depends on ARCH_SUNXI || COMPILE_TEST + depends on COMMON_CLK + help + Generic PWM framework driver for Allwinner D1/T113s/R329 SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-sun20i. + config PWM_SUNPLUS tristate "Sunplus PWM support" depends on ARCH_SUNPLUS || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 19899b912e00..cea872e22c78 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_PWM_STM32) += pwm-stm32.o obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o +obj-$(CONFIG_PWM_SUN20I) += pwm-sun20i.o obj-$(CONFIG_PWM_SUNPLUS) += pwm-sunplus.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o diff --git a/drivers/pwm/pwm-sun20i.c b/drivers/pwm/pwm-sun20i.c new file mode 100644 index 000000000000..20e6b7b5b62e --- /dev/null +++ b/drivers/pwm/pwm-sun20i.c @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PWM Controller Driver for sunxi platforms (D1, T113-S3 and R329) + * + * Limitations: + * - When the parameters change, current running period will not be completed + * and run new settings immediately. + * - It output HIGH-Z state when PWM channel disabled. + * + * Copyright (c) 2023 Aleksandr Shubin + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PWM_CLK_CFG(chan) (0x20 + (((chan) >> 1) * 0x4)) +#define PWM_CLK_CFG_SRC GENMASK(8, 7) +#define PWM_CLK_CFG_DIV_M GENMASK(3, 0) + +#define PWM_CLK_GATE 0x40 +#define PWM_CLK_GATE_BYPASS(chan) BIT((chan) - 16) +#define PWM_CLK_GATE_GATING(chan) BIT(chan) + +#define PWM_ENABLE 0x80 +#define PWM_ENABLE_EN(chan) BIT(chan) + +#define PWM_CTL(chan) (0x100 + (chan) * 0x20) +#define PWM_CTL_ACT_STA BIT(8) +#define PWM_CTL_PRESCAL_K GENMASK(7, 0) + +#define PWM_PERIOD(chan) (0x104 + (chan) * 0x20) +#define PWM_PERIOD_ENTIRE_CYCLE GENMASK(31, 16) +#define PWM_PERIOD_ACT_CYCLE GENMASK(15, 0) + +#define PWM_MAGIC (255 * 65535 + 2 * 65534 + 1) + +struct sun20i_pwm_chip { + struct clk *clk_bus, *clk_hosc, *clk_apb0; + struct reset_control *rst; + struct pwm_chip chip; + void __iomem *base; + /* Mutex to protect pwm apply state */ + struct mutex mutex; +}; + +static inline struct sun20i_pwm_chip *to_sun20i_pwm_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct sun20i_pwm_chip, chip); +} + +static inline u32 sun20i_pwm_readl(struct sun20i_pwm_chip *chip, + unsigned long offset) +{ + return readl(chip->base + offset); +} + +static inline void sun20i_pwm_writel(struct sun20i_pwm_chip *chip, + u32 val, unsigned long offset) +{ + writel(val, chip->base + offset); +} + +static int sun20i_pwm_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct sun20i_pwm_chip *sun20i_chip = to_sun20i_pwm_chip(chip); + u16 ent_cycle, act_cycle, prescal; + u64 clk_rate, tmp; + u8 div_id; + u32 val; + + mutex_lock(&sun20i_chip->mutex); + + val = sun20i_pwm_readl(sun20i_chip, PWM_CLK_CFG(pwm->hwpwm)); + div_id = FIELD_GET(PWM_CLK_CFG_DIV_M, val); + if (FIELD_GET(PWM_CLK_CFG_SRC, val) == 0) + clk_rate = clk_get_rate(sun20i_chip->clk_hosc); + else + clk_rate = clk_get_rate(sun20i_chip->clk_apb0); + + val = sun20i_pwm_readl(sun20i_chip, PWM_CTL(pwm->hwpwm)); + state->polarity = (PWM_CTL_ACT_STA & val) ? PWM_POLARITY_NORMAL : PWM_POLARITY_INVERSED; + + prescal = FIELD_GET(PWM_CTL_PRESCAL_K, val) + 1; + + val = sun20i_pwm_readl(sun20i_chip, PWM_ENABLE); + state->enabled = (PWM_ENABLE_EN(pwm->hwpwm) & val) ? true : false; + + val = sun20i_pwm_readl(sun20i_chip, PWM_PERIOD(pwm->hwpwm)); + act_cycle = FIELD_GET(PWM_PERIOD_ACT_CYCLE, val); + ent_cycle = FIELD_GET(PWM_PERIOD_ENTIRE_CYCLE, val); + + /* + * The duration of the active phase should not be longer + * than the duration of the period + */ + if (act_cycle > ent_cycle) + act_cycle = ent_cycle; + + tmp = ((u64)(act_cycle) * prescal << div_id) * NSEC_PER_SEC; + state->duty_cycle = DIV_ROUND_UP_ULL(tmp, clk_rate); + tmp = ((u64)(ent_cycle) * prescal << div_id) * NSEC_PER_SEC; + state->period = DIV_ROUND_UP_ULL(tmp, clk_rate); + mutex_unlock(&sun20i_chip->mutex); + + return 0; +} + +static int sun20i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct sun20i_pwm_chip *sun20i_chip = to_sun20i_pwm_chip(chip); + u32 clk_gate, clk_cfg, pwm_en, ctl, period; + u64 bus_rate, hosc_rate, clk_div, val; + u32 prescaler, div_m; + bool use_bus_clk; + int ret = 0; + + mutex_lock(&sun20i_chip->mutex); + + pwm_en = sun20i_pwm_readl(sun20i_chip, PWM_ENABLE); + + if (state->enabled != pwm->state.enabled) + clk_gate = sun20i_pwm_readl(sun20i_chip, PWM_CLK_GATE); + + if (state->enabled != pwm->state.enabled && !state->enabled) { + clk_gate &= ~PWM_CLK_GATE_GATING(pwm->hwpwm); + pwm_en &= ~PWM_ENABLE_EN(pwm->hwpwm); + sun20i_pwm_writel(sun20i_chip, pwm_en, PWM_ENABLE); + sun20i_pwm_writel(sun20i_chip, clk_gate, PWM_CLK_GATE); + } + + if (state->polarity != pwm->state.polarity || + state->duty_cycle != pwm->state.duty_cycle || + state->period != pwm->state.period) { + ctl = sun20i_pwm_readl(sun20i_chip, PWM_CTL(pwm->hwpwm)); + clk_cfg = sun20i_pwm_readl(sun20i_chip, PWM_CLK_CFG(pwm->hwpwm)); + hosc_rate = clk_get_rate(sun20i_chip->clk_hosc); + bus_rate = clk_get_rate(sun20i_chip->clk_apb0); + if (pwm_en & PWM_ENABLE_EN(pwm->hwpwm ^ 1)) { + /* if the neighbor channel is enable, check period only */ + use_bus_clk = FIELD_GET(PWM_CLK_CFG_SRC, clk_cfg) != 0; + val = state->period * (use_bus_clk ? bus_rate : hosc_rate); + do_div(val, NSEC_PER_SEC); + + div_m = FIELD_GET(PWM_CLK_CFG_DIV_M, clk_cfg); + } else { + /* check period and select clock source */ + use_bus_clk = false; + val = state->period * hosc_rate; + do_div(val, NSEC_PER_SEC); + if (val <= 1) { + use_bus_clk = true; + val = state->period * bus_rate; + do_div(val, NSEC_PER_SEC); + if (val <= 1) { + ret = -EINVAL; + goto unlock_mutex; + } + } + div_m = fls(DIV_ROUND_DOWN_ULL(val, PWM_MAGIC)); + if (div_m >= 9) { + ret = -EINVAL; + goto unlock_mutex; + } + + /* set up the CLK_DIV_M and clock CLK_SRC */ + clk_cfg = FIELD_PREP(PWM_CLK_CFG_DIV_M, div_m); + clk_cfg |= FIELD_PREP(PWM_CLK_CFG_SRC, use_bus_clk); + + sun20i_pwm_writel(sun20i_chip, clk_cfg, PWM_CLK_CFG(pwm->hwpwm)); + } + + /* calculate prescaler, PWM entire cycle */ + clk_div = val >> div_m; + if (clk_div <= 65534) { + prescaler = 0; + } else { + prescaler = DIV_ROUND_UP_ULL(clk_div - 65534, 65535); + if (prescaler >= 256) { + ret = -EINVAL; + goto unlock_mutex; + } + do_div(clk_div, prescaler + 1); + } + + period = FIELD_PREP(PWM_PERIOD_ENTIRE_CYCLE, clk_div); + + /* set duty cycle */ + val = state->duty_cycle * (use_bus_clk ? bus_rate : hosc_rate); + do_div(val, NSEC_PER_SEC); + clk_div = val >> div_m; + do_div(clk_div, prescaler + 1); + + /* + * The formula of the output period and the duty-cycle for PWM are as follows. + * T period = (PWM01_CLK / PWM0_PRESCALE_K)^-1 * (PPR0.PWM_ENTIRE_CYCLE + 1) + * T high-level = (PWM01_CLK / PWM0_PRESCALE_K)^-1 * PPR0.PWM_ACT_CYCLE + * Duty-cycle = T high-level / T period + * In accordance with this formula, in order to set the duty-cycle to 100%, + * it is necessary that PWM_ACT_CYCLE >= PWM_ENTIRE_CYCLE + 1 + */ + if (state->duty_cycle == state->period) + clk_div++; + period |= FIELD_PREP(PWM_PERIOD_ACT_CYCLE, clk_div); + sun20i_pwm_writel(sun20i_chip, period, PWM_PERIOD(pwm->hwpwm)); + + ctl = FIELD_PREP(PWM_CTL_PRESCAL_K, prescaler); + if (state->polarity == PWM_POLARITY_NORMAL) + ctl |= PWM_CTL_ACT_STA; + + sun20i_pwm_writel(sun20i_chip, ctl, PWM_CTL(pwm->hwpwm)); + } + + if (state->enabled != pwm->state.enabled && state->enabled) { + clk_gate &= ~PWM_CLK_GATE_BYPASS(pwm->hwpwm); + clk_gate |= PWM_CLK_GATE_GATING(pwm->hwpwm); + pwm_en |= PWM_ENABLE_EN(pwm->hwpwm); + sun20i_pwm_writel(sun20i_chip, pwm_en, PWM_ENABLE); + sun20i_pwm_writel(sun20i_chip, clk_gate, PWM_CLK_GATE); + } + +unlock_mutex: + mutex_unlock(&sun20i_chip->mutex); + + return ret; +} + +static const struct pwm_ops sun20i_pwm_ops = { + .get_state = sun20i_pwm_get_state, + .apply = sun20i_pwm_apply, + .owner = THIS_MODULE, +}; + +static const struct of_device_id sun20i_pwm_dt_ids[] = { + { .compatible = "allwinner,sun20i-d1-pwm" }, + { }, +}; +MODULE_DEVICE_TABLE(of, sun20i_pwm_dt_ids); + +static int sun20i_pwm_probe(struct platform_device *pdev) +{ + struct sun20i_pwm_chip *sun20i_chip; + int ret; + + sun20i_chip = devm_kzalloc(&pdev->dev, sizeof(*sun20i_chip), GFP_KERNEL); + if (!sun20i_chip) + return -ENOMEM; + + sun20i_chip->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sun20i_chip->base)) + return PTR_ERR(sun20i_chip->base); + + sun20i_chip->clk_bus = devm_clk_get_enabled(&pdev->dev, "bus"); + if (IS_ERR(sun20i_chip->clk_bus)) + return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->clk_bus), + "failed to get bus clock\n"); + + sun20i_chip->clk_hosc = devm_clk_get_enabled(&pdev->dev, "hosc"); + if (IS_ERR(sun20i_chip->clk_hosc)) + return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->clk_hosc), + "failed to get hosc clock\n"); + + sun20i_chip->clk_apb0 = devm_clk_get_enabled(&pdev->dev, "apb0"); + if (IS_ERR(sun20i_chip->clk_apb0)) + return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->clk_apb0), + "failed to get apb0 clock\n"); + + sun20i_chip->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(sun20i_chip->rst)) + return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->rst), + "failed to get bus reset\n"); + + ret = of_property_read_u32(pdev->dev.of_node, "allwinner,pwm-channels", + &sun20i_chip->chip.npwm); + if (ret) + sun20i_chip->chip.npwm = 8; + + /* Deassert reset */ + ret = reset_control_deassert(sun20i_chip->rst); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to deassert reset\n"); + + sun20i_chip->chip.dev = &pdev->dev; + sun20i_chip->chip.ops = &sun20i_pwm_ops; + + mutex_init(&sun20i_chip->mutex); + + ret = pwmchip_add(&sun20i_chip->chip); + if (ret < 0) { + reset_control_assert(sun20i_chip->rst); + return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n"); + } + + platform_set_drvdata(pdev, sun20i_chip); + + return 0; +} + +static void sun20i_pwm_remove(struct platform_device *pdev) +{ + struct sun20i_pwm_chip *sun20i_chip = platform_get_drvdata(pdev); + + pwmchip_remove(&sun20i_chip->chip); + + reset_control_assert(sun20i_chip->rst); +} + +static struct platform_driver sun20i_pwm_driver = { + .driver = { + .name = "sun20i-pwm", + .of_match_table = sun20i_pwm_dt_ids, + }, + .probe = sun20i_pwm_probe, + .remove_new = sun20i_pwm_remove, +}; +module_platform_driver(sun20i_pwm_driver); + +MODULE_AUTHOR("Aleksandr Shubin "); +MODULE_DESCRIPTION("Allwinner sun20i PWM driver"); +MODULE_LICENSE("GPL"); From patchwork Thu Aug 24 11:40:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandr Shubin X-Patchwork-Id: 1825348 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=IKtvF8nm; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RWh5c2GYPz1yZs for ; Thu, 24 Aug 2023 21:42:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241096AbjHXLl4 (ORCPT ); Thu, 24 Aug 2023 07:41:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241094AbjHXLl0 (ORCPT ); Thu, 24 Aug 2023 07:41:26 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AFF31987; Thu, 24 Aug 2023 04:41:24 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id 38308e7fff4ca-2bcb89b476bso72878401fa.1; Thu, 24 Aug 2023 04:41:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1692877282; x=1693482082; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lYEBuXLu4uE2kJ2ozzMWwnVNoOekh2iwP5U6RNf7wSQ=; b=IKtvF8nmYy3jZ7/tJ1ocNP83YPhmUOfU1ukKLrZoQ6NlIktkzevrCQrmnmiW4x0qzW HBI4kVl2oTb/QFXqzblfGXbqZ9nkrWF3UbKlS7ie5LUa3Ewrwlmib/AGoAa+uXp/sq9L zpWyllOijHQbzEjlhrDvRBGgNtKdereRvqMDxclED6/MvyPD+YZX6RGlcnALjWO44THx 1DjSTu8htrFdTfgfjsHEpiwzll6TF1HKu5m6j7ZbCYBz3WXvGtXvNWf1g2FVfPbFoazR WGvenfJw+bnejp3NWw5nt6qPME6QQLaj0sszl3S1ryTnnViYmWGUSB3OK2e3HnZ62lFg 056g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692877282; x=1693482082; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lYEBuXLu4uE2kJ2ozzMWwnVNoOekh2iwP5U6RNf7wSQ=; b=jyJ84GbUrwcSB45k9mEVWw4/2BGdqq+sIINjDbw2RKqcwU5JeeKlkIHIyn6qkNzHEX +lPC5U849xRtvVEQwixoA3Gjc/CyI2fQyKPSWs4XZSXNOXCx83qMTO6a86Uh4eMS4AOv cHizEpuDq8piJ1yyN8rbnqTIhXOTsh1ijbK4SFlE3xMDWMs2H/GNj+Lnbfo4JUGWOy53 Wx0ZEHOE9qSq1s6nU6cpbbZYjpJBDz5Ls+buGFddYr81uGdrrgHKusUziQUIrtTw0DI6 tBlyKwdR/S+iHMCuRcn6WdYs6r7tJDLzHtJ4nzb1InY4yUjzr3f2Nccey262vwph641n S0XQ== X-Gm-Message-State: AOJu0YzjcLlEU4b0ZjlzP4JH1aRvWG33fKVGtkzxMskMk9BNDxJnTO2K djR3nWs/RjQzXBQv9G+XS7Epbo3tD+gvx8U= X-Google-Smtp-Source: AGHT+IGosD9atNDiPZaywzwFkj+U9Wv2BBqLfQ1/+Gnx3OMtc/Isue8TDcEuNM0sXvJzNSBzWrxEzA== X-Received: by 2002:a2e:9e09:0:b0:2b6:dac0:affe with SMTP id e9-20020a2e9e09000000b002b6dac0affemr11525371ljk.31.1692877281745; Thu, 24 Aug 2023 04:41:21 -0700 (PDT) Received: from localhost.localdomain (mail.pulsar-telecom.ru. [94.181.180.60]) by smtp.gmail.com with ESMTPSA id o17-20020a2e0c51000000b002ba053e1f9bsm534568ljd.35.2023.08.24.04.41.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 04:41:21 -0700 (PDT) From: Aleksandr Shubin To: linux-kernel@vger.kernel.org Cc: Aleksandr Shubin , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Cristian Ciocaltea , Greg Kroah-Hartman , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: [PATCH v6 3/3] riscv: dts: allwinner: d1: Add pwm node Date: Thu, 24 Aug 2023 14:40:27 +0300 Message-Id: <20230824114038.891493-4-privatesub2@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230824114038.891493-1-privatesub2@gmail.com> References: <20230824114038.891493-1-privatesub2@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org D1 and T113s contain a pwm controller with 8 channels. This controller is supported by the sun20i-pwm driver. Add a device tree node for it. Signed-off-by: Aleksandr Shubin --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 922e8e0e2c09..c4ce13ab9512 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -127,6 +127,18 @@ uart3_pb_pins: uart3-pb-pins { }; }; + pwm: pwm@2000c00 { + compatible = "allwinner,sun20i-d1-pwm"; + reg = <0x02000c00 0x400>; + clocks = <&ccu CLK_BUS_PWM>, + <&dcxo>, + <&ccu CLK_APB0>; + clock-names = "bus", "hosc", "apb0"; + resets = <&ccu RST_BUS_PWM>; + status = "disabled"; + #pwm-cells = <0x3>; + }; + ccu: clock-controller@2001000 { compatible = "allwinner,sun20i-d1-ccu"; reg = <0x2001000 0x1000>;