From patchwork Thu Aug 17 12:43:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lehua Ding X-Patchwork-Id: 1822337 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RRPpB2vSMz1yft for ; Thu, 17 Aug 2023 22:44:18 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 58849385DC18 for ; Thu, 17 Aug 2023 12:44:16 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id 857583858C50 for ; Thu, 17 Aug 2023 12:44:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 857583858C50 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp85t1692276235tiz70ng9 Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.8]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 17 Aug 2023 20:43:54 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: swyrzWPvyR0kcFI766yAM1kqGxZ7bq4BrZ93Bs6lBiZypi34X+OfNqfUxYpyt qkm/IH5lKErLf6itXzW230+6XNbwj6uYlMVDaiTgLthlHsmjEquZzH/NZOrDwQMQdTF5hlb JFyF/Ui3wGfRxprhKB8qa3kebnwfJaSCie0NaGasOXUSmSKVRvCJrOKnG0hJANHvIEOooTb 9KzfHdVrjEvQRkftvQvmQCKv+3ITv3awVHjRDN/U00ccCG0kL9NP9xNxIbpjjRYuj8IHMLb E4591qoHHXJnCA/0Rg1vJH0IFmPZWgMr20lJZt4sA3lca6rco5WTkT4T/1EBX+MWtJ15+Lo vF56j9304n6LfUAHa1cd3ordtt91FSiHuoNlgAC580/4r7bQm2CuS+ITQSDjl/VCoeOXoDS BtkT5LzpCys= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 9230511714327642456 From: Lehua Ding To: gcc-patches@gcc.gnu.org, rdapp.gcc@gmail.com Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com Subject: [PATCH V2] RISC-V: Add the missed half floating-point mode patterns of local_pic_load/store when only use zfhmin or zhinxmin Date: Thu, 17 Aug 2023 20:43:54 +0800 Message-Id: <20230817124354.3137796-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, There is a new failed RISC-V testcase(testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c) on the current trunk branch when use medany as default cmodel. The reason is the load of half floating-point imm is convert from RTL 1 to RTL 2 as the cmodel be changed from medlow to medany. This change let insn 7 be combineed with @pred_broadcast patterns (insn 8) at combine pass. However, insn 6 and insn 7 are combined for SF and DF mode, but not for HF mode, and the fail combined leads to insn 7 and insn 8 be combined. The reason of the fail combined is the local_pic_loadhf pattern doesn't exist when only enable zfhmin(implied by zvfh). Therefore, when only zfhmin but not zfh is enabled, the define_insn of *local_pic_load must also be able to produce the pattern for *load_pic_loadhf pattern, since the zfhmin extension also includes a half floating-point load/store instructions. So, I added an ANFLSF Iterator and applied it to local_pic_load/store define_insns. I have checked other ANYF usage scenarios and feel that this is the only place that needs to be corrected. I may have missed something, please correct. Thanks. RTL 1: (insn 6 3 7 2 (set (reg:DI 137) (high:DI (symbol_ref/u:DI ("*.LC0") [flags 0x82]))) "/work/home/lding/open-source/riscv-gnu-toolchain-push/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c":7:1 discrim 3 179 {*movdi_64bit} (nil)) (insn 7 6 8 2 (set (reg:HF 136) (mem/u/c:HF (lo_sum:DI (reg:DI 137) (symbol_ref/u:DI ("*.LC0") [flags 0x82])) [0 S2 A16])) "/work/home/lding/open-source/riscv-gnu-toolchain-push/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c":7:1 discrim 3 126 {*movhf_hardfloat} (expr_list:REG_EQUAL (const_double:HF 8.8828125e+0 [0x0.8e2p+4]) (nil))) RTL 2: (insn 6 3 7 2 (set (reg/f:DI 137) (symbol_ref/u:DI ("*.LC0") [flags 0x82])) "/work/home/lding/open-source/riscv-gnu-toolchain-push/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c":7:1 discrim 3 179 {*movdi_64bit} (nil)) (insn 7 6 8 2 (set (reg:HF 136) (mem/u/c:HF (reg/f:DI 137) [0 S2 A16])) "/work/home/lding/open-source/riscv-gnu-toolchain-push/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c":7:1 discrim 3 126 {*movhf_hardfloat} (expr_list:REG_EQUAL (const_double:HF 8.8828125e+0 [0x0.8e2p+4]) (nil))) (insn 8 7 9 2 (set (reg:V2HF 135) (if_then_else:V2HF (unspec:V2BI [ (const_vector:V2BI [ (const_int 1 [0x1]) repeated x2 ]) (const_int 2 [0x2]) repeated x3 (const_int 0 [0]) (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (vec_duplicate:V2HF (reg:HF 136)) (unspec:V2HF [ (reg:SI 0 zero) ] UNSPEC_VUNDEF))) "/work/home/lding/open-source/riscv-gnu-toolchain-push/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c":6:1 discrim 3 1389 {*pred_broadcastv2hf} (nil)) Best, Lehua gcc/ChangeLog: * config/riscv/iterators.md (TARGET_HARD_FLOAT || TARGET_ZFINX): New. * config/riscv/pic.md (*local_pic_load): Change ANYF. (*local_pic_load): To ANYLSF. (*local_pic_load_32d): Ditto. (*local_pic_load_32d): Ditto. (*local_pic_store): Ditto. (*local_pic_store): Ditto. (*local_pic_store_32d): Ditto. (*local_pic_store_32d): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/_Float16-zfhmin-4.c: New test. * gcc.target/riscv/_Float16-zhinxmin-4.c: New test. --- gcc/config/riscv/iterators.md | 5 +++ gcc/config/riscv/pic.md | 34 +++++++++---------- .../gcc.target/riscv/_Float16-zfhmin-4.c | 11 ++++++ .../gcc.target/riscv/_Float16-zhinxmin-4.c | 11 ++++++ 4 files changed, 44 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-4.c diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index d374a10810c..500bbc39a6b 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -67,6 +67,11 @@ (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX") (HF "TARGET_ZFH || TARGET_ZHINX")]) +;; Iterator for hardware-supported load/store floating-point modes. +(define_mode_iterator ANYLSF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX") + (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX") + (HF "TARGET_ZFHMIN || TARGET_ZHINXMIN")]) + ;; Iterator for floating-point modes that can be loaded into X registers. (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")]) diff --git a/gcc/config/riscv/pic.md b/gcc/config/riscv/pic.md index 9507850455a..da636e31619 100644 --- a/gcc/config/riscv/pic.md +++ b/gcc/config/riscv/pic.md @@ -43,17 +43,17 @@ "u\t%0,%1" [(set (attr "length") (const_int 8))]) -;; We can support ANYF loads into X register if there is no double support +;; We can support ANYLSF loads into X register if there is no double support ;; or if the target is 64-bit. -(define_insn "*local_pic_load" - [(set (match_operand:ANYF 0 "register_operand" "=f,*r") - (mem:ANYF (match_operand 1 "absolute_symbolic_operand" ""))) +(define_insn "*local_pic_load" + [(set (match_operand:ANYLSF 0 "register_operand" "=f,*r") + (mem:ANYLSF (match_operand 1 "absolute_symbolic_operand" ""))) (clobber (match_scratch:P 2 "=r,X"))] "TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1]) && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)" "@ - \t%0,%1,%2 + \t%0,%1,%2 \t%0,%1" [(set (attr "length") (const_int 8))]) @@ -61,13 +61,13 @@ ;; supported. ld is not valid in that case. Punt for now. Maybe add a split ;; for this later. -(define_insn "*local_pic_load_32d" - [(set (match_operand:ANYF 0 "register_operand" "=f") - (mem:ANYF (match_operand 1 "absolute_symbolic_operand" ""))) +(define_insn "*local_pic_load_32d" + [(set (match_operand:ANYLSF 0 "register_operand" "=f") + (mem:ANYLSF (match_operand 1 "absolute_symbolic_operand" ""))) (clobber (match_scratch:P 2 "=r"))] "TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1]) && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)" - "\t%0,%1,%2" + "\t%0,%1,%2" [(set (attr "length") (const_int 8))]) (define_insn "*local_pic_load_sf" @@ -88,14 +88,14 @@ "\t%z1,%0,%2" [(set (attr "length") (const_int 8))]) -(define_insn "*local_pic_store" - [(set (mem:ANYF (match_operand 0 "absolute_symbolic_operand" "")) - (match_operand:ANYF 1 "register_operand" "f,*r")) +(define_insn "*local_pic_store" + [(set (mem:ANYLSF (match_operand 0 "absolute_symbolic_operand" "")) + (match_operand:ANYLSF 1 "register_operand" "f,*r")) (clobber (match_scratch:P 2 "=r,&r"))] "TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0]) && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)" "@ - \t%1,%0,%2 + \t%1,%0,%2 \t%1,%0,%2" [(set (attr "length") (const_int 8))]) @@ -103,13 +103,13 @@ ;; supported. sd is not valid in that case. Punt for now. Maybe add a split ;; for this later. -(define_insn "*local_pic_store_32d" - [(set (match_operand:ANYF 0 "register_operand" "=f") - (mem:ANYF (match_operand 1 "absolute_symbolic_operand" ""))) +(define_insn "*local_pic_store_32d" + [(set (match_operand:ANYLSF 0 "register_operand" "=f") + (mem:ANYLSF (match_operand 1 "absolute_symbolic_operand" ""))) (clobber (match_scratch:P 2 "=r"))] "TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1]) && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)" - "\t%1,%0,%2" + "\t%1,%0,%2" [(set (attr "length") (const_int 8))]) (define_insn "*local_pic_store_sf" diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-4.c b/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-4.c new file mode 100644 index 00000000000..42a238a0380 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-4.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zfhmin -mabi=lp64d -O3 -mcmodel=medany" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* Make sure zfhmin behaves the same way as zfh. */ +/* +** foo: { target { no-opts "-flto" } } +** flh\tfa0,\.LC0,[a-z0-9]+ +** ... +*/ +_Float16 foo() { return 0.8974; } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-4.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-4.c new file mode 100644 index 00000000000..4ac49228898 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-4.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64if_zfhmin -mabi=lp64 -O3 -mcmodel=medany" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* Make sure zfhmin behaves the same way as zfh. */ +/* +** foo: { target { no-opts "-flto" } } +** lh\ta0,\.LC0 +** ... +*/ +_Float16 foo() { return 0.8974; }