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MX U-Boot Team" CC: , , Yannic Moog , Daniel Schultz , Wadim Egorov Subject: [PATCH v2 1/6] board: phytec: Add common PHYTEC SoM detection Date: Thu, 17 Aug 2023 10:57:06 +0200 Message-ID: <20230817085711.45339-2-t.remmet@phytec.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230817085711.45339-1-t.remmet@phytec.de> References: <20230817085711.45339-1-t.remmet@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Florix.phytec.de (172.25.0.13) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRmVeSWpSXmKPExsWyRpKBR/fzg7spBlcO6Fg8vOpv0X7Kx+Lt 3k52iymP17NbdL9Td2D1mDfrBIvHzll32T3O3tnB6NHf3cLqsfHdDqYA1igum5TUnMyy1CJ9 uwSujJ2HtjEXXPaqmNzzmbWB8b91FyMnh4SAicSnhmtsXYxcHEICS5gk5p74DeU8Y5R4O+Mc G0gVm4CGxNMVp5lAbBGBMomHvZ+YQWxmgcWMEqt/W4LYwgJuEpPW/2UBsVkEVCU2HHsFVs8r YC5xb2U7C8Q2eYn9B8+C9XIKWEg0dd9gB7GFgGoW9exihKgXlDg58wkLxHx5ieats6F2SUgc fPGCGaJeXmLXpZOMMDOnnXvNDGGHShzZtJppAqPQLCSjZiEZNQvJqAWMzKsYhXIzk7NTizKz 9QoyKktSk/VSUjcxggJfhIFrB2PfHI9DjEwcjIcYJTiYlUR4e3hvpQjxpiRWVqUW5ccXleak Fh9ilOZgURLnvd/DlCgkkJ5YkpqdmlqQWgSTZeLglGpgNFg7eZ2zDuNnV/HCPSePXjuy+ZKB VVbn79bqT5XPeiKYFnptcWVO5RVekDglce6xoix7u8P7PBUClKIZH7RMv/WntEdSLTzE/etd sd5NL09It35Zd2AHTwBHCXfb/R+zlz02u/Nyx7G1G4+/UWQ48qTp5J6ivmCLDesPq3XlX+/M uXNWbYLhBiWW4oxEQy3mouJEAEQsImBqAgAA X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Recent shipped PHYTEC SoMs come with an i2c EEPROM containing information about the hardware such as board revision and variant. This can be used for RAM detection and loading device tree overlays during kernel start. Signed-off-by: Teresa Remmet Reviewed-by: Yannic Moog Tested-by: Yannic Moog Reviewed-by: Fabio Estevam --- Changes in v2: - none --- board/phytec/common/Kconfig | 5 + board/phytec/common/Makefile | 10 ++ board/phytec/common/phytec_som_detection.c | 188 +++++++++++++++++++++ board/phytec/common/phytec_som_detection.h | 104 ++++++++++++ 4 files changed, 307 insertions(+) create mode 100644 board/phytec/common/Kconfig create mode 100644 board/phytec/common/Makefile create mode 100644 board/phytec/common/phytec_som_detection.c create mode 100644 board/phytec/common/phytec_som_detection.h diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig new file mode 100644 index 000000000000..d614d45b1d60 --- /dev/null +++ b/board/phytec/common/Kconfig @@ -0,0 +1,5 @@ +config PHYTEC_SOM_DETECTION + bool "Support SoM detection for PHYTEC platforms" + select SPL_CRC8 if SPL + help + Support of I2C EEPROM based SoM detection. diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile new file mode 100644 index 000000000000..5fe8725ef684 --- /dev/null +++ b/board/phytec/common/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2023 PHYTEC Messtechnik GmbH +# Author: Teresa Remmet + +ifdef CONFIG_SPL_BUILD +# necessary to create built-in.o +obj- := __dummy__.o +endif + +obj-$(CONFIG_PHYTEC_SOM_DETECTION) += phytec_som_detection.o diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c new file mode 100644 index 000000000000..366bdd4ace4b --- /dev/null +++ b/board/phytec/common/phytec_som_detection.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "phytec_som_detection.h" + +struct phytec_eeprom_data eeprom_data; + +int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data, + int bus_num, int addr, int addr_fallback) +{ + int ret; + + ret = phytec_eeprom_data_init(data, bus_num, addr); + if (ret) { + pr_err("%s: init failed. Trying fall back address 0x%x\n", + __func__, addr_fallback); + ret = phytec_eeprom_data_init(data, bus_num, addr_fallback); + } + + if (ret) + pr_err("%s: EEPROM data init failed\n", __func__); + + return ret; +} + +int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + int ret; + + ret = phytec_eeprom_data_init(data, bus_num, addr); + if (ret) + pr_err("%s: EEPROM data init failed\n", __func__); + + return ret; +} + +int phytec_eeprom_data_init(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + int ret, i; + unsigned int crc; + int *ptr; + + if (!data) + data = &eeprom_data; + +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, addr, 2, &dev); + if (ret) { + pr_err("%s: i2c EEPROM not found: %i.\n", __func__, ret); + return ret; + } + + ret = dm_i2c_read(dev, 0, (uint8_t *)data, + sizeof(struct phytec_eeprom_data)); + if (ret) { + pr_err("%s: Unable to read EEPROM data\n", __func__); + return ret; + } +#else + i2c_set_bus_num(bus_num); + ret = i2c_read(addr, 0, 2, (uint8_t *)data, + sizeof(struct phytec_eeprom_data)); +#endif + + if (data->api_rev == 0xff) { + pr_err("%s: EEPROM is not flashed. Prototype?\n", __func__); + return -EINVAL; + } + + ptr = (int *)data; + for (i = 0; i < sizeof(struct phytec_eeprom_data); i += sizeof(ptr)) + if (*ptr != 0x0) + break; + + if (i == sizeof(struct phytec_eeprom_data)) { + pr_err("%s: EEPROM data is all zero. Erased?\n", __func__); + return -EINVAL; + } + + /* We are done here for early revisions */ + if (data->api_rev <= PHYTEC_API_REV1) + return 0; + + crc = crc8(0, (const unsigned char *)data, + sizeof(struct phytec_eeprom_data)); + debug("%s: crc: %x\n", __func__, crc); + + if (crc) { + pr_err("%s: CRC mismatch. EEPROM data is not usable\n", + __func__); + return -EINVAL; + } + + return 0; +} + +void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data) +{ + struct phytec_api2_data *api2; + char pcb_sub_rev; + unsigned int ksp_no, sub_som_type1, sub_som_type2; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + return; + + api2 = &data->data.data_api2; + + /* Calculate PCB subrevision */ + pcb_sub_rev = api2->pcb_sub_opt_rev & 0x0f; + pcb_sub_rev = pcb_sub_rev ? ((pcb_sub_rev - 1) + 'a') : ' '; + + /* print standard product string */ + if (api2->som_type <= 1) { + printf("SoM: %s-%03u-%s.%s PCB rev: %u%c\n", + phytec_som_type_str[api2->som_type], api2->som_no, + api2->opt, api2->bom_rev, api2->pcb_rev, pcb_sub_rev); + return; + } + /* print KSP/KSM string */ + if (api2->som_type <= 3) { + ksp_no = (api2->ksp_no << 8) | api2->som_no; + printf("SoM: %s-%u ", + phytec_som_type_str[api2->som_type], ksp_no); + /* print standard product based KSP/KSM strings */ + } else { + switch (api2->som_type) { + case 4: + sub_som_type1 = 0; + sub_som_type2 = 3; + break; + case 5: + sub_som_type1 = 0; + sub_som_type2 = 2; + break; + case 6: + sub_som_type1 = 1; + sub_som_type2 = 3; + break; + case 7: + sub_som_type1 = 1; + sub_som_type2 = 2; + break; + default: + break; + }; + + printf("SoM: %s-%03u-%s-%03u ", + phytec_som_type_str[sub_som_type1], + api2->som_no, phytec_som_type_str[sub_som_type2], + api2->ksp_no); + } + + printf("Option: %s BOM rev: %s PCB rev: %u%c\n", api2->opt, + api2->bom_rev, api2->pcb_rev, pcb_sub_rev); +} + +char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data) +{ + char *opt; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + opt = data->data.data_api0.opt; + else + opt = data->data.data_api2.opt; + + return opt; +} diff --git a/board/phytec/common/phytec_som_detection.h b/board/phytec/common/phytec_som_detection.h new file mode 100644 index 000000000000..01f7e4652ddb --- /dev/null +++ b/board/phytec/common/phytec_som_detection.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +#ifndef _PHYTEC_SOM_DETECTION_H +#define _PHYTEC_SOM_DETECTION_H + +#define PHYTEC_MAX_OPTIONS 17 +#define PHYTEC_EEPROM_INVAL 0xff + +#define PHYTEC_GET_OPTION(option) \ + (((option) > '9') ? (option) - 'A' + 10 : (option) - '0') + +enum { + PHYTEC_API_REV0 = 0, + PHYTEC_API_REV1, + PHYTEC_API_REV2, +}; + +static const char * const phytec_som_type_str[] = { + "PCM", + "PCL", + "KSM", + "KSP", +}; + +struct phytec_api0_data { + u8 pcb_rev; /* PCB revision of SoM */ + u8 som_type; /* SoM type */ + u8 ksp_no; /* KSP no */ + char opt[16]; /* SoM options */ + u8 mac[6]; /* MAC address (optional) */ + u8 pad[5]; /* padding */ + u8 cksum; /* checksum */ +} __packed; + +struct phytec_api2_data { + u8 pcb_rev; /* PCB revision of SoM */ + u8 pcb_sub_opt_rev; /* PCB subrevision and opt revision */ + u8 som_type; /* SoM type */ + u8 som_no; /* SoM number */ + u8 ksp_no; /* KSP information */ + char opt[PHYTEC_MAX_OPTIONS]; /* SoM options */ + char bom_rev[2]; /* BOM revision */ + u8 mac[6]; /* MAC address (optional) */ + u8 crc8; /* checksum */ +} __packed; + +struct phytec_eeprom_data { + u8 api_rev; + union { + struct phytec_api0_data data_api0; + struct phytec_api2_data data_api2; + } data; +} __packed; + +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) + +int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data, + int bus_num, int addr, + int addr_fallback); +int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, + int bus_num, int addr); +int phytec_eeprom_data_init(struct phytec_eeprom_data *data, + int bus_num, int addr); +void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data); + +char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data); + +#else + +inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data, + int bus_num, int addr, + int addr_fallback) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline int phytec_eeprom_data_init(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data) +{ +} + +inline char *__maybe_unused phytec_get_opt(struct phytec_eeprom_data *data) +{ + return NULL; +} + +#endif /* IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) */ + +#endif /* _PHYTEC_SOM_DETECTION_H */ From patchwork Thu Aug 17 08:57:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 1822207 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=phytec.de header.i=@phytec.de header.a=rsa-sha256 header.s=a4 header.b=ku56yv/W; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RRJmn3xsNz1yNm for ; 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Thu, 17 Aug 2023 10:57:24 +0200 (CEST) Received: from llp-tremmet2.fritz.box (172.25.0.11) by Berlix.phytec.de (172.25.0.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 17 Aug 2023 10:57:23 +0200 From: Teresa Remmet To: Stefano Babic , Fabio Estevam , "NXP i . MX U-Boot Team" CC: , , Yannic Moog , Daniel Schultz , Wadim Egorov Subject: [PATCH v2 2/6] board: phytec: common: Add imx8m specific EEPROM detection support Date: Thu, 17 Aug 2023 10:57:07 +0200 Message-ID: <20230817085711.45339-3-t.remmet@phytec.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230817085711.45339-1-t.remmet@phytec.de> References: <20230817085711.45339-1-t.remmet@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Florix.phytec.de (172.25.0.13) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRmVeSWpSXmKPExsWyRpKBR/fLg7spBhtWMls8vOpv0X7Kx+Lt 3k52iymP17NbdL9Td2D1mDfrBIvHzll32T3O3tnB6NHf3cLqsfHdDqYA1igum5TUnMyy1CJ9 uwSujIcHHzEVLLCu+L15K0sD43WDLkZODgkBE4kVk6cxdzFycQgJLGGSuPHuPCuE84xR4u2M c2wgVWwCGhJPV5xmArFFBMokHvZ+YgaxmQUWM0qs/m0JYgsLREls+tPBDmKzCKhKPFxyC8zm FTCXuPinhxFim7zE/oNnwXo5BSwkmrpvgNUIAdUs6tnFCFEvKHFy5hMWiPnyEs1bZ0PtkpA4 +OIFM0S9vMSuSyfhZk4795oZwg6VOLJpNdMERqFZSEbNQjJqFpJRCxiZVzEK5WYmZ6cWZWbr FWRUlqQm66WkbmIEBb4IA9cOxr45HocYmTgYDzFKcDArifD28N5KEeJNSaysSi3Kjy8qzUkt PsQozcGiJM57v4cpUUggPbEkNTs1tSC1CCbLxMEp1cBYY2zFVMi0p3HDbYco/Solvo2yQYv5 fj46l9Dz6M65+SUcl3JySwzn7DfgOvlWe/7NhZUF/yL7169c1MlZ87ZiJoeAwkOVI2cufXwS eSu3eolP74HYLT/m/dG5KLd94YEZyoL8Ll6iZRtFTzzIvqNcGNh4Z0/vY85zsk6nlOYfbtod vaO1ZK68EktxRqKhFnNRcSIAoRMAPWoCAAA= X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add imx8m specific detection part. Which includes checking the EEPROM data for article number options. Signed-off-by: Teresa Remmet Reviewed-by: Yannic Moog Tested-by: Yannic Moog --- Changes in v2: - remove blank line at EOF - fix string conversion to integer - fix typo s/revsions/revisions --- board/phytec/common/Kconfig | 8 ++ board/phytec/common/Makefile | 1 + board/phytec/common/imx8m_som_detection.c | 168 ++++++++++++++++++++++ board/phytec/common/imx8m_som_detection.h | 54 +++++++ 4 files changed, 231 insertions(+) create mode 100644 board/phytec/common/imx8m_som_detection.c create mode 100644 board/phytec/common/imx8m_som_detection.h diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index d614d45b1d60..3b1c5aa0d02b 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -3,3 +3,11 @@ config PHYTEC_SOM_DETECTION select SPL_CRC8 if SPL help Support of I2C EEPROM based SoM detection. + +config PHYTEC_IMX8M_SOM_DETECTION + bool "Support SoM detection for i.MX8M PHYTEC platforms" + depends on ARCH_IMX8M && PHYTEC_SOM_DETECTION + default y + help + Support of I2C EEPROM based SoM detection. Supported + for PHYTEC i.MX8MM/i.MX8MP boards diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index 5fe8725ef684..fe28964ce21c 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -8,3 +8,4 @@ obj- := __dummy__.o endif obj-$(CONFIG_PHYTEC_SOM_DETECTION) += phytec_som_detection.o +obj-$(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) += imx8m_som_detection.o diff --git a/board/phytec/common/imx8m_som_detection.c b/board/phytec/common/imx8m_som_detection.c new file mode 100644 index 000000000000..c6c96ed19cb3 --- /dev/null +++ b/board/phytec/common/imx8m_som_detection.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +#include +#include +#include +#include +#include +#include + +#include "imx8m_som_detection.h" + +extern struct phytec_eeprom_data eeprom_data; + +/* Check if the SoM is actually one of the following products: + * - i.MX8MM + * - i.MX8MN + * - i.MX8MP + * - i.MX8MQ + * + * Returns 0 in case it's a known SoM. Otherwise, returns -1. + */ +u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data) +{ + char *opt; + u8 som; + + /* We can not do the check for early API revisions */ + if (data->api_rev < PHYTEC_API_REV2) + return -1; + + if (!data) + data = &eeprom_data; + + som = data->data.data_api2.som_no; + debug("%s: som id: %u\n", __func__, som); + + opt = phytec_get_opt(data); + if (!opt) + return -1; + + if (som == PHYTEC_IMX8MP_SOM && is_imx8mp()) + return 0; + + if (som == PHYTEC_IMX8MM_SOM) { + if ((PHYTEC_GET_OPTION(opt[0]) != 0) && + (PHYTEC_GET_OPTION(opt[1]) == 0) && is_imx8mm()) + return 0; + else if ((PHYTEC_GET_OPTION(opt[0]) == 0) && + (PHYTEC_GET_OPTION(opt[1]) != 0) && is_imx8mn()) + return 0; + } + + if (som == PHYTEC_IMX8MQ_SOM && is_imx8mq()) + return 0; + + pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__); + return -1; +} + +/* + * All PHYTEC i.MX8M boards have RAM size definition at the + * same location. + */ +u8 __maybe_unused phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data) +{ + char *opt; + u8 ddr_id; + + if (!data) + data = &eeprom_data; + + opt = phytec_get_opt(data); + if (opt) + ddr_id = PHYTEC_GET_OPTION(opt[2]); + else + ddr_id = PHYTEC_EEPROM_INVAL; + + debug("%s: ddr id: %u\n", __func__, ddr_id); + return ddr_id; +} + +/* + * Filter SPI-NOR flash information. All i.MX8M boards have this at + * the same location. + * returns: 0x0 if no SPI is populated. Otherwise a board depended + * code for the size. PHYTEC_EEPROM_INVAL when the data is invalid. + */ +u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data) +{ + char *opt; + u8 spi; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL; + + opt = phytec_get_opt(data); + if (opt) + spi = PHYTEC_GET_OPTION(opt[4]); + else + spi = PHYTEC_EEPROM_INVAL; + + debug("%s: spi: %u\n", __func__, spi); + return spi; +} + +/* + * Filter ethernet phy information. All i.MX8M boards have this at + * the same location. + * returns: 0x0 if no ethernet phy is populated. 0x1 if it is populated. + * PHYTEC_EEPROM_INVAL when the data is invalid. + */ +u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data) +{ + char *opt; + u8 eth; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL; + + opt = phytec_get_opt(data); + if (opt) { + eth = PHYTEC_GET_OPTION(opt[5]); + eth &= 0x1; + } else { + eth = PHYTEC_EEPROM_INVAL; + } + + debug("%s: eth: %u\n", __func__, eth); + return eth; +} + +/* + * Filter RTC information for phyCORE-i.MX8MP. + * returns: 0 if no RTC is populated. 1 if it is populated. + * PHYTEC_EEPROM_INVAL when the data is invalid. + */ +u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data) +{ + char *opt; + u8 rtc; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL; + + opt = phytec_get_opt(data); + if (opt) { + rtc = PHYTEC_GET_OPTION(opt[5]); + rtc &= 0x4; + rtc = !(rtc >> 2); + } else { + rtc = PHYTEC_EEPROM_INVAL; + } + debug("%s: rtc: %u\n", __func__, rtc); + return rtc; +} diff --git a/board/phytec/common/imx8m_som_detection.h b/board/phytec/common/imx8m_som_detection.h new file mode 100644 index 000000000000..88d3037bf363 --- /dev/null +++ b/board/phytec/common/imx8m_som_detection.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +#ifndef _PHYTEC_IMX8M_SOM_DETECTION_H +#define _PHYTEC_IMX8M_SOM_DETECTION_H + +#include "phytec_som_detection.h" + +#define PHYTEC_IMX8MQ_SOM 66 +#define PHYTEC_IMX8MM_SOM 69 +#define PHYTEC_IMX8MP_SOM 70 + +#if IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) + +u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data); + +#else + +inline u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data) +{ + return -1; +} + +inline u8 __maybe_unused +phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) */ + +#endif /* _PHYTEC_IMX8M_SOM_DETECTION_H */ From patchwork Thu Aug 17 08:57:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 1822208 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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MX U-Boot Team" CC: , , Yannic Moog , Daniel Schultz , Wadim Egorov Subject: [PATCH v2 3/6] board: phytec: phycore-imx8mp: Add EEPROM detection initialisation Date: Thu, 17 Aug 2023 10:57:08 +0200 Message-ID: <20230817085711.45339-4-t.remmet@phytec.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230817085711.45339-1-t.remmet@phytec.de> References: <20230817085711.45339-1-t.remmet@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Florix.phytec.de (172.25.0.13) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKLMWRmVeSWpSXmKPExsWyRpKBR/fLg7spBkvXiVs8vOpv0X7Kx+Lt 3k52iymP17NbdL9Td2D1mDfrBIvHzll32T3O3tnB6NHf3cLqsfHdDqYA1igum5TUnMyy1CJ9 uwSujN6Gp6wFUwUrrj/yamC8ztfFyMEhIWAicelFXRcjF4eQwBImiY+t/xkhnGeMEm9nnGPr YuTkYBPQkHi64jQTiC0iUCbxsPcTM4jNLLCYUWL1b0sQW1ggSuLu9C8sIDaLgKrEutubGEFs XgFzibndB9lBbAkBeYn9B8+C9XIKWEg0dd8AiwsB1Szq2QVVLyhxcuYTFoj58hLNW2dD7ZKQ OPjiBTNEvbzErksnGWFmTjv3mhnCDpU4smk10wRGoVlIRs1CMmoWklELGJlXMQrlZiZnpxZl ZusVZFSWpCbrpaRuYgQFvQgD1w7GvjkehxiZOBgPMUpwMCuJ8Pbw3koR4k1JrKxKLcqPLyrN SS0+xCjNwaIkznu/hylRSCA9sSQ1OzW1ILUIJsvEwSnVwMiSslhkudFyo9YrIlan1RbuD97O LSIW/Hm540VrRv+e/Oa5VjOnPw28+MqYMaCq0TdDVfbzo95/Z855bp76UU0+qo7xlkfFruVX mxXrYurtdrbFLpp75kGEErd7xgLvF04rSpsn1e2/+Pxl4Lft6xad1/zimL8s7zvv0463J5un zDLlydquulmJpTgj0VCLuag4EQAhqfc8aAIAAA== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add EEPROM detection initialisation for phyCORE-i.MX8MM and print SoM information during boot when successful. Signed-off-by: Teresa Remmet Reviewed-by: Yannic Moog Tested-by: Yannic Moog --- Changes in v2: - removed superfluous goto --- board/phytec/phycore_imx8mp/Kconfig | 1 + board/phytec/phycore_imx8mp/spl.c | 17 +++++++++++++++++ configs/phycore-imx8mp_defconfig | 1 + 3 files changed, 19 insertions(+) diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig index c053a46fc9d1..f846d10bad9e 100644 --- a/board/phytec/phycore_imx8mp/Kconfig +++ b/board/phytec/phycore_imx8mp/Kconfig @@ -12,4 +12,5 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg" +source "board/phytec/common/Kconfig" endif diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index faed6fc3b76d..49406f2eafad 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -21,8 +21,13 @@ #include #include +#include "../common/imx8m_som_detection.h" + DECLARE_GLOBAL_DATA_PTR; +#define EEPROM_ADDR 0x51 +#define EEPROM_ADDR_FALLBACK 0x59 + int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; @@ -30,6 +35,18 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) void spl_dram_init(void) { + int ret; + + ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR, + EEPROM_ADDR_FALLBACK); + if (ret) + goto out; + + ret = phytec_imx8m_detect(NULL); + if (!ret) + phytec_print_som_info(NULL); + +out: ddr_init(&dram_timing); } diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 7bf404be860b..7937e15e6422 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -12,6 +12,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_PHYCORE_IMX8MP=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y From patchwork Thu Aug 17 08:57:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 1822209 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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MX U-Boot Team" CC: , , Yannic Moog , Daniel Schultz , Wadim Egorov Subject: [PATCH v2 4/6] board: phytec: phycore_imx8mp: Update 2GB RAM Timings Date: Thu, 17 Aug 2023 10:57:09 +0200 Message-ID: <20230817085711.45339-5-t.remmet@phytec.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230817085711.45339-1-t.remmet@phytec.de> References: <20230817085711.45339-1-t.remmet@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Florix.phytec.de (172.25.0.13) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRmVeSWpSXmKPExsWyRpKBR/fLg7spBg9+aVs8vOpv0X7Kx+Lt 3k52iymP17NbdL9Td2D1mDfrBIvHzll32T3O3tnB6NHf3cLqsfHdDqYA1igum5TUnMyy1CJ9 uwSujKONagWNORV3Tx1nbmBcENjFyMkhIWAisebVN+YuRi4OIYElTBJdK/ayQjjPGCX6ZjSw g1SxCWhIPF1xmgnEFhEok3jY+4kZxGYWWMwosfq3JYgtLOArcXfNG0YQm0VAVeLSjQcsIDav gLnE190bGCG2yUvsP3gWrJdTwEKiqfsG2HwhoJpFPbsYIeoFJU7OfMICMV9eonnrbKhdEhIH X7xghqiXl9h16STczGnnXjND2KESRzatZprAKDQLyahZSEbNQjJqASPzKkah3Mzk7NSizGy9 gozKktRkvZTUTYygsBdh4NrB2DfH4xAjEwfjIUYJDmYlEd4e3lspQrwpiZVVqUX58UWlOanF hxilOViUxHnv9zAlCgmkJ5akZqemFqQWwWSZODilGhgVaz+UZP9iP9YYk2WY2yZuzx3YqbdK tDM4izvnOpvfv1pfgzXdJr9+LxNpWhyr6ZF41v/NrtVnP5d3KmrlJh07Ea7z7oPLxnWXrd1a /+eYbbXWYm8zOxV53T34z+a+aKt7l45y7tL4eai9salyY5PztEgOBy/pL/139qZdKfVUPPPZ e53uNCWW4oxEQy3mouJEAACB+DhpAgAA X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Due to PCB layout constraints in PCB revisions until including 1549.2, a RAM frequency of 2 GHz can cause rare instabilities. Set the RAM frequency to 1.5 GHz to achieve a stable system under all conditions. Signed-off-by: Teresa Remmet Reviewed-by: Yannic Moog Tested-by: Yannic Moog --- Changes in v2: - none --- board/phytec/phycore_imx8mp/lpddr4_timing.c | 278 ++++++++++---------- 1 file changed, 135 insertions(+), 143 deletions(-) diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.c b/board/phytec/phycore_imx8mp/lpddr4_timing.c index e59dd74377cb..f2707b859606 100644 --- a/board/phytec/phycore_imx8mp/lpddr4_timing.c +++ b/board/phytec/phycore_imx8mp/lpddr4_timing.c @@ -13,63 +13,68 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x323 }, - { 0x3d400024, 0x1e84800 }, - { 0x3d400064, 0x7a0118 }, - { 0x3d4000d0, 0xc00307a3 }, - { 0x3d4000d4, 0xc50000 }, - { 0x3d4000dc, 0xf4003f }, - { 0x3d4000e0, 0x330000 }, + { 0x3d400020, 0x1223 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0xf10000 }, { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x2028222a }, - { 0x3d400104, 0x807bf }, - { 0x3d40010c, 0xe0e000 }, - { 0x3d400110, 0x12040a12 }, - { 0x3d400114, 0x2050f0f }, - { 0x3d400118, 0x1010009 }, - { 0x3d40011c, 0x501 }, - { 0x3d400130, 0x20800 }, - { 0x3d400134, 0xe100002 }, - { 0x3d400138, 0x120 }, - { 0x3d400144, 0xc80064 }, - { 0x3d400180, 0x3e8001e }, - { 0x3d400184, 0x3207a12 }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, { 0x3d400188, 0x0 }, - { 0x3d400190, 0x49f820e }, + { 0x3d400190, 0x49b820a }, { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x1f0e }, + { 0x3d4001b4, 0x1b0a }, { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x1 }, + { 0x3d4001c0, 0x7 }, { 0x3d4001c4, 0x1 }, { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x9121c1c }, + { 0x3d400108, 0x7101817 }, { 0x3d400200, 0x1f }, + { 0x3d400208, 0x0 }, { 0x3d40020c, 0x0 }, { 0x3d400210, 0x1f1f }, { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x7070707 }, - { 0x3d40021c, 0xf07 }, - { 0x3d400250, 0x1f05 }, - { 0x3d400254, 0x1f }, - { 0x3d400264, 0x90003ff }, - { 0x3d40026c, 0x20003ff }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, { 0x3d400408, 0x72ff }, - { 0x3d400494, 0x1000e00 }, - { 0x3d400498, 0x3ff0000 }, - { 0x3d40049c, 0x1000e00 }, - { 0x3d4004a0, 0x3ff0000 }, - { 0x3d402020, 0x21 }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, { 0x3d402024, 0x30d400 }, - { 0x3d402050, 0x20d040 }, + { 0x3d402050, 0x20d000 }, { 0x3d402064, 0xc001c }, { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x330000 }, + { 0x3d4020e0, 0xf30000 }, { 0x3d4020e8, 0x660048 }, { 0x3d4020ec, 0x160048 }, { 0x3d402100, 0xa040305 }, @@ -89,12 +94,12 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x21 }, + { 0x3d403020, 0x1021 }, { 0x3d403024, 0xc3500 }, - { 0x3d403050, 0x20d040 }, + { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x30007 }, { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x330000 }, + { 0x3d4030e0, 0xf30000 }, { 0x3d4030e8, 0x660048 }, { 0x3d4030ec, 0x160048 }, { 0x3d403100, 0xa010102 }, @@ -137,12 +142,12 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x110a7, 0x6 }, { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, - { 0x120a2, 0x3 }, - { 0x120a3, 0x2 }, - { 0x120a4, 0x5 }, - { 0x120a5, 0x4 }, - { 0x120a6, 0x7 }, - { 0x120a7, 0x6 }, + { 0x120a2, 0x2 }, + { 0x120a3, 0x3 }, + { 0x120a4, 0x4 }, + { 0x120a5, 0x5 }, + { 0x120a6, 0x6 }, + { 0x120a7, 0x7 }, { 0x130a0, 0x0 }, { 0x130a1, 0x1 }, { 0x130a2, 0x2 }, @@ -185,7 +190,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x7055, 0x1ff }, { 0x8055, 0x1ff }, { 0x9055, 0x1ff }, - { 0x200c5, 0x18 }, + { 0x200c5, 0x19 }, { 0x1200c5, 0x7 }, { 0x2200c5, 0x7 }, { 0x2002e, 0x2 }, @@ -194,11 +199,11 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x90204, 0x0 }, { 0x190204, 0x0 }, { 0x290204, 0x0 }, - { 0x20024, 0x1e3 }, + { 0x20024, 0x1a3 }, { 0x2003a, 0x2 }, - { 0x120024, 0x1e3 }, + { 0x120024, 0x1a3 }, { 0x2003a, 0x2 }, - { 0x220024, 0x1e3 }, + { 0x220024, 0x1a3 }, { 0x2003a, 0x2 }, { 0x20056, 0x3 }, { 0x120056, 0x3 }, @@ -264,7 +269,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, - { 0x20008, 0x3e8 }, + { 0x20008, 0x2ee }, { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, @@ -310,19 +315,15 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x200f6, 0x0 }, { 0x200f7, 0xf000 }, { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, + { 0x2002d, 0x1 }, + { 0x12002d, 0x1 }, + { 0x22002d, 0x1 }, { 0x2007d, 0x212 }, { 0x12007d, 0x212 }, { 0x22007d, 0x212 }, { 0x2007c, 0x61 }, { 0x12007c, 0x61 }, { 0x22007c, 0x61 }, - { 0x1004a, 0x500 }, - { 0x1104a, 0x500 }, - { 0x1204a, 0x500 }, - { 0x1304a, 0x500 }, { 0x2002c, 0x0 }, }; @@ -1052,7 +1053,7 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { /* P0 message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xfa0 }, + { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1061,26 +1062,26 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x5400b, 0x2 }, { 0x5400f, 0x100 }, { 0x54012, 0x110 }, - { 0x54019, 0x3ff4 }, - { 0x5401a, 0x33 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0xf1 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x3ff4 }, - { 0x54020, 0x33 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0xf1 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xf400 }, - { 0x54033, 0x333f }, + { 0x54032, 0xd400 }, + { 0x54033, 0xf12d }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xf400 }, - { 0x54039, 0x333f }, + { 0x54038, 0xd400 }, + { 0x54039, 0xf12d }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1102,25 +1103,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x5400f, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, + { 0x54033, 0xf300 }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, + { 0x54039, 0xf300 }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1142,25 +1143,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { { 0x5400f, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, + { 0x54033, 0xf300 }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, + { 0x54039, 0xf300 }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1171,37 +1172,36 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { /* P0 2D message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xfa0 }, + { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, { 0x54008, 0x61 }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x110 }, - { 0x54019, 0x3ff4 }, - { 0x5401a, 0x33 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0xf1 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x3ff4 }, - { 0x54020, 0x33 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0xf1 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xf400 }, - { 0x54033, 0x333f }, + { 0x54032, 0xd400 }, + { 0x54033, 0xf12d }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xf400 }, - { 0x54039, 0x333f }, + { 0x54038, 0xd400 }, + { 0x54039, 0xf12d }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1629,67 +1629,58 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x90155, 0x20 }, { 0x90156, 0x2aa }, { 0x90157, 0x9 }, - { 0x90158, 0x0 }, - { 0x90159, 0x400 }, - { 0x9015a, 0x10e }, - { 0x9015b, 0x8 }, - { 0x9015c, 0xe8 }, - { 0x9015d, 0x109 }, - { 0x9015e, 0x0 }, - { 0x9015f, 0x8140 }, - { 0x90160, 0x10c }, - { 0x90161, 0x10 }, - { 0x90162, 0x8138 }, - { 0x90163, 0x10c }, - { 0x90164, 0x8 }, - { 0x90165, 0x7c8 }, - { 0x90166, 0x101 }, - { 0x90167, 0x8 }, - { 0x90168, 0x448 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, { 0x90169, 0x109 }, - { 0x9016a, 0xf }, - { 0x9016b, 0x7c0 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, { 0x9016c, 0x109 }, - { 0x9016d, 0x0 }, - { 0x9016e, 0xe8 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, { 0x9016f, 0x109 }, - { 0x90170, 0x47 }, - { 0x90171, 0x630 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, { 0x90172, 0x109 }, - { 0x90173, 0x8 }, - { 0x90174, 0x618 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, { 0x90175, 0x109 }, { 0x90176, 0x8 }, - { 0x90177, 0xe0 }, - { 0x90178, 0x109 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, { 0x90179, 0x0 }, - { 0x9017a, 0x7c8 }, + { 0x9017a, 0x478 }, { 0x9017b, 0x109 }, - { 0x9017c, 0x8 }, - { 0x9017d, 0x8140 }, - { 0x9017e, 0x10c }, - { 0x9017f, 0x0 }, - { 0x90180, 0x478 }, - { 0x90181, 0x109 }, - { 0x90182, 0x0 }, - { 0x90183, 0x1 }, - { 0x90184, 0x8 }, - { 0x90185, 0x8 }, - { 0x90186, 0x4 }, - { 0x90187, 0x8 }, - { 0x90188, 0x8 }, - { 0x90189, 0x7c8 }, - { 0x9018a, 0x101 }, - { 0x90006, 0x0 }, - { 0x90007, 0x0 }, - { 0x90008, 0x8 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, { 0x90009, 0x0 }, - { 0x9000a, 0x0 }, - { 0x9000b, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, { 0x9001f, 0x29 }, - { 0x90026, 0x6a }, + { 0x90026, 0x68 }, { 0x400d0, 0x0 }, { 0x400d1, 0x101 }, { 0x400d2, 0x105 }, @@ -1699,15 +1690,16 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x400d6, 0x20a }, { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, - { 0x2000b, 0x7d }, - { 0x2000c, 0xfa }, - { 0x2000d, 0x9c4 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x34b }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, { 0x2000e, 0x2c }, - { 0x12000b, 0xc }, + { 0x12000b, 0x70 }, { 0x12000c, 0x19 }, { 0x12000d, 0xfa }, { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, + { 0x22000b, 0x1c }, { 0x22000c, 0x6 }, { 0x22000d, 0x3e }, { 0x22000e, 0x10 }, @@ -1804,8 +1796,8 @@ static struct dram_cfg_param ddr_phy_pie[] = { static struct dram_fsp_msg ddr_dram_fsp_msg[] = { { - /* P0 4000mts 1D */ - .drate = 4000, + /* P0 3000mts 1D */ + .drate = 3000, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), @@ -1825,8 +1817,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), }, { - /* P0 4000mts 2D */ - .drate = 4000, + /* P0 3000mts 2D */ + .drate = 3000, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), @@ -1845,5 +1837,5 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 4000, 400, 100, }, + .fsp_table = { 3000, 400, 100, }, }; From patchwork Thu Aug 17 08:57:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 1822211 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=phytec.de header.i=@phytec.de header.a=rsa-sha256 header.s=a4 header.b=Q042DwdM; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RRJnl6vJLz1yNm for ; Thu, 17 Aug 2023 18:58:33 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1F0E586ABD; Thu, 17 Aug 2023 10:57:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=phytec.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=phytec.de header.i=@phytec.de header.b="Q042DwdM"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 15BB486AA8; Thu, 17 Aug 2023 10:57:32 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mickerik.phytec.de (mickerik.phytec.de [91.26.50.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 319A986AAF for ; Thu, 17 Aug 2023 10:57:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=phytec.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=T.Remmet@phytec.de DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1692262645; x=1694854645; h=From:Sender:Reply-To:Subject:Date:Message-ID:To:CC:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=ZV2Xl69Co0z53VIb1tQVF8a/9CkFNhnmfsEofu/ZyIs=; b=Q042DwdMiOwR9k7d0dzaPkYoIi8Qmm5aKC+csyNLsdVGqhpj7v/tL1n8v5gAWL3Y wnTJ3oWDU9ISbTZgasAnjvXO6kK852W+poMqc7+N/meY4F2URA5dJqooeg64vrzx nWpLGfukf/1JJvOM1Ykb2mwn+9ztUbpi6pG8vKVSReg=; X-AuditID: ac14000a-923ff70000007ecb-b6-64dde0f54ea9 Received: from berlix.phytec.de (Unknown_Domain [172.25.0.12]) (using TLS with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client did not present a certificate) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 15.D2.32459.5F0EDD46; Thu, 17 Aug 2023 10:57:25 +0200 (CEST) Received: from llp-tremmet2.fritz.box (172.25.0.11) by Berlix.phytec.de (172.25.0.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 17 Aug 2023 10:57:24 +0200 From: Teresa Remmet To: Stefano Babic , Fabio Estevam , "NXP i . MX U-Boot Team" CC: , , Yannic Moog , Daniel Schultz , Wadim Egorov Subject: [PATCH v2 5/6] board: phytec: common: phytec_som_detection: Add helper for PCB revision Date: Thu, 17 Aug 2023 10:57:10 +0200 Message-ID: <20230817085711.45339-6-t.remmet@phytec.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230817085711.45339-1-t.remmet@phytec.de> References: <20230817085711.45339-1-t.remmet@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Florix.phytec.de (172.25.0.13) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRmVeSWpSXmKPExsWyRpKBR/frg7spBpfXslo8vOpv0X7Kx+Lt 3k52iymP17NbdL9Td2D1mDfrBIvHzll32T3O3tnB6NHf3cLqsfHdDqYA1igum5TUnMyy1CJ9 uwSujMNdbxkLTvBVHDvzkLmB8TBPFyMnh4SAiUTD7RvsXYxcHEICS5gkDjycxwzhPGOU6JvR wA5SxSagIfF0xWkmEFtEoEziYe8nZhCbWWAxo8Tq35YgtrBAgsS2o3eA6jk4WARUJR7+8gMJ 8wqYS9zcDFEuISAvsf/gWTCbU8BCoqn7Bth4IaCaRT27GCHqBSVOznzCAjFeXqJ562yoVRIS B1+8YIaol5fYdekkI8zMaedeQ80PlTiyaTXTBEahWUhGzUIyahaSUQsYmVcxCuVmJmenFmVm 6xVkVJakJuulpG5iBIW9CAPXDsa+OR6HGJk4GA8xSnAwK4nw9vDeShHiTUmsrEotyo8vKs1J LT7EKM3BoiTOe7+HKVFIID2xJDU7NbUgtQgmy8TBKdXAmJV1/Scrq130yVnvWhV/eL5qNw3O aCxtXhm4xmJby7zCtt2LWSV6clK+5VrP0eK7NEP/bYjcxNVG1989YZgy5+6ZQMe7e4LW1NtE tLMatXKcjvoj1mu2w2vnCR4jXueFyR55ryw+Hcn+eDQwoqKCJ9rlt0ozR8L61K49Z+YE7G/V bThwrmuNEktxRqKhFnNRcSIAmOTmC2kCAAA= X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add helper function to read out the PCB revision of a PHYTEC SoM. Signed-off-by: Teresa Remmet Reviewed-by: Yannic Moog Tested-by: Yannic Moog --- Changes in v2: - none --- board/phytec/common/phytec_som_detection.c | 15 +++++++++++++++ board/phytec/common/phytec_som_detection.h | 5 +++++ 2 files changed, 20 insertions(+) diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index 366bdd4ace4b..55562731270b 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -186,3 +186,18 @@ char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data) return opt; } + +u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data) +{ + struct phytec_api2_data *api2; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL; + + api2 = &data->data.data_api2; + + return api2->pcb_rev; +} diff --git a/board/phytec/common/phytec_som_detection.h b/board/phytec/common/phytec_som_detection.h index 01f7e4652ddb..c68e2302cc42 100644 --- a/board/phytec/common/phytec_som_detection.h +++ b/board/phytec/common/phytec_som_detection.h @@ -68,6 +68,7 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data, void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data); char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data); #else @@ -99,6 +100,10 @@ inline char *__maybe_unused phytec_get_opt(struct phytec_eeprom_data *data) return NULL; } +u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} #endif /* IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) */ #endif /* _PHYTEC_SOM_DETECTION_H */ From patchwork Thu Aug 17 08:57:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 1822210 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=phytec.de header.i=@phytec.de header.a=rsa-sha256 header.s=a4 header.b=Lyzg2Wwb; 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Thu, 17 Aug 2023 10:57:24 +0200 From: Teresa Remmet To: Stefano Babic , Fabio Estevam , "NXP i . MX U-Boot Team" CC: , , Yannic Moog , Daniel Schultz , Wadim Egorov Subject: [PATCH v2 6/6] board: phytec: phycore_imx8mp: Add 4000MTS RAM timings based on PCB rev Date: Thu, 17 Aug 2023 10:57:11 +0200 Message-ID: <20230817085711.45339-7-t.remmet@phytec.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230817085711.45339-1-t.remmet@phytec.de> References: <20230817085711.45339-1-t.remmet@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Florix.phytec.de (172.25.0.13) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRmVeSWpSXmKPExsWyRpKBR/frg7spBp/nilk8vOpv0X7Kx+Lt 3k52iymP17NbdL9Td2D1mDfrBIvHzll32T3O3tnB6NHf3cLqsfHdDqYA1igum5TUnMyy1CJ9 uwSujA2/NrAXnJeuOPjiLXsD40PxLkZODgkBE4nZ5yaxdjFycQgJLGGSuNF9Acp5xijRN6OB HaSKTUBD4umK00wgtohAmcTD3k/MIDazwGJGidW/LUFsYYF4ifvvZrGC2CwCqhI/1k4Bq+EV MJf4sucpM8Q2eYn9B8+C2ZwCFhJN3TfA5gsB1Szq2cUIUS8ocXLmExaI+fISzVtnQ+2SkDj4 4gUzRL28xK5LJxlhZk479xpqfqjEkU2rmSYwCs1CMmoWklGzkIxawMi8ilEoNzM5O7UoM1uv IKOyJDVZLyV1EyMo8EUYuHYw9s3xOMTIxMF4iFGCg1lJhLeH91aKEG9KYmVValF+fFFpTmrx IUZpDhYlcd77PUyJQgLpiSWp2ampBalFMFkmDk6pBsb4hbW9Tp3MiovtObuWN/o7P47KrKw8 I6T5YJqwZIj1HYmLW7OTJnUfOTXj/zSzRAbPP6v875ZvjLDtcWN+P0fiSNbeiyGs3/LWMb3R ryj0+Li+Tahz0oT5ri7SaYWbbh0PknfuYDzUwxH0cN2hINacF5r6+WyrDcT99J/us7Bcau5X dfpCthJLcUaioRZzUXEiAGL7SZBqAgAA X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Starting with PCB revision 3 we can safely make use of higher RAM frequency again. Make use of the EEPROM detection to determine the revision and use the updated RAM timings for new SoMs. Signed-off-by: Teresa Remmet Reviewed-by: Yannic Moog Tested-by: Yannic Moog --- Changes in v2: - Fix wrong RAM Timing values as pointed out by Yannic --- board/phytec/phycore_imx8mp/spl.c | 61 +++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 49406f2eafad..d38f6368fe36 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -46,6 +46,67 @@ void spl_dram_init(void) if (!ret) phytec_print_som_info(NULL); + ret = phytec_get_rev(NULL); + if (ret >= 3 && ret != PHYTEC_EEPROM_INVAL) { + dram_timing.ddrc_cfg[3].val = 0x1323; + dram_timing.ddrc_cfg[4].val = 0x1e84800; + dram_timing.ddrc_cfg[5].val = 0x7a0118; + dram_timing.ddrc_cfg[8].val = 0xc00307a3; + dram_timing.ddrc_cfg[9].val = 0xc50000; + dram_timing.ddrc_cfg[10].val = 0xf4003f; + dram_timing.ddrc_cfg[11].val = 0xf30000; + dram_timing.ddrc_cfg[14].val = 0x2028222a; + dram_timing.ddrc_cfg[15].val = 0x8083f; + dram_timing.ddrc_cfg[16].val = 0xe0e000; + dram_timing.ddrc_cfg[17].val = 0x12040a12; + dram_timing.ddrc_cfg[18].val = 0x2050f0f; + dram_timing.ddrc_cfg[19].val = 0x1010009; + dram_timing.ddrc_cfg[20].val = 0x502; + dram_timing.ddrc_cfg[21].val = 0x20800; + dram_timing.ddrc_cfg[22].val = 0xe100002; + dram_timing.ddrc_cfg[23].val = 0x120; + dram_timing.ddrc_cfg[24].val = 0xc80064; + dram_timing.ddrc_cfg[25].val = 0x3e8001e; + dram_timing.ddrc_cfg[26].val = 0x3207a12; + dram_timing.ddrc_cfg[28].val = 0x4a3820e; + dram_timing.ddrc_cfg[30].val = 0x230e; + dram_timing.ddrc_cfg[37].val = 0x799; + dram_timing.ddrc_cfg[38].val = 0x9141d1c; + dram_timing.ddrc_cfg[74].val = 0x302; + dram_timing.ddrc_cfg[83].val = 0x599; + dram_timing.ddrc_cfg[99].val = 0x302; + dram_timing.ddrc_cfg[108].val = 0x599; + dram_timing.ddrphy_cfg[66].val = 0x18; + dram_timing.ddrphy_cfg[75].val = 0x1e3; + dram_timing.ddrphy_cfg[77].val = 0x1e3; + dram_timing.ddrphy_cfg[79].val = 0x1e3; + dram_timing.ddrphy_cfg[145].val = 0x3e8; + dram_timing.fsp_msg[0].drate = 4000; + dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0; + dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f; + dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f; + dram_timing.fsp_msg[3].drate = 4000; + dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0; + dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f; + dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f; + dram_timing.ddrphy_pie[480].val = 0x465; + dram_timing.ddrphy_pie[481].val = 0xfa; + dram_timing.ddrphy_pie[482].val = 0x9c4; + dram_timing.fsp_table[0] = 4000; + } + out: ddr_init(&dram_timing); }