From patchwork Tue Aug 8 04:08:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiongfeng Wang X-Patchwork-Id: 1818947 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RL3gJ6kFHz1yYl for ; Wed, 9 Aug 2023 05:49:48 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229463AbjHHTtp (ORCPT ); Tue, 8 Aug 2023 15:49:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231527AbjHHTt0 (ORCPT ); Tue, 8 Aug 2023 15:49:26 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94EE4504C8 for ; Tue, 8 Aug 2023 09:54:32 -0700 (PDT) Received: from dggpemm500002.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4RKfRj2C9cztRsG; Tue, 8 Aug 2023 11:53:21 +0800 (CST) Received: from localhost.localdomain.localdomain (10.175.113.25) by dggpemm500002.china.huawei.com (7.185.36.229) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 8 Aug 2023 11:56:48 +0800 From: Xiongfeng Wang To: , , , , , , , , CC: , , , , , , Subject: [PATCH v2 1/2] PCI: Add pci_find_next_dvsec_capability to find next Designated VSEC Date: Tue, 8 Aug 2023 12:08:57 +0800 Message-ID: <20230808040858.183568-2-wangxiongfeng2@huawei.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230808040858.183568-1-wangxiongfeng2@huawei.com> References: <20230808040858.183568-1-wangxiongfeng2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.113.25] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggpemm500002.china.huawei.com (7.185.36.229) X-CFilter-Loop: Reflected X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Some devices may have several DVSEC (Designated Vendor-Specific Extended Capability) entries with the same DVSEC ID. Add pci_find_next_dvsec_capability() to find them all. Signed-off-by: Xiongfeng Wang Reviewed-by: Andrew Donnellan Acked-by: Bjorn Helgaas --- drivers/pci/pci.c | 39 ++++++++++++++++++++++++++------------- include/linux/pci.h | 2 ++ 2 files changed, 28 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 60230da957e0..2ff5b1ce0eec 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -749,35 +749,48 @@ u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap) EXPORT_SYMBOL_GPL(pci_find_vsec_capability); /** - * pci_find_dvsec_capability - Find DVSEC for vendor + * pci_find_next_dvsec_capability - Find next DVSEC for vendor * @dev: PCI device to query + * @start: Address at which to start looking (0 to start at beginning of list) * @vendor: Vendor ID to match for the DVSEC - * @dvsec: Designated Vendor-specific capability ID + * @dvsec: Vendor-defined DVSEC ID * - * If DVSEC has Vendor ID @vendor and DVSEC ID @dvsec return the capability - * offset in config space; otherwise return 0. + * Returns the address of the next DVSEC if the DVSEC has Vendor ID @vendor and + * DVSEC ID @dvsec; otherwise return 0. DVSEC can occur several times with the + * same DVSEC ID for some devices, and this provides a way to find them all. */ -u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec) +u16 pci_find_next_dvsec_capability(struct pci_dev *dev, u16 start, u16 vendor, + u16 dvsec) { - int pos; + u16 pos = start; - pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DVSEC); - if (!pos) - return 0; - - while (pos) { + while ((pos = pci_find_next_ext_capability(dev, pos, + PCI_EXT_CAP_ID_DVSEC))) { u16 v, id; pci_read_config_word(dev, pos + PCI_DVSEC_HEADER1, &v); pci_read_config_word(dev, pos + PCI_DVSEC_HEADER2, &id); if (vendor == v && dvsec == id) return pos; - - pos = pci_find_next_ext_capability(dev, pos, PCI_EXT_CAP_ID_DVSEC); } return 0; } +EXPORT_SYMBOL_GPL(pci_find_next_dvsec_capability); + +/** + * pci_find_dvsec_capability - Find DVSEC for vendor + * @dev: PCI device to query + * @vendor: Vendor ID to match for the DVSEC + * @dvsec: Vendor-defined DVSEC ID + * + * If DVSEC has Vendor ID @vendor and DVSEC ID @dvsec return the capability + * offset in config space; otherwise return 0. + */ +u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec) +{ + return pci_find_next_dvsec_capability(dev, 0, vendor, dvsec); +} EXPORT_SYMBOL_GPL(pci_find_dvsec_capability); /** diff --git a/include/linux/pci.h b/include/linux/pci.h index c69a2cc1f412..82bb905daf72 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1168,6 +1168,8 @@ u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); struct pci_bus *pci_find_next_bus(const struct pci_bus *from); u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); +u16 pci_find_next_dvsec_capability(struct pci_dev *dev, u16 start, u16 vendor, + u16 dvsec); u64 pci_get_dsn(struct pci_dev *dev); From patchwork Tue Aug 8 04:08:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiongfeng Wang X-Patchwork-Id: 1819046 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RL6kw74Bdz1yfB for ; Wed, 9 Aug 2023 08:08:08 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231712AbjHHWIG (ORCPT ); Tue, 8 Aug 2023 18:08:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231933AbjHHWID (ORCPT ); Tue, 8 Aug 2023 18:08:03 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5924512D97D for ; Tue, 8 Aug 2023 09:54:31 -0700 (PDT) Received: from dggpemm500002.china.huawei.com (unknown [172.30.72.55]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4RKfRk0NhDztRwp; Tue, 8 Aug 2023 11:53:22 +0800 (CST) Received: from localhost.localdomain.localdomain (10.175.113.25) by dggpemm500002.china.huawei.com (7.185.36.229) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 8 Aug 2023 11:56:49 +0800 From: Xiongfeng Wang To: , , , , , , , , CC: , , , , , , Subject: [PATCH v2 2/2] ocxl: use pci_find_next_dvsec_capability() to simplify the code Date: Tue, 8 Aug 2023 12:08:58 +0800 Message-ID: <20230808040858.183568-3-wangxiongfeng2@huawei.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230808040858.183568-1-wangxiongfeng2@huawei.com> References: <20230808040858.183568-1-wangxiongfeng2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.113.25] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggpemm500002.china.huawei.com (7.185.36.229) X-CFilter-Loop: Reflected X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org PCI core add pci_find_next_dvsec_capability() to query the next DVSEC. We can use that core API to simplify the code. Also remove the unused macros. Signed-off-by: Xiongfeng Wang Reviewed-by: Andrew Donnellan --- arch/powerpc/platforms/powernv/ocxl.c | 20 ++------------------ drivers/misc/ocxl/config.c | 21 ++++++--------------- include/misc/ocxl-config.h | 4 ---- 3 files changed, 8 insertions(+), 37 deletions(-) diff --git a/arch/powerpc/platforms/powernv/ocxl.c b/arch/powerpc/platforms/powernv/ocxl.c index 629067781cec..8dbc1a9535fc 100644 --- a/arch/powerpc/platforms/powernv/ocxl.c +++ b/arch/powerpc/platforms/powernv/ocxl.c @@ -71,29 +71,13 @@ static DEFINE_MUTEX(links_list_lock); * the AFUs, by pro-rating if needed. */ -static int find_dvsec_from_pos(struct pci_dev *dev, int dvsec_id, int pos) -{ - int vsec = pos; - u16 vendor, id; - - while ((vsec = pci_find_next_ext_capability(dev, vsec, - OCXL_EXT_CAP_ID_DVSEC))) { - pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET, - &vendor); - pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id); - if (vendor == PCI_VENDOR_ID_IBM && id == dvsec_id) - return vsec; - } - return 0; -} - static int find_dvsec_afu_ctrl(struct pci_dev *dev, u8 afu_idx) { int vsec = 0; u8 idx; - while ((vsec = find_dvsec_from_pos(dev, OCXL_DVSEC_AFU_CTRL_ID, - vsec))) { + while ((vsec = pci_find_next_dvsec_capability(dev, vsec, + PCI_VENDOR_ID_IBM, OCXL_DVSEC_AFU_CTRL_ID))) { pci_read_config_byte(dev, vsec + OCXL_DVSEC_AFU_CTRL_AFU_IDX, &idx); if (idx == afu_idx) diff --git a/drivers/misc/ocxl/config.c b/drivers/misc/ocxl/config.c index 92ab49705f64..6c0fca32e6db 100644 --- a/drivers/misc/ocxl/config.c +++ b/drivers/misc/ocxl/config.c @@ -39,23 +39,14 @@ static int find_dvsec(struct pci_dev *dev, int dvsec_id) static int find_dvsec_afu_ctrl(struct pci_dev *dev, u8 afu_idx) { int vsec = 0; - u16 vendor, id; u8 idx; - while ((vsec = pci_find_next_ext_capability(dev, vsec, - OCXL_EXT_CAP_ID_DVSEC))) { - pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET, - &vendor); - pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id); - - if (vendor == PCI_VENDOR_ID_IBM && - id == OCXL_DVSEC_AFU_CTRL_ID) { - pci_read_config_byte(dev, - vsec + OCXL_DVSEC_AFU_CTRL_AFU_IDX, - &idx); - if (idx == afu_idx) - return vsec; - } + while ((vsec = pci_find_next_dvsec_capability(dev, vsec, + PCI_VENDOR_ID_IBM, OCXL_DVSEC_AFU_CTRL_ID))) { + pci_read_config_byte(dev, vsec + OCXL_DVSEC_AFU_CTRL_AFU_IDX, + &idx); + if (idx == afu_idx) + return vsec; } return 0; } diff --git a/include/misc/ocxl-config.h b/include/misc/ocxl-config.h index ccfd3b463517..40cf1b143170 100644 --- a/include/misc/ocxl-config.h +++ b/include/misc/ocxl-config.h @@ -10,10 +10,6 @@ * It follows the specification for opencapi 3.0 */ -#define OCXL_EXT_CAP_ID_DVSEC 0x23 - -#define OCXL_DVSEC_VENDOR_OFFSET 0x4 -#define OCXL_DVSEC_ID_OFFSET 0x8 #define OCXL_DVSEC_TL_ID 0xF000 #define OCXL_DVSEC_TL_BACKOFF_TIMERS 0x10 #define OCXL_DVSEC_TL_RECV_CAP 0x18