From patchwork Fri Jul 21 18:44:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811076 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=Kd3v2EM5; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R6z5W4syLz20Fh for ; Sat, 22 Jul 2023 04:45:35 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2920286373; Fri, 21 Jul 2023 20:45:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Kd3v2EM5"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 97C1886272; Fri, 21 Jul 2023 20:45:14 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4464886297 for ; Fri, 21 Jul 2023 20:45:10 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=n-francis@ti.com Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 36LIj1Lq015487; Fri, 21 Jul 2023 13:45:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1689965101; bh=MMdJRx2F4hnpcd9DMcBAWKM7sVbEo2IzvrSCDsNi87s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Kd3v2EM5HrTNh+PXLK+Cvt8FJpLJp8m1epCbV/f+GExOaC2qoDBEGDQGKL/g2/eMv wMNDwVkw1BnvZXJN/yL/LpTh8RqT9zYiA9I38o/CocP3dU/bHXdpCglR7Uy0Dso3iv P/MiVfeFmowtMMcHMdU1OK/EYGp4gMiQRYOPn0ls= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 36LIj179109467 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 21 Jul 2023 13:45:01 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 21 Jul 2023 13:45:00 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jul 2023 13:45:00 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloI131068; Fri, 21 Jul 2023 13:44:54 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 01/23] binman: ti-board-config: Add support for TI board config binaries Date: Sat, 22 Jul 2023 00:14:24 +0530 Message-ID: <20230721184446.5821-2-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The ti-board-config entry loads and validates a given YAML config file against a given schema, and generates the board config binary. K3 devices require these binaries to be packed into the final system firmware images. Reviewed-by: Simon Glass Signed-off-by: Neha Malcom Francis --- tools/binman/entries.rst | 48 ++++ tools/binman/etype/ti_board_config.py | 259 ++++++++++++++++++ tools/binman/ftest.py | 20 ++ tools/binman/test/277_ti_board_cfg.dts | 14 + .../binman/test/278_ti_board_cfg_combined.dts | 25 ++ .../binman/test/279_ti_board_cfg_no_type.dts | 11 + tools/binman/test/yaml/config.yaml | 18 ++ tools/binman/test/yaml/schema.yaml | 49 ++++ tools/binman/test/yaml/schema_notype.yaml | 38 +++ 9 files changed, 482 insertions(+) create mode 100644 tools/binman/etype/ti_board_config.py create mode 100644 tools/binman/test/277_ti_board_cfg.dts create mode 100644 tools/binman/test/278_ti_board_cfg_combined.dts create mode 100644 tools/binman/test/279_ti_board_cfg_no_type.dts create mode 100644 tools/binman/test/yaml/config.yaml create mode 100644 tools/binman/test/yaml/schema.yaml create mode 100644 tools/binman/test/yaml/schema_notype.yaml diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst index b71af801fd..14a2d03fad 100644 --- a/tools/binman/entries.rst +++ b/tools/binman/entries.rst @@ -1658,6 +1658,54 @@ by setting the size of the entry to something larger than the text. +.. _etype_ti_board_config: + +Entry: ti-board-config: An entry containing a TI schema validated board config binary +------------------------------------------------------------------------------------- + +This etype supports generation of two kinds of board configuration +binaries: singular board config binary as well as combined board config +binary. + +Properties / Entry arguments: + - config-file: File containing board configuration data in YAML + - schema-file: File containing board configuration YAML schema against + which the config file is validated + +Output files: + - board config binary: File containing board configuration binary + +These above parameters are used only when the generated binary is +intended to be a single board configuration binary. Example:: + + my-ti-board-config { + ti-board-config { + config = "board-config.yaml"; + schema = "schema.yaml"; + }; + }; + +To generate a combined board configuration binary, we pack the +needed individual binaries into a ti-board-config binary. In this case, +the available supported subnode names are board-cfg, pm-cfg, sec-cfg and +rm-cfg. The final binary is prepended with a header containing details about +the included board config binaries. Example:: + + my-combined-ti-board-config { + ti-board-config { + board-cfg { + config = "board-cfg.yaml"; + schema = "schema.yaml"; + }; + sec-cfg { + config = "sec-cfg.yaml"; + schema = "schema.yaml"; + }; + } + } + + + .. _etype_u_boot: Entry: u-boot: U-Boot flat binary diff --git a/tools/binman/etype/ti_board_config.py b/tools/binman/etype/ti_board_config.py new file mode 100644 index 0000000000..94f894c281 --- /dev/null +++ b/tools/binman/etype/ti_board_config.py @@ -0,0 +1,259 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (c) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Written by Neha Malcom Francis +# +# Entry-type module for generating schema validated TI board +# configuration binary +# + +import os +import struct +import yaml + +from collections import OrderedDict +from jsonschema import validate +from shutil import copyfileobj + +from binman.entry import Entry +from binman.etype.section import Entry_section +from dtoc import fdt_util +from u_boot_pylib import tools + +BOARDCFG = 0xB +BOARDCFG_SEC = 0xD +BOARDCFG_PM = 0xE +BOARDCFG_RM = 0xC +BOARDCFG_NUM_ELEMS = 4 + +class Entry_ti_board_config(Entry_section): + """An entry containing a TI schema validated board config binary + + This etype supports generation of two kinds of board configuration + binaries: singular board config binary as well as combined board config + binary. + + Properties / Entry arguments: + - config-file: File containing board configuration data in YAML + - schema-file: File containing board configuration YAML schema against + which the config file is validated + + Output files: + - board config binary: File containing board configuration binary + + These above parameters are used only when the generated binary is + intended to be a single board configuration binary. Example:: + + my-ti-board-config { + ti-board-config { + config = "board-config.yaml"; + schema = "schema.yaml"; + }; + }; + + To generate a combined board configuration binary, we pack the + needed individual binaries into a ti-board-config binary. In this case, + the available supported subnode names are board-cfg, pm-cfg, sec-cfg and + rm-cfg. The final binary is prepended with a header containing details about + the included board config binaries. Example:: + + my-combined-ti-board-config { + ti-board-config { + board-cfg { + config = "board-cfg.yaml"; + schema = "schema.yaml"; + }; + sec-cfg { + config = "sec-cfg.yaml"; + schema = "schema.yaml"; + }; + } + } + """ + def __init__(self, section, etype, node): + super().__init__(section, etype, node) + self._config = None + self._schema = None + self._entries = OrderedDict() + self._num_elems = BOARDCFG_NUM_ELEMS + self._fmt = '; + #size-cells = <1>; + + binman { + ti-board-config { + config = "yaml/config.yaml"; + schema = "yaml/schema.yaml"; + }; + }; +}; diff --git a/tools/binman/test/278_ti_board_cfg_combined.dts b/tools/binman/test/278_ti_board_cfg_combined.dts new file mode 100644 index 0000000000..95ef449cbf --- /dev/null +++ b/tools/binman/test/278_ti_board_cfg_combined.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +/ { + binman { + ti-board-config { + board-cfg { + config = "yaml/config.yaml"; + schema = "yaml/schema.yaml"; + }; + sec-cfg { + config = "yaml/config.yaml"; + schema = "yaml/schema.yaml"; + }; + rm-cfg { + config = "yaml/config.yaml"; + schema = "yaml/schema.yaml"; + }; + pm-cfg { + config = "yaml/config.yaml"; + schema = "yaml/schema.yaml"; + }; + }; + }; +}; diff --git a/tools/binman/test/279_ti_board_cfg_no_type.dts b/tools/binman/test/279_ti_board_cfg_no_type.dts new file mode 100644 index 0000000000..584b7acc5a --- /dev/null +++ b/tools/binman/test/279_ti_board_cfg_no_type.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +/ { + binman { + ti-board-config { + config = "yaml/config.yaml"; + schema = "yaml/schema_notype.yaml"; + }; + }; +}; diff --git a/tools/binman/test/yaml/config.yaml b/tools/binman/test/yaml/config.yaml new file mode 100644 index 0000000000..5f799a6e3a --- /dev/null +++ b/tools/binman/test/yaml/config.yaml @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Test config +# +--- + +main-branch: + obj: + a: 0x0 + b: 0 + arr: [0, 0, 0, 0] + another-arr: + - #1 + c: 0 + d: 0 + - #2 + c: 0 + d: 0 diff --git a/tools/binman/test/yaml/schema.yaml b/tools/binman/test/yaml/schema.yaml new file mode 100644 index 0000000000..8aa03f3c8e --- /dev/null +++ b/tools/binman/test/yaml/schema.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Test schema +# +--- + +definitions: + u8: + type: integer + minimum: 0 + maximum: 0xff + u16: + type: integer + minimum: 0 + maximum: 0xffff + u32: + type: integer + minimum: 0 + maximum: 0xffffffff + +type: object +properties: + main-branch: + type: object + properties: + obj: + type: object + properties: + a: + $ref: "#/definitions/u32" + b: + $ref: "#/definitions/u16" + arr: + type: array + minItems: 4 + maxItems: 4 + items: + $ref: "#/definitions/u8" + another-arr: + type: array + minItems: 2 + maxItems: 2 + items: + type: object + properties: + c: + $ref: "#/definitions/u8" + d: + $ref: "#/definitions/u8" diff --git a/tools/binman/test/yaml/schema_notype.yaml b/tools/binman/test/yaml/schema_notype.yaml new file mode 100644 index 0000000000..6b4d98ffa1 --- /dev/null +++ b/tools/binman/test/yaml/schema_notype.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Test schema +# +--- + +definitions: + u8: + type: integer + minimum: 0 + maximum: 0xff + u16: + type: integer + minimum: 0 + maximum: 0xffff + u32: + type: integer + minimum: 0 + maximum: 0xffffffff + +type: object +properties: + main-branch: + type: object + properties: + obj: + type: object + properties: + a: + $ref: "#/definitions/u4" + b: + $ref: "#/definitions/u16" + arr: + type: array + minItems: 4 + maxItems: 4 + items: + $ref: "#/definitions/u8" From patchwork Fri Jul 21 18:44:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811077 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=XsHvKFrK; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R6z5g0tGpz20Fh for ; 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Fri, 21 Jul 2023 13:45:07 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jul 2023 13:45:07 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloJ131068; Fri, 21 Jul 2023 13:45:01 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 02/23] binman: ti-secure: Add support for TI signing Date: Sat, 22 Jul 2023 00:14:25 +0530 Message-ID: <20230721184446.5821-3-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The ti-secure entry contains certificate for binaries that will be loaded or booted by system firmware whereas the ti-secure-rom entry contains certificate for binaries that will be booted by ROM. Support for both these types of certificates is necessary for booting of K3 devices. Reviewed-by: Simon Glass [vigneshr@ti.com: fixed inconsist cert generation by multiple packing] Signed-off-by: Vignesh Raghavendra Signed-off-by: Neha Malcom Francis --- board/ti/keys/custMpk.pem | 51 ++++ board/ti/keys/ti-degenerate-key.pem | 10 + tools/binman/btool/openssl.py | 244 +++++++++++++++++ tools/binman/entries.rst | 65 +++++ tools/binman/etype/ti_secure.py | 78 ++++++ tools/binman/etype/ti_secure_rom.py | 249 ++++++++++++++++++ tools/binman/etype/x509_cert.py | 87 +++++- tools/binman/ftest.py | 52 ++++ tools/binman/test/279_ti_secure.dts | 17 ++ tools/binman/test/280_ti_secure_rom.dts | 17 ++ .../test/281_ti_secure_rom_combined.dts | 25 ++ tools/binman/test/288_ti_secure_rom_a.dts | 19 ++ tools/binman/test/289_ti_secure_rom_b.dts | 18 ++ 13 files changed, 924 insertions(+), 8 deletions(-) create mode 100644 board/ti/keys/custMpk.pem create mode 100644 board/ti/keys/ti-degenerate-key.pem create mode 100644 tools/binman/etype/ti_secure.py create mode 100644 tools/binman/etype/ti_secure_rom.py create mode 100644 tools/binman/test/279_ti_secure.dts create mode 100644 tools/binman/test/280_ti_secure_rom.dts create mode 100644 tools/binman/test/281_ti_secure_rom_combined.dts create mode 100644 tools/binman/test/288_ti_secure_rom_a.dts create mode 100644 tools/binman/test/289_ti_secure_rom_b.dts diff --git a/board/ti/keys/custMpk.pem b/board/ti/keys/custMpk.pem new file mode 100644 index 0000000000..adba378c80 --- /dev/null +++ b/board/ti/keys/custMpk.pem @@ -0,0 +1,51 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIJKQIBAAKCAgEAvxSuSdh/ctNrI83rSA5l3CJN8g5PgvbttfLd23yR+m5Z/9X3 +tt4EHYrM0pXZ0eDEwfhQv/9IDJEiUJpMe4vzlgooJrOk2eCpVUEa+z5bJ2y/ysBx +ry9yIu5GASVirT7HBPaxGLYswBJuD+KbPuWmoKgGRQNBF04WH6l01oRO1nmnELgR +qQ6SHyXdf7Hy0bnyaNgzWUuCfXfM0Zz6I7T7WIjyzerVFvIsdS36YsPBCW7gBnDg +tQcJmWLZ1uTnbG3IggdQk/fi2O3RX+PQns+TVNlf3V3ON2DxqxSKBHtlp7p/30VF +fEuhW65OxpQ9jE6H0pQ8pPOf2vzyNnznDa1aQjfxKoHQbqGnZwMeh+0Au3NKaCgx +ooKaowTB6If/RX6qwZ/UOwXHg/0hcf69fzjJFhlSDuYDM40dHsk2HM1OnYIpiM2b +Kr5sX3uysjp5AGp99a0anR7NWCrPXvROgKs7T9341N40osQg2VkZLYUCXh9osUyN +uREG6S12tViMUKg3bmZ4b4MwRk00n7QYSrm7+nvFrtYyEISEbD+agDM1/E281W5g +VFDPfm2AlwT6jwsg/b2YK6E3vVn9SuxFoQmLF8lyFDO3BV4SXeJaHc4hVPbh6tVV +qifrTQnfGUCCLmaJF2XZbrPWOE6NYRbWdNTeFl9RGdVCuIPSyN5LqWmXto0CAwEA +AQKCAgAzkAwcJ0z1GnId/lJQZno8NhGckRoJuEKbR8dwlCP8VUz6Ca5H7Y9kvXDa +Hs/hn+rYgP6hYOz7XyrIX2rmJ/T6dxEwqGeC1+o59FConcIRWHpE5zuGT6JYJL5F +TuZa48bm4v8VMQvQZOjIZpkIFwao8c6HTwKAnHTB5IN/48I2hCt+Cn3RhfoOZ7Rm +4gkpaSkt+7GXlhXHb82YfujNO+hbktEamhUYlQ9EK70Wa8aqmf3gHxO0JgsEFjW8 +lJaSnultlTW8SDcx3LMUUjCYumECk4oX/VlJfmKYjPlVjkr3QQ+Cm3nNucb4K4hc +c+JL+2ERhSj8RjXL7VgbNgdPnIjvQDJuTNqecTU8xWPYrkOLQpNibbLjnutLkhJz +fMyRtmDtrsey8WiCDuCHkPJ8/f8RjL2zWI9fzTDDIzdlEKouUFGOovaHVnbua6pn +hymcu9d9FV3p2rcbj0ivCs7e8j+vhSxFJEJoAbcQdXCTi/n2uR7pLtoMNiUzsejy +d46Uz+KEU920NTwE2z6JJq8I2vegnxjc7PDDrV3/5rK04B93aXiqvwWseCpxelrI +xaMkRHbXrIXRO6MXQ3N+zNq8Dg3hjGTTvaBKuwgvqLwlXY8+Aa3ooFzEOInIOSsI +XcWqXxt/tgZgsj9RwpC42t8kbA+BkbNk9EIUa+P5kEr2P/fO7QKCAQEA4EtArnOX +D6tQF8uTw8USOZC2P9s/ez1z4jRq3oKP0Kv4tJiuIObJ/dUvGVD7aM5v2xaCfhm8 +xpk09VPUgghfG5jR5qVvQr75kCNToJQudWi4ngk1HwKJzzTO11giFEdybvTUA+Pj +fmxCM0dYYqRWZoj0hLqXlUCwxE74BFIhJVjeYbf+nTQrqpllTLoW7MTZHzGx5SXx +4dNzyVAUH49Yt2D8mgXXCkf5sGLh762wj34b/rR10Kr4O5utGMZrfTRIbuQ1pNjU +m66baPzq+mC0BzqZEW70TgEb7lOr8rcVXLOi3r36omfd9/MHx7iZD6o3K1axSO15 +grD4ZrN7Ac3QJwKCAQEA2heCoBdpvy6YUk8AO2k8qDygTdmPQRuwjjT+Z2fMslBt +D7DkpKwZ6Bl9OclcpiiLHmH+hv65KqYg+tR0RRb7PcogB9El9x7yKkGTPZEYWGky +n8P84rJpKwjnwWQvPQktI1cs3YGvZA9DQTFBavRrwuzgd1oSJq5aPQ2tme0kMvWp +l1/B/cPK+PKCi/Wfisaze1TjijP9qIeUwkdNN6WLrLU3QgsGppcg2I7RQtAIikT6 +GkuiOQAvWMsrJVV6PNrVKz4fJDJ59Rz6jbDHZNi1MEYNxQoB/Pl7QIakbfjWpHLv +8Ey7cB2JKxjQy8tmyl8WNQVbXbE6daPXcMTUmaRAKwKCAQBv1lYMJmq+T2eCVen6 +BbvOpE+bi5EdvEiaFBTtmiBnpjg+pJq+oRU60h/H+c9CNR0lGxY6Fk9An4f+g6xE +ojP6KLsQzJCrsVny+wpp2TlJJcxYULMCIVvhy60PR0zG29E9biqBPhJjKUvhEcQK +e3LxcXyq6fdHXphFajLUxLbuTl+kTgBRFoBnclFGbsubh5PTsA3J+p+fQLZNPPar +veg4l82cZykQYU8pGkUaI3sUMYd3+zd7sqRP5JHs9pMGPRmY4YW2CsAIWIn5UZNB +ARMDP76vKKn8cyUgMuxb+9pU/OVLN2NPs4bEaZQJjAwV+YPEwldny7F47xEM9JVz +EtKlAoIBAQDUt62u3GdGE/p5/ZgqWoDRTyDEDfmN9aYFbmbdEP80xQE7FrxMaZhz +K7laja6SWmUm40nQ/c45bQQp4uLtKHcxU15egX7YRBTLZl5o5IasZR79ebnEm2O8 +l9kEZeU1USf3mmWmP4GExOZCRfqaiYA6BbUCdJXTqKdXeWnkAssV8UrS3JFoJHpq +yo7OWGqefyQ8nRW6jO9SW7uaqtUD+7H6aF5XSk3YWvusfdBZrHNH+fM/hpnZovaL +Us7ogTDS/laA8PyK37jYfMVdQhmZoU1Iomt3zkUWK3gt/aWPpfAlQf4Jka4YspZB +tNiijefaZ1hPqsPs5Joyd/YAhdsfaHc1AoIBAQCn/9j6RRjRaw0ip756oad4AXHz +XBwVB2CrY96qT6Hj9Sq7tGgdskqGkOQkAivBLBizUdcWv0t1yenOsSgasQeMlvlh +B8md9cLvpKXPB3HM3rTDH/xNXe0TpVKLf7SXC8HfDyIweHwMW3QgO2DWrvI4BV/T +ckBatRNQ90HxkqGFhC/Mp529lQlyg3ifxPxJsvZOyPMUnrflAvsKQk5c2ZiQg3nZ +h7I2pjSYgCl+Ib52l8p9bf1kcrVGgPM+auzm496i0RPobFeDBoBvSoznJktHJ7+3 +NnZH+jLiZCODiQPGtQUi+T6eIZUIJF0YASpsCCtUzXCxwW3lYIDNy7UlMivF +-----END RSA PRIVATE KEY----- diff --git a/board/ti/keys/ti-degenerate-key.pem b/board/ti/keys/ti-degenerate-key.pem new file mode 100644 index 0000000000..bd7d3745ad --- /dev/null +++ b/board/ti/keys/ti-degenerate-key.pem @@ -0,0 +1,10 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIBWwIBAAKBgQDRfrnXQaP0k6vRK/gZ+bDflSU6y1JagGeQ/b+QYuiDz14japog +8fRSu5WBsAxaSaySAUwS3L9Ppw+hGMecmyIJ494aMfZTtk1g49gU58joduiRnu7e +QSZHMnehhuNlfD7A2tAAKnxIYuabs8zHYM/SS9Ne7t3kIQMbKfUSzNy6qQIBAQIB +AQJBAOelUA376o6w3HkShXfN+shaOZYqFuTJ9exLMwsLp7DZKXB5F9I4JJ+Vkvho +k6QWs7vkhleLSYUZknXHYm26ZE0CQQDnhTtd4PTBoZPjPXOeYMJFtEdMNy0XP6ey +bcce389ugoY7BEkvASrd8PHgJQHziepgWOG4DGp33c64Hfq4zI3NAgEBAgEBAkA0 +RbK4uqoLciQluesTPU6lBy7Se3Dw0F9xBqlF5SR4KI6q+zQrHpBKyFOofMHZgizR +iCrL55cxEM146zMw3AnF +-----END RSA PRIVATE KEY----- diff --git a/tools/binman/btool/openssl.py b/tools/binman/btool/openssl.py index 3a4dbdd6d7..aad3b61ae2 100644 --- a/tools/binman/btool/openssl.py +++ b/tools/binman/btool/openssl.py @@ -15,6 +15,13 @@ import hashlib from binman import bintool from u_boot_pylib import tools + +VALID_SHAS = [256, 384, 512, 224] +SHA_OIDS = {256:'2.16.840.1.101.3.4.2.1', + 384:'2.16.840.1.101.3.4.2.2', + 512:'2.16.840.1.101.3.4.2.3', + 224:'2.16.840.1.101.3.4.2.4'} + class Bintoolopenssl(bintool.Bintool): """openssl tool @@ -74,6 +81,243 @@ imageSize = INTEGER:{len(indata)} '-sha512'] return self.run_cmd(*args) + def x509_cert_sysfw(self, cert_fname, input_fname, key_fname, sw_rev, + config_fname, req_dist_name_dict): + """Create a certificate to be booted by system firmware + + Args: + cert_fname (str): Filename of certificate to create + input_fname (str): Filename containing data to sign + key_fname (str): Filename of .pem file + sw_rev (int): Software revision + config_fname (str): Filename to write fconfig into + req_dist_name_dict (dict): Dictionary containing key-value pairs of + req_distinguished_name section extensions, must contain extensions for + C, ST, L, O, OU, CN and emailAddress + + Returns: + str: Tool output + """ + indata = tools.read_file(input_fname) + hashval = hashlib.sha512(indata).hexdigest() + with open(config_fname, 'w', encoding='utf-8') as outf: + print(f'''[ req ] +distinguished_name = req_distinguished_name +x509_extensions = v3_ca +prompt = no +dirstring_type = nobmp + +[ req_distinguished_name ] +C = {req_dist_name_dict['C']} +ST = {req_dist_name_dict['ST']} +L = {req_dist_name_dict['L']} +O = {req_dist_name_dict['O']} +OU = {req_dist_name_dict['OU']} +CN = {req_dist_name_dict['CN']} +emailAddress = {req_dist_name_dict['emailAddress']} + +[ v3_ca ] +basicConstraints = CA:true +1.3.6.1.4.1.294.1.3 = ASN1:SEQUENCE:swrv +1.3.6.1.4.1.294.1.34 = ASN1:SEQUENCE:sysfw_image_integrity +1.3.6.1.4.1.294.1.35 = ASN1:SEQUENCE:sysfw_image_load + +[ swrv ] +swrv = INTEGER:{sw_rev} + +[ sysfw_image_integrity ] +shaType = OID:2.16.840.1.101.3.4.2.3 +shaValue = FORMAT:HEX,OCT:{hashval} +imageSize = INTEGER:{len(indata)} + +[ sysfw_image_load ] +destAddr = FORMAT:HEX,OCT:00000000 +authInPlace = INTEGER:2 +''', file=outf) + args = ['req', '-new', '-x509', '-key', key_fname, '-nodes', + '-outform', 'DER', '-out', cert_fname, '-config', config_fname, + '-sha512'] + return self.run_cmd(*args) + + def x509_cert_rom(self, cert_fname, input_fname, key_fname, sw_rev, + config_fname, req_dist_name_dict, cert_type, bootcore, + bootcore_opts, load_addr, sha): + """Create a certificate + + Args: + cert_fname (str): Filename of certificate to create + input_fname (str): Filename containing data to sign + key_fname (str): Filename of .pem file + sw_rev (int): Software revision + config_fname (str): Filename to write fconfig into + req_dist_name_dict (dict): Dictionary containing key-value pairs of + req_distinguished_name section extensions, must contain extensions for + C, ST, L, O, OU, CN and emailAddress + cert_type (int): Certification type + bootcore (int): Booting core + load_addr (int): Load address of image + sha (int): Hash function + + Returns: + str: Tool output + """ + indata = tools.read_file(input_fname) + hashval = hashlib.sha512(indata).hexdigest() + with open(config_fname, 'w', encoding='utf-8') as outf: + print(f''' +[ req ] + distinguished_name = req_distinguished_name + x509_extensions = v3_ca + prompt = no + dirstring_type = nobmp + + [ req_distinguished_name ] +C = {req_dist_name_dict['C']} +ST = {req_dist_name_dict['ST']} +L = {req_dist_name_dict['L']} +O = {req_dist_name_dict['O']} +OU = {req_dist_name_dict['OU']} +CN = {req_dist_name_dict['CN']} +emailAddress = {req_dist_name_dict['emailAddress']} + + [ v3_ca ] + basicConstraints = CA:true + 1.3.6.1.4.1.294.1.1 = ASN1:SEQUENCE:boot_seq + 1.3.6.1.4.1.294.1.2 = ASN1:SEQUENCE:image_integrity + 1.3.6.1.4.1.294.1.3 = ASN1:SEQUENCE:swrv +# 1.3.6.1.4.1.294.1.4 = ASN1:SEQUENCE:encryption + 1.3.6.1.4.1.294.1.8 = ASN1:SEQUENCE:debug + + [ boot_seq ] + certType = INTEGER:{cert_type} + bootCore = INTEGER:{bootcore} + bootCoreOpts = INTEGER:{bootcore_opts} + destAddr = FORMAT:HEX,OCT:{load_addr:08x} + imageSize = INTEGER:{len(indata)} + + [ image_integrity ] + shaType = OID:{SHA_OIDS[sha]} + shaValue = FORMAT:HEX,OCT:{hashval} + + [ swrv ] + swrv = INTEGER:{sw_rev} + +# [ encryption ] +# initalVector = FORMAT:HEX,OCT:TEST_IMAGE_ENC_IV +# randomString = FORMAT:HEX,OCT:TEST_IMAGE_ENC_RS +# iterationCnt = INTEGER:TEST_IMAGE_KEY_DERIVE_INDEX +# salt = FORMAT:HEX,OCT:TEST_IMAGE_KEY_DERIVE_SALT + + [ debug ] + debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000 + debugType = INTEGER:4 + coreDbgEn = INTEGER:0 + coreDbgSecEn = INTEGER:0 +''', file=outf) + args = ['req', '-new', '-x509', '-key', key_fname, '-nodes', + '-outform', 'DER', '-out', cert_fname, '-config', config_fname, + '-sha512'] + return self.run_cmd(*args) + + def x509_cert_rom_combined(self, cert_fname, input_fname, key_fname, sw_rev, + config_fname, req_dist_name_dict, load_addr, sha, total_size, num_comps, + sysfw_inner_cert_ext_boot_sequence_string, dm_data_ext_boot_sequence_string, + imagesize_sbl, hashval_sbl, load_addr_sysfw, imagesize_sysfw, + hashval_sysfw, load_addr_sysfw_data, imagesize_sysfw_data, + hashval_sysfw_data, sysfw_inner_cert_ext_boot_block, + dm_data_ext_boot_block): + """Create a certificate + + Args: + cert_fname (str): Filename of certificate to create + input_fname (str): Filename containing data to sign + key_fname (str): Filename of .pem file + sw_rev (int): Software revision + config_fname (str): Filename to write fconfig into + req_dist_name_dict (dict): Dictionary containing key-value pairs of + req_distinguished_name section extensions, must contain extensions for + C, ST, L, O, OU, CN and emailAddress + cert_type (int): Certification type + bootcore (int): Booting core + load_addr (int): Load address of image + sha (int): Hash function + + Returns: + str: Tool output + """ + indata = tools.read_file(input_fname) + hashval = hashlib.sha512(indata).hexdigest() + sha_type = SHA_OIDS[sha] + with open(config_fname, 'w', encoding='utf-8') as outf: + print(f''' +[ req ] +distinguished_name = req_distinguished_name +x509_extensions = v3_ca +prompt = no +dirstring_type = nobmp + +[ req_distinguished_name ] +C = {req_dist_name_dict['C']} +ST = {req_dist_name_dict['ST']} +L = {req_dist_name_dict['L']} +O = {req_dist_name_dict['O']} +OU = {req_dist_name_dict['OU']} +CN = {req_dist_name_dict['CN']} +emailAddress = {req_dist_name_dict['emailAddress']} + +[ v3_ca ] +basicConstraints = CA:true +1.3.6.1.4.1.294.1.3=ASN1:SEQUENCE:swrv +1.3.6.1.4.1.294.1.9=ASN1:SEQUENCE:ext_boot_info + +[swrv] +swrv=INTEGER:{sw_rev} + +[ext_boot_info] +extImgSize=INTEGER:{total_size} +numComp=INTEGER:{num_comps} +sbl=SEQUENCE:sbl +sysfw=SEQUENCE:sysfw +sysfw_data=SEQUENCE:sysfw_data +{sysfw_inner_cert_ext_boot_sequence_string} +{dm_data_ext_boot_sequence_string} + +[sbl] +compType = INTEGER:1 +bootCore = INTEGER:16 +compOpts = INTEGER:0 +destAddr = FORMAT:HEX,OCT:{load_addr:08x} +compSize = INTEGER:{imagesize_sbl} +shaType = OID:{sha_type} +shaValue = FORMAT:HEX,OCT:{hashval_sbl} + +[sysfw] +compType = INTEGER:2 +bootCore = INTEGER:0 +compOpts = INTEGER:0 +destAddr = FORMAT:HEX,OCT:{load_addr_sysfw:08x} +compSize = INTEGER:{imagesize_sysfw} +shaType = OID:{sha_type} +shaValue = FORMAT:HEX,OCT:{hashval_sysfw} + +[sysfw_data] +compType = INTEGER:18 +bootCore = INTEGER:0 +compOpts = INTEGER:0 +destAddr = FORMAT:HEX,OCT:{load_addr_sysfw_data:08x} +compSize = INTEGER:{imagesize_sysfw_data} +shaType = OID:{sha_type} +shaValue = FORMAT:HEX,OCT:{hashval_sysfw_data} + +{sysfw_inner_cert_ext_boot_block} + +{dm_data_ext_boot_block} + ''', file=outf) + args = ['req', '-new', '-x509', '-key', key_fname, '-nodes', + '-outform', 'DER', '-out', cert_fname, '-config', config_fname, + '-sha512'] + return self.run_cmd(*args) + def fetch(self, method): """Fetch handler for openssl diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst index 14a2d03fad..a4c0223c84 100644 --- a/tools/binman/entries.rst +++ b/tools/binman/entries.rst @@ -1706,6 +1706,71 @@ the included board config binaries. Example:: +.. _etype_ti_secure: + +Entry: ti-secure: Entry containing a TI x509 certificate binary +--------------------------------------------------------------- + +Properties / Entry arguments: + - content: List of phandles to entries to sign + - keyfile: Filename of file containing key to sign binary with + - sha: Hash function to be used for signing + +Output files: + - input. - input file passed to openssl + - config. - input file generated for openssl (which is + used as the config file) + - cert. - output file generated by openssl (which is + used as the entry contents) + +openssl signs the provided data, using the TI templated config file and +writes the signature in this entry. This allows verification that the +data is genuine. + + + +.. _etype_ti_secure_rom: + +Entry: ti-secure-rom: Entry containing a TI x509 certificate binary for images booted by ROM +-------------------------------------------------------------------------------------------- + +Properties / Entry arguments: + - keyfile: Filename of file containing key to sign binary with + - combined: boolean if device follows combined boot flow + - countersign: boolean if device contains countersigned system firmware + - load: load address of SPL + - sw-rev: software revision + - sha: Hash function to be used for signing + - core: core on which bootloader runs, valid cores are 'secure' and 'public' + - content: phandle of SPL in case of legacy bootflow or phandles of component binaries + in case of combined bootflow + +The following properties are only for generating a combined bootflow binary: + - sysfw-inner-cert: boolean if binary contains sysfw inner certificate + - dm-data: boolean if binary contains dm-data binary + - content-sbl: phandle of SPL binary + - content-sysfw: phandle of sysfw binary + - content-sysfw-data: phandle of sysfw-data or tifs-data binary + - content-sysfw-inner-cert (optional): phandle of sysfw inner certificate binary + - content-dm-data (optional): phandle of dm-data binary + - load-sysfw: load address of sysfw binary + - load-sysfw-data: load address of sysfw-data or tifs-data binary + - load-sysfw-inner-cert (optional): load address of sysfw inner certificate binary + - load-dm-data (optional): load address of dm-data binary + +Output files: + - input. - input file passed to openssl + - config. - input file generated for openssl (which is + used as the config file) + - cert. - output file generated by openssl (which is + used as the entry contents) + +openssl signs the provided data, using the TI templated config file and +writes the signature in this entry. This allows verification that the +data is genuine. + + + .. _etype_u_boot: Entry: u-boot: U-Boot flat binary diff --git a/tools/binman/etype/ti_secure.py b/tools/binman/etype/ti_secure.py new file mode 100644 index 0000000000..d939dce571 --- /dev/null +++ b/tools/binman/etype/ti_secure.py @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (c) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Written by Neha Malcom Francis +# + +# Support for generation of TI secured binary blobs + +from binman.entry import EntryArg +from binman.etype.x509_cert import Entry_x509_cert + +from dtoc import fdt_util + +class Entry_ti_secure(Entry_x509_cert): + """Entry containing a TI x509 certificate binary + + Properties / Entry arguments: + - content: List of phandles to entries to sign + - keyfile: Filename of file containing key to sign binary with + - sha: Hash function to be used for signing + + Output files: + - input. - input file passed to openssl + - config. - input file generated for openssl (which is + used as the config file) + - cert. - output file generated by openssl (which is + used as the entry contents) + + openssl signs the provided data, using the TI templated config file and + writes the signature in this entry. This allows verification that the + data is genuine. + """ + def __init__(self, section, etype, node): + super().__init__(section, etype, node) + self.openssl = None + + def ReadNode(self): + super().ReadNode() + self.key_fname = self.GetEntryArgsOrProps([ + EntryArg('keyfile', str)], required=True)[0] + self.sha = fdt_util.GetInt(self._node, 'sha', 512) + self.req_dist_name = {'C': 'US', + 'ST': 'TX', + 'L': 'Dallas', + 'O': 'Texas Instruments Incorporated', + 'OU': 'Processors', + 'CN': 'TI Support', + 'emailAddress': 'support@ti.com'} + + def GetCertificate(self, required): + """Get the contents of this entry + + Args: + required: True if the data must be present, False if it is OK to + return None + + Returns: + bytes content of the entry, which is the certificate binary for the + provided data + """ + return super().GetCertificate(required=required, type='sysfw') + + def ObtainContents(self): + data = self.data + if data is None: + data = self.GetCertificate(False) + if data is None: + return False + self.SetContents(data) + return True + + def ProcessContents(self): + # The blob may have changed due to WriteSymbols() + data = self.data + return self.ProcessContentsUpdate(data) + + def AddBintools(self, btools): + super().AddBintools(btools) + self.openssl = self.AddBintool(btools, 'openssl') diff --git a/tools/binman/etype/ti_secure_rom.py b/tools/binman/etype/ti_secure_rom.py new file mode 100644 index 0000000000..9a7ac9e9e0 --- /dev/null +++ b/tools/binman/etype/ti_secure_rom.py @@ -0,0 +1,249 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (c) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Written by Neha Malcom Francis +# + +# Support for generation of TI secured bootloaders booted by ROM + +from binman.entry import EntryArg +from binman.etype.x509_cert import Entry_x509_cert + +import hashlib + +from dtoc import fdt_util +from u_boot_pylib import tools + +VALID_SHAS = [256, 384, 512, 224] +SHA_OIDS = {256:'2.16.840.1.101.3.4.2.1', + 384:'2.16.840.1.101.3.4.2.2', + 512:'2.16.840.1.101.3.4.2.3', + 224:'2.16.840.1.101.3.4.2.4'} + +class Entry_ti_secure_rom(Entry_x509_cert): + """Entry containing a TI x509 certificate binary for images booted by ROM + + Properties / Entry arguments: + - keyfile: Filename of file containing key to sign binary with + - combined: boolean if device follows combined boot flow + - countersign: boolean if device contains countersigned system firmware + - load: load address of SPL + - sw-rev: software revision + - sha: Hash function to be used for signing + - core: core on which bootloader runs, valid cores are 'secure' and 'public' + - content: phandle of SPL in case of legacy bootflow or phandles of component binaries + in case of combined bootflow + + The following properties are only for generating a combined bootflow binary: + - sysfw-inner-cert: boolean if binary contains sysfw inner certificate + - dm-data: boolean if binary contains dm-data binary + - content-sbl: phandle of SPL binary + - content-sysfw: phandle of sysfw binary + - content-sysfw-data: phandle of sysfw-data or tifs-data binary + - content-sysfw-inner-cert (optional): phandle of sysfw inner certificate binary + - content-dm-data (optional): phandle of dm-data binary + - load-sysfw: load address of sysfw binary + - load-sysfw-data: load address of sysfw-data or tifs-data binary + - load-sysfw-inner-cert (optional): load address of sysfw inner certificate binary + - load-dm-data (optional): load address of dm-data binary + + Output files: + - input. - input file passed to openssl + - config. - input file generated for openssl (which is + used as the config file) + - cert. - output file generated by openssl (which is + used as the entry contents) + + openssl signs the provided data, using the TI templated config file and + writes the signature in this entry. This allows verification that the + data is genuine. + """ + def __init__(self, section, etype, node): + super().__init__(section, etype, node) + self.openssl = None + + def ReadNode(self): + super().ReadNode() + self.combined = fdt_util.GetBool(self._node, 'combined', False) + self.countersign = fdt_util.GetBool(self._node, 'countersign', False) + self.load_addr = fdt_util.GetInt(self._node, 'load', 0x00000000) + self.sw_rev = fdt_util.GetInt(self._node, 'sw-rev', 1) + self.sha = fdt_util.GetInt(self._node, 'sha', 512) + self.core = fdt_util.GetString(self._node, 'core', 'secure') + self.key_fname = self.GetEntryArgsOrProps([ + EntryArg('keyfile', str)], required=True)[0] + if self.combined: + self.sysfw_inner_cert = fdt_util.GetBool(self._node, 'sysfw-inner-cert', False) + self.load_addr_sysfw = fdt_util.GetInt(self._node, 'load-sysfw', 0x00000000) + self.load_addr_sysfw_data = fdt_util.GetInt(self._node, 'load-sysfw-data', 0x00000000) + self.dm_data = fdt_util.GetBool(self._node, 'dm-data', False) + if self.dm_data: + self.load_addr_dm_data = fdt_util.GetInt(self._node, 'load-dm-data', 0x00000000) + self.req_dist_name = {'C': 'US', + 'ST': 'TX', + 'L': 'Dallas', + 'O': 'Texas Instruments Incorporated', + 'OU': 'Processors', + 'CN': 'TI Support', + 'emailAddress': 'support@ti.com'} + + def NonCombinedGetCertificate(self, required): + """Generate certificate for legacy boot flow + + Args: + required: True if the data must be present, False if it is OK to + return None + + Returns: + bytes content of the entry, which is the certificate binary for the + provided data + """ + if self.core == 'secure': + if self.countersign: + self.cert_type = 3 + else: + self.cert_type = 2 + self.bootcore = 0 + self.bootcore_opts = 32 + else: + self.cert_type = 1 + self.bootcore = 16 + self.bootcore_opts = 0 + return super().GetCertificate(required=required, type='rom') + + def CombinedGetCertificate(self, required): + """Generate certificate for combined boot flow + + Args: + required: True if the data must be present, False if it is OK to + return None + + Returns: + bytes content of the entry, which is the certificate binary for the + provided data + """ + uniq = self.GetUniqueName() + + self.num_comps = 3 + self.sha_type = SHA_OIDS[self.sha] + + # sbl + self.content = fdt_util.GetPhandleList(self._node, 'content-sbl') + input_data_sbl = self.GetContents(required) + if input_data_sbl is None: + return None + + input_fname_sbl = tools.get_output_filename('input.%s' % uniq) + tools.write_file(input_fname_sbl, input_data_sbl) + + indata_sbl = tools.read_file(input_fname_sbl) + self.hashval_sbl = hashlib.sha512(indata_sbl).hexdigest() + self.imagesize_sbl = len(indata_sbl) + + # sysfw + self.content = fdt_util.GetPhandleList(self._node, 'content-sysfw') + input_data_sysfw = self.GetContents(required) + + input_fname_sysfw = tools.get_output_filename('input.%s' % uniq) + tools.write_file(input_fname_sysfw, input_data_sysfw) + + indata_sysfw = tools.read_file(input_fname_sysfw) + self.hashval_sysfw = hashlib.sha512(indata_sysfw).hexdigest() + self.imagesize_sysfw = len(indata_sysfw) + + # sysfw data + self.content = fdt_util.GetPhandleList(self._node, 'content-sysfw-data') + input_data_sysfw_data = self.GetContents(required) + + input_fname_sysfw_data = tools.get_output_filename('input.%s' % uniq) + tools.write_file(input_fname_sysfw_data, input_data_sysfw_data) + + indata_sysfw_data = tools.read_file(input_fname_sysfw_data) + self.hashval_sysfw_data = hashlib.sha512(indata_sysfw_data).hexdigest() + self.imagesize_sysfw_data = len(indata_sysfw_data) + + # sysfw inner cert + self.sysfw_inner_cert_ext_boot_block = "" + self.sysfw_inner_cert_ext_boot_sequence_string = "" + imagesize_sysfw_inner_cert = 0 + if self.sysfw_inner_cert: + self.content = fdt_util.GetPhandleList(self._node, 'content-sysfw-inner-cert') + input_data_sysfw_inner_cert = self.GetContents(required) + + input_fname_sysfw_inner_cert = tools.get_output_filename('input.%s' % uniq) + tools.write_file(input_fname_sysfw_inner_cert, input_data_sysfw_inner_cert) + + indata_sysfw_inner_cert = tools.read_file(input_fname_sysfw_inner_cert) + hashval_sysfw_inner_cert = hashlib.sha512(indata_sysfw_inner_cert).hexdigest() + imagesize_sysfw_inner_cert = len(indata_sysfw_inner_cert) + self.num_comps += 1 + self.sysfw_inner_cert_ext_boot_sequence_string = "sysfw_inner_cert=SEQUENCE:sysfw_inner_cert" + self.sysfw_inner_cert_ext_boot_block = f"""[sysfw_inner_cert] +compType = INTEGER:3 +bootCore = INTEGER:0 +compOpts = INTEGER:0 +destAddr = FORMAT:HEX,OCT:00000000 +compSize = INTEGER:{imagesize_sysfw_inner_cert} +shaType = OID:{self.sha_type} +shaValue = FORMAT:HEX,OCT:{hashval_sysfw_inner_cert}""" + + # dm data + self.dm_data_ext_boot_sequence_string = "" + self.dm_data_ext_boot_block = "" + imagesize_dm_data = 0 + if self.dm_data: + self.content = fdt_util.GetPhandleList(self._node, 'content-dm-data') + input_data_dm_data = self.GetContents(required) + + input_fname_dm_data = tools.get_output_filename('input.%s' % uniq) + tools.write_file(input_fname_dm_data, input_data_dm_data) + + indata_dm_data = tools.read_file(input_fname_dm_data) + hashval_dm_data = hashlib.sha512(indata_dm_data).hexdigest() + imagesize_dm_data = len(indata_dm_data) + self.num_comps += 1 + self.dm_data_ext_boot_sequence_string = "dm_data=SEQUENCE:dm_data" + self.dm_data_ext_boot_block = f"""[dm_data] +compType = INTEGER:17 +bootCore = INTEGER:16 +compOpts = INTEGER:0 +destAddr = FORMAT:HEX,OCT:{self.load_addr_dm_data:08x} +compSize = INTEGER:{imagesize_dm_data} +shaType = OID:{self.sha_type} +shaValue = FORMAT:HEX,OCT:{hashval_dm_data}""" + + self.total_size = self.imagesize_sbl + self.imagesize_sysfw + self.imagesize_sysfw_data + imagesize_sysfw_inner_cert + imagesize_dm_data + return super().GetCertificate(required=required, type='rom-combined') + + def GetCertificate(self, required): + """Get the contents of this entry + + Args: + required: True if the data must be present, False if it is OK to + return None + + Returns: + bytes content of the entry, which is the certificate binary for the + provided data + """ + if self.combined: + return self.CombinedGetCertificate(required) + else: + return self.NonCombinedGetCertificate(required) + + def ObtainContents(self): + data = self.data + if data is None: + data = self.GetCertificate(False) + if data is None: + return False + self.SetContents(data) + return True + + def ProcessContents(self): + # The blob may have changed due to WriteSymbols() + data = self.data + return self.ProcessContentsUpdate(data) + + def AddBintools(self, btools): + super().AddBintools(btools) + self.openssl = self.AddBintool(btools, 'openssl') diff --git a/tools/binman/etype/x509_cert.py b/tools/binman/etype/x509_cert.py index f80a6ec2d1..d028cfe38c 100644 --- a/tools/binman/etype/x509_cert.py +++ b/tools/binman/etype/x509_cert.py @@ -31,6 +31,26 @@ class Entry_x509_cert(Entry_collection): def __init__(self, section, etype, node): super().__init__(section, etype, node) self.openssl = None + self.req_dist_name = None + self.cert_type = None + self.bootcore = None + self.bootcore_opts = None + self.load_addr = None + self.sha = None + self.total_size = None + self.num_comps = None + self.sysfw_inner_cert_ext_boot_sequence_string = None + self.dm_data_ext_boot_sequence_string = None + self.imagesize_sbl = None + self.hashval_sbl = None + self.load_addr_sysfw = None + self.imagesize_sysfw = None + self.hashval_sysfw = None + self.load_addr_sysfw_data = None + self.imagesize_sysfw_data = None + self.hashval_sysfw_data = None + self.sysfw_inner_cert_ext_boot_block = None + self.dm_data_ext_boot_block = None def ReadNode(self): super().ReadNode() @@ -38,13 +58,16 @@ class Entry_x509_cert(Entry_collection): self._cert_rev = fdt_util.GetInt(self._node, 'cert-revision-int', 0) self.key_fname = self.GetEntryArgsOrProps([ EntryArg('keyfile', str)], required=True)[0] + self.sw_rev = fdt_util.GetInt(self._node, 'sw-rev', 1) - def GetCertificate(self, required): + def GetCertificate(self, required, type='generic'): """Get the contents of this entry Args: required: True if the data must be present, False if it is OK to return None + type: Type of x509 certificate to generate, current supported ones are + 'generic', 'sysfw', 'rom' Returns: bytes content of the entry, which is the signed vblock for the @@ -60,13 +83,61 @@ class Entry_x509_cert(Entry_collection): input_fname = tools.get_output_filename('input.%s' % uniq) config_fname = tools.get_output_filename('config.%s' % uniq) tools.write_file(input_fname, input_data) - stdout = self.openssl.x509_cert( - cert_fname=output_fname, - input_fname=input_fname, - key_fname=self.key_fname, - cn=self._cert_ca, - revision=self._cert_rev, - config_fname=config_fname) + if type == 'generic': + stdout = self.openssl.x509_cert( + cert_fname=output_fname, + input_fname=input_fname, + key_fname=self.key_fname, + cn=self._cert_ca, + revision=self._cert_rev, + config_fname=config_fname) + elif type == 'sysfw': + stdout = self.openssl.x509_cert_sysfw( + cert_fname=output_fname, + input_fname=input_fname, + key_fname=self.key_fname, + config_fname=config_fname, + sw_rev=self.sw_rev, + req_dist_name_dict=self.req_dist_name) + elif type == 'rom': + stdout = self.openssl.x509_cert_rom( + cert_fname=output_fname, + input_fname=input_fname, + key_fname=self.key_fname, + config_fname=config_fname, + sw_rev=self.sw_rev, + req_dist_name_dict=self.req_dist_name, + cert_type=self.cert_type, + bootcore=self.bootcore, + bootcore_opts=self.bootcore_opts, + load_addr=self.load_addr, + sha=self.sha + ) + elif type == 'rom-combined': + stdout = self.openssl.x509_cert_rom_combined( + cert_fname=output_fname, + input_fname=input_fname, + key_fname=self.key_fname, + config_fname=config_fname, + sw_rev=self.sw_rev, + req_dist_name_dict=self.req_dist_name, + load_addr=self.load_addr, + sha=self.sha, + total_size=self.total_size, + num_comps=self.num_comps, + sysfw_inner_cert_ext_boot_sequence_string=self.sysfw_inner_cert_ext_boot_sequence_string, + dm_data_ext_boot_sequence_string=self.dm_data_ext_boot_sequence_string, + imagesize_sbl=self.imagesize_sbl, + hashval_sbl=self.hashval_sbl, + load_addr_sysfw=self.load_addr_sysfw, + imagesize_sysfw=self.imagesize_sysfw, + hashval_sysfw=self.hashval_sysfw, + load_addr_sysfw_data=self.load_addr_sysfw_data, + imagesize_sysfw_data=self.imagesize_sysfw_data, + hashval_sysfw_data=self.hashval_sysfw_data, + sysfw_inner_cert_ext_boot_block=self.sysfw_inner_cert_ext_boot_block, + dm_data_ext_boot_block=self.dm_data_ext_boot_block + ) if stdout is not None: data = tools.read_file(output_fname) else: diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index b9a490a5bd..f4bff50aaf 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -98,6 +98,7 @@ PRE_LOAD_MAGIC = b'UBSH' PRE_LOAD_VERSION = 0x11223344.to_bytes(4, 'big') PRE_LOAD_HDR_SIZE = 0x00001000.to_bytes(4, 'big') TI_BOARD_CONFIG_DATA = b'\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00' +TI_UNSECURE_DATA = b'unsecuredata' # Subdirectory of the input dir to use to put test FDTs TEST_FDT_SUBDIR = 'fdts' @@ -211,6 +212,7 @@ class TestFunctional(unittest.TestCase): TestFunctional._MakeInputFile('fw_dynamic.bin', OPENSBI_DATA) TestFunctional._MakeInputFile('scp.bin', SCP_DATA) TestFunctional._MakeInputFile('rockchip-tpl.bin', ROCKCHIP_TPL_DATA) + TestFunctional._MakeInputFile('ti_unsecure.bin', TI_UNSECURE_DATA) # Add a few .dtb files for testing TestFunctional._MakeInputFile('%s/test-fdt1.dtb' % TEST_FDT_SUBDIR, @@ -6697,5 +6699,55 @@ fdt fdtmap Extract the devicetree blob from the fdtmap data = self._DoReadFile('279_ti_board_cfg_no_type.dts') self.assertIn("Schema validation error", str(e.exception)) + def testPackTiSecure(self): + """Test that an image with a TI secured binary can be created""" + keyfile = self.TestFile('key.key') + entry_args = { + 'keyfile': keyfile, + } + data = self._DoReadFileDtb('279_ti_secure.dts', + entry_args=entry_args)[0] + self.assertGreater(len(data), len(TI_UNSECURE_DATA)) + + def testPackTiSecureMissingTool(self): + """Test that an image with a TI secured binary (non-functional) can be created + when openssl is missing""" + keyfile = self.TestFile('key.key') + entry_args = { + 'keyfile': keyfile, + } + with test_util.capture_sys_output() as (_, stderr): + self._DoTestFile('279_ti_secure.dts', + force_missing_bintools='openssl', + entry_args=entry_args) + err = stderr.getvalue() + self.assertRegex(err, "Image 'image'.*missing bintools.*: openssl") + + def testPackTiSecureROM(self): + """Test that a ROM image with a TI secured binary can be created""" + keyfile = self.TestFile('key.key') + entry_args = { + 'keyfile': keyfile, + } + data = self._DoReadFileDtb('280_ti_secure_rom.dts', + entry_args=entry_args)[0] + data_a = self._DoReadFileDtb('288_ti_secure_rom_a.dts', + entry_args=entry_args)[0] + data_b = self._DoReadFileDtb('289_ti_secure_rom_b.dts', + entry_args=entry_args)[0] + self.assertGreater(len(data), len(TI_UNSECURE_DATA)) + self.assertGreater(len(data_a), len(TI_UNSECURE_DATA)) + self.assertGreater(len(data_b), len(TI_UNSECURE_DATA)) + + def testPackTiSecureROMCombined(self): + """Test that a ROM image with a TI secured binary can be created""" + keyfile = self.TestFile('key.key') + entry_args = { + 'keyfile': keyfile, + } + data = self._DoReadFileDtb('281_ti_secure_rom_combined.dts', + entry_args=entry_args)[0] + self.assertGreater(len(data), len(TI_UNSECURE_DATA)) + if __name__ == "__main__": unittest.main() diff --git a/tools/binman/test/279_ti_secure.dts b/tools/binman/test/279_ti_secure.dts new file mode 100644 index 0000000000..941d0ab4ca --- /dev/null +++ b/tools/binman/test/279_ti_secure.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + ti-secure { + content = <&unsecure_binary>; + }; + unsecure_binary: blob-ext { + filename = "ti_unsecure.bin"; + }; + }; +}; diff --git a/tools/binman/test/280_ti_secure_rom.dts b/tools/binman/test/280_ti_secure_rom.dts new file mode 100644 index 0000000000..d1313769f4 --- /dev/null +++ b/tools/binman/test/280_ti_secure_rom.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + ti-secure-rom { + content = <&unsecure_binary>; + }; + unsecure_binary: blob-ext { + filename = "ti_unsecure.bin"; + }; + }; +}; diff --git a/tools/binman/test/281_ti_secure_rom_combined.dts b/tools/binman/test/281_ti_secure_rom_combined.dts new file mode 100644 index 0000000000..bf872739bc --- /dev/null +++ b/tools/binman/test/281_ti_secure_rom_combined.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + ti-secure-rom { + content = <&unsecure_binary>; + content-sbl = <&unsecure_binary>; + content-sysfw = <&unsecure_binary>; + content-sysfw-data = <&unsecure_binary>; + content-sysfw-inner-cert = <&unsecure_binary>; + content-dm-data = <&unsecure_binary>; + combined; + sysfw-inner-cert; + dm-data; + }; + unsecure_binary: blob-ext { + filename = "ti_unsecure.bin"; + }; + }; +}; diff --git a/tools/binman/test/288_ti_secure_rom_a.dts b/tools/binman/test/288_ti_secure_rom_a.dts new file mode 100644 index 0000000000..887138f0e4 --- /dev/null +++ b/tools/binman/test/288_ti_secure_rom_a.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + ti-secure-rom { + content = <&unsecure_binary>; + core = "secure"; + countersign; + }; + unsecure_binary: blob-ext { + filename = "ti_unsecure.bin"; + }; + }; +}; diff --git a/tools/binman/test/289_ti_secure_rom_b.dts b/tools/binman/test/289_ti_secure_rom_b.dts new file mode 100644 index 0000000000..c6d6182158 --- /dev/null +++ b/tools/binman/test/289_ti_secure_rom_b.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + ti-secure-rom { + content = <&unsecure_binary>; + core = "public"; + }; + unsecure_binary: blob-ext { + filename = "ti_unsecure.bin"; + }; + }; +}; From patchwork Fri Jul 21 18:44:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811078 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com 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15.1.2507.23 via Frontend Transport; Fri, 21 Jul 2023 13:45:13 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloK131068; Fri, 21 Jul 2023 13:45:07 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 03/23] arm: dts: k3: Add support for packaging sysfw.itb and tiboot3.bin Date: Sat, 22 Jul 2023 00:14:26 +0530 Message-ID: <20230721184446.5821-4-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Board config binary artifacts must be generated to be used by binman to package sysfw.itb and tiboot3.bin for all K3 devices. For devices that follow combined flow, these board configuration binaries must again be packaged into a combined board configuration blobs to be used by binman to package tiboot3.bin. Add common k3-binman.dtsi to generate all the board configuration binaries needed. Also add custMpk.pem and ti-degenerate-key.pem needed for signing GP and HS bootloader images common to all K3 devices. Reviewed-by: Simon Glass Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-binman.dtsi | 116 ++++++++++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) create mode 100644 arch/arm/dts/k3-binman.dtsi diff --git a/arch/arm/dts/k3-binman.dtsi b/arch/arm/dts/k3-binman.dtsi new file mode 100644 index 0000000000..2a67cebf94 --- /dev/null +++ b/arch/arm/dts/k3-binman.dtsi @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/ { + binman: binman { + multiple-images; + }; +}; + +&binman { + custMpk { + filename = "custMpk.pem"; + blob-ext { + filename = "../keys/custMpk.pem"; + }; + }; + + ti-degenerate-key { + filename = "ti-degenerate-key.pem"; + blob-ext { + filename = "../keys/ti-degenerate-key.pem"; + }; + }; +}; + +#ifndef CONFIG_ARM64 + +&binman { + board-cfg { + filename = "board-cfg.bin"; + bcfg_yaml: ti-board-config { + config = "board-cfg.yaml"; + schema = "../common/schema.yaml"; + }; + }; + pm-cfg { + filename = "pm-cfg.bin"; + rcfg_yaml: ti-board-config { + config = "pm-cfg.yaml"; + schema = "../common/schema.yaml"; + }; + }; + rm-cfg { + filename = "rm-cfg.bin"; + pcfg_yaml: ti-board-config { + config = "rm-cfg.yaml"; + schema = "../common/schema.yaml"; + }; + }; + sec-cfg { + filename = "sec-cfg.bin"; + scfg_yaml: ti-board-config { + config = "sec-cfg.yaml"; + schema = "../common/schema.yaml"; + }; + }; + combined-tifs-cfg { + filename = "combined-tifs-cfg.bin"; + ti-board-config { + bcfg_yaml_tifs: board-cfg { + config = "board-cfg.yaml"; + schema = "../common/schema.yaml"; + }; + scfg_yaml_tifs: sec-cfg { + config = "sec-cfg.yaml"; + schema = "../common/schema.yaml"; + }; + pcfg_yaml_tifs: pm-cfg { + config = "pm-cfg.yaml"; + schema = "../common/schema.yaml"; + }; + rcfg_yaml_tifs: rm-cfg { + config = "rm-cfg.yaml"; + schema = "../common/schema.yaml"; + }; + }; + }; + combined-dm-cfg { + filename = "combined-dm-cfg.bin"; + ti-board-config { + pcfg_yaml_dm: pm-cfg { + config = "pm-cfg.yaml"; + schema = "../common/schema.yaml"; + }; + rcfg_yaml_dm: rm-cfg { + config = "rm-cfg.yaml"; + schema = "../common/schema.yaml"; + }; + }; + }; + combined-sysfw-cfg { + filename = "combined-sysfw-cfg.bin"; + ti-board-config { + board-cfg { + config = "board-cfg.yaml"; + schema = "../common/schema.yaml"; + }; + sec-cfg { + config = "sec-cfg.yaml"; + schema = "../common/schema.yaml"; + }; + pm-cfg { + config = "pm-cfg.yaml"; + schema = "../common/schema.yaml"; + }; + rm-cfg { + config = "rm-cfg.yaml"; + schema = "../common/schema.yaml"; + }; + }; + }; +}; + +#endif From patchwork Fri Jul 21 18:44:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811109 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Fri, 21 Jul 2023 13:45:20 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloL131068; Fri, 21 Jul 2023 13:45:14 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 04/23] j721e: schema: yaml: Add general schema and J721E board config files Date: Sat, 22 Jul 2023 00:14:27 +0530 Message-ID: <20230721184446.5821-5-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Mailman-Approved-At: Fri, 21 Jul 2023 21:38:23 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Schema file in YAML must be provided in board/ti/common for validating input config files and packaging system firmware. The schema includes entries for rm-cfg, board-cfg, pm-cfg and sec-cfg. Board config files must be provided in board/ti/ in YAML. These can then be consumed for generation of binaries to package system firmware. Added YAML configs for J721E in particular. Signed-off-by: Tarun Sahu [n-francis@ti.com: prepared patch for upstreaming] Signed-off-by: Neha Malcom Francis --- board/ti/common/schema.yaml | 436 +++++ board/ti/j721e/board-cfg.yaml | 36 + board/ti/j721e/pm-cfg.yaml | 12 + board/ti/j721e/rm-cfg.yaml | 3174 +++++++++++++++++++++++++++++++++ board/ti/j721e/sec-cfg.yaml | 380 ++++ 5 files changed, 4038 insertions(+) create mode 100644 board/ti/common/schema.yaml create mode 100644 board/ti/j721e/board-cfg.yaml create mode 100644 board/ti/j721e/pm-cfg.yaml create mode 100644 board/ti/j721e/rm-cfg.yaml create mode 100644 board/ti/j721e/sec-cfg.yaml diff --git a/board/ti/common/schema.yaml b/board/ti/common/schema.yaml new file mode 100644 index 0000000000..c8dd2e79e7 --- /dev/null +++ b/board/ti/common/schema.yaml @@ -0,0 +1,436 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Config schema for TI K3 devices +# + +--- + +definitions: + u8: + type: integer + minimum: 0 + maximum: 0xff + u16: + type: integer + minimum: 0 + maximum: 0xffff + u32: + type: integer + minimum: 0 + maximum: 0xffffffff + + + +type: object +properties: + pm-cfg: + type: object + properties: + rev: + type: object + properties: + boardcfg_abi_maj: + $ref: "#/definitions/u8" + boardcfg_abi_min: + $ref: "#/definitions/u8" + board-cfg: + type: object + properties: + rev: + type: object + properties: + boardcfg_abi_maj: + $ref: "#/definitions/u8" + boardcfg_abi_min: + $ref: "#/definitions/u8" + control: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + main_isolation_enable: + $ref: "#/definitions/u8" + main_isolation_hostid: + $ref: "#/definitions/u16" + + + secproxy: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + scaling_factor: + $ref: "#/definitions/u8" + scaling_profile: + $ref: "#/definitions/u8" + disable_main_nav_secure_proxy: + $ref: "#/definitions/u8" + + msmc: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + msmc_cache_size: + $ref: "#/definitions/u8" + debug_cfg: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + trace_dst_enables: + $ref: "#/definitions/u16" + trace_src_enables: + $ref: "#/definitions/u16" + + sec-cfg: + type: object + properties: + rev: + type: object + properties: + boardcfg_abi_maj: + $ref: "#/definitions/u8" + boardcfg_abi_min: + $ref: "#/definitions/u8" + + processor_acl_list: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + proc_acl_entries: + type: array + minItems: 32 + maxItems: 32 + items: + type: object + properties: + processor_id: + $ref: "#/definitions/u8" + proc_access_master: + $ref: "#/definitions/u8" + proc_access_secondary: + type: array + minItems: 3 + maxItems: 3 + items: + $ref: "#/definitions/u8" + host_hierarchy: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + host_hierarchy_entries: + type: array + minItems: 32 + maxItems: 32 + items: + type: object + properties: + host_id: + $ref: "#/definitions/u8" + supervisor_host_id: + $ref: "#/definitions/u8" + + otp_config: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + otp_entry: + type: array + minItems: 32 + maxItems: 32 + items: + type: object + properties: + host_id: + $ref: "#/definitions/u8" + host_perms: + $ref: "#/definitions/u8" + write_host_id: + $ref: "#/definitions/u8" + + dkek_config: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + allowed_hosts: + type: array + minItems: 4 + maxItems: 4 + items: + $ref: "#/definitions/u8" + allow_dkek_export_tisci: + $ref: "#/definitions/u8" + rsvd: + type: array + minItems: 3 + maxItems: 3 + items: + $ref: "#/definitions/u8" + + sa2ul_cfg: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + rsvd: + type: array + minItems: 2 + maxItems: 4 + items: + $ref: "#/definitions/u8" + enable_saul_psil_global_config_writes: + $ref: "#/definitions/u8" + auth_resource_owner: + $ref: "#/definitions/u8" + + sec_dbg_config: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + allow_jtag_unlock: + $ref: "#/definitions/u8" + allow_wildcard_unlock: + $ref: "#/definitions/u8" + allowed_debug_level_rsvd: + $ref: "#/definitions/u8" + rsvd: + $ref: "#/definitions/u8" + min_cert_rev: + $ref: "#/definitions/u32" + jtag_unlock_hosts: + type: array + minItems: 4 + maxItems: 4 + items: + $ref: "#/definitions/u8" + + + sec_handover_cfg: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + handover_msg_sender: + $ref: "#/definitions/u8" + handover_to_host_id: + $ref: "#/definitions/u8" + rsvd: + type: array + minItems: 4 + maxItems: 4 + items: + $ref: "#/definitions/u8" + + rm-cfg: + type: object + properties: + rm_boardcfg: + type: object + properties: + rev: + type: object + properties: + boardcfg_abi_maj: + $ref: "#/definitions/u8" + boardcfg_abi_min: + $ref: "#/definitions/u8" + + host_cfg: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + host_cfg_entries: + type: array + minItems: 0 + maxItems: 32 + items: + type: object + properties: + host_id: + $ref: "#/definitions/u8" + allowed_atype: + $ref: "#/definitions/u8" + allowed_qos: + $ref: "#/definitions/u16" + allowed_orderid: + $ref: "#/definitions/u32" + allowed_priority: + $ref: "#/definitions/u16" + allowed_sched_priority: + $ref: "#/definitions/u8" + resasg: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + resasg_entries_size: + $ref: "#/definitions/u16" + reserved: + $ref: "#/definitions/u16" + + resasg_entries: + type: array + minItems: 0 + maxItems: 468 + items: + type: object + properties: + start_resource: + $ref: "#/definitions/u16" + num_resource: + $ref: "#/definitions/u16" + type: + $ref: "#/definitions/u16" + host_id: + $ref: "#/definitions/u8" + reserved: + $ref: "#/definitions/u8" + + tifs-rm-cfg: + type: object + properties: + rm_boardcfg: + type: object + properties: + rev: + type: object + properties: + boardcfg_abi_maj: + $ref: "#/definitions/u8" + boardcfg_abi_min: + $ref: "#/definitions/u8" + + host_cfg: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + host_cfg_entries: + type: array + minItems: 0 + maxItems: 32 + items: + type: object + properties: + host_id: + $ref: "#/definitions/u8" + allowed_atype: + $ref: "#/definitions/u8" + allowed_qos: + $ref: "#/definitions/u16" + allowed_orderid: + $ref: "#/definitions/u32" + allowed_priority: + $ref: "#/definitions/u16" + allowed_sched_priority: + $ref: "#/definitions/u8" + resasg: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + resasg_entries_size: + $ref: "#/definitions/u16" + reserved: + $ref: "#/definitions/u16" + + resasg_entries: + type: array + minItems: 0 + maxItems: 468 + items: + type: object + properties: + start_resource: + $ref: "#/definitions/u16" + num_resource: + $ref: "#/definitions/u16" + type: + $ref: "#/definitions/u16" + host_id: + $ref: "#/definitions/u8" + reserved: + $ref: "#/definitions/u8" diff --git a/board/ti/j721e/board-cfg.yaml b/board/ti/j721e/board-cfg.yaml new file mode 100644 index 0000000000..1375dcad35 --- /dev/null +++ b/board/ti/j721e/board-cfg.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for J721E +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable: 0x5A + main_isolation_hostid: 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor: 0x1 + scaling_profile: 0x1 + disable_main_nav_secure_proxy: 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size: 0x0 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables: 0x00 + trace_src_enables: 0x00 diff --git a/board/ti/j721e/pm-cfg.yaml b/board/ti/j721e/pm-cfg.yaml new file mode 100644 index 0000000000..7ae52b3358 --- /dev/null +++ b/board/ti/j721e/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for J721E +# + +--- + +pm-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 diff --git a/board/ti/j721e/rm-cfg.yaml b/board/ti/j721e/rm-cfg.yaml new file mode 100644 index 0000000000..9f604cf1aa --- /dev/null +++ b/board/ti/j721e/rm-cfg.yaml @@ -0,0 +1,3174 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for J721E +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - #1 + host_id: 3 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #2 + host_id: 5 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #3 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #4 + host_id: 13 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #5 + host_id: 21 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #6 + host_id: 26 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #7 + host_id: 28 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #8 + host_id: 35 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #9 + host_id: 37 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #10 + host_id: 40 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #11 + host_id: 42 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + 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15168 + host_id: 5 + reserved: 0 diff --git a/board/ti/j721e/sec-cfg.yaml b/board/ti/j721e/sec-cfg.yaml new file mode 100644 index 0000000000..1eab5883a7 --- /dev/null +++ b/board/ti/j721e/sec-cfg.yaml @@ -0,0 +1,380 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security configuration for J721E +# + +--- + +sec-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - #1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - #1 + host_id: 0 + supervisor_host_id: 0 + - #2 + host_id: 0 + supervisor_host_id: 0 + - #3 + host_id: 0 + supervisor_host_id: 0 + - #4 + host_id: 0 + supervisor_host_id: 0 + - #5 + host_id: 0 + supervisor_host_id: 0 + - #6 + host_id: 0 + supervisor_host_id: 0 + - #7 + host_id: 0 + supervisor_host_id: 0 + - #8 + host_id: 0 + supervisor_host_id: 0 + - #9 + host_id: 0 + supervisor_host_id: 0 + - #10 + host_id: 0 + supervisor_host_id: 0 + - #11 + host_id: 0 + supervisor_host_id: 0 + - #12 + host_id: 0 + supervisor_host_id: 0 + - #13 + host_id: 0 + supervisor_host_id: 0 + - #14 + host_id: 0 + supervisor_host_id: 0 + - #15 + host_id: 0 + supervisor_host_id: 0 + - #16 + host_id: 0 + supervisor_host_id: 0 + - #17 + host_id: 0 + supervisor_host_id: 0 + - #18 + host_id: 0 + supervisor_host_id: 0 + - #19 + host_id: 0 + supervisor_host_id: 0 + - #20 + host_id: 0 + supervisor_host_id: 0 + - #21 + host_id: 0 + supervisor_host_id: 0 + - #22 + host_id: 0 + supervisor_host_id: 0 + - #23 + host_id: 0 + supervisor_host_id: 0 + - #24 + host_id: 0 + supervisor_host_id: 0 + - #25 + host_id: 0 + supervisor_host_id: 0 + - #26 + host_id: 0 + supervisor_host_id: 0 + - #27 + host_id: 0 + supervisor_host_id: 0 + - #28 + host_id: 0 + supervisor_host_id: 0 + - #29 + host_id: 0 + supervisor_host_id: 0 + - #30 + host_id: 0 + supervisor_host_id: 0 + - #31 + host_id: 0 + supervisor_host_id: 0 + - #32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + otp_entry: + - #1 + host_id: 0 + host_perms: 0 + - #2 + host_id: 0 + host_perms: 0 + - #3 + host_id: 0 + host_perms: 0 + - #4 + host_id: 0 + host_perms: 0 + - #5 + host_id: 0 + host_perms: 0 + - #6 + host_id: 0 + host_perms: 0 + - #7 + host_id: 0 + host_perms: 0 + - #8 + host_id: 0 + host_perms: 0 + - #9 + host_id: 0 + host_perms: 0 + - #10 + host_id: 0 + host_perms: 0 + - #11 + host_id: 0 + host_perms: 0 + - #12 + host_id: 0 + host_perms: 0 + - #13 + host_id: 0 + host_perms: 0 + - #14 + host_id: 0 + host_perms: 0 + - #15 + host_id: 0 + host_perms: 0 + - #16 + host_id: 0 + host_perms: 0 + - #17 + host_id: 0 + host_perms: 0 + - #18 + host_id: 0 + host_perms: 0 + - #19 + host_id: 0 + host_perms: 0 + - #20 + host_id: 0 + host_perms: 0 + - #21 + host_id: 0 + host_perms: 0 + - #22 + host_id: 0 + host_perms: 0 + - #23 + host_id: 0 + host_perms: 0 + - #24 + host_id: 0 + host_perms: 0 + - #25 + host_id: 0 + host_perms: 0 + - #26 + host_id: 0 + host_perms: 0 + - #27 + host_id: 0 + host_perms: 0 + - #28 + host_id: 0 + host_perms: 0 + - #29 + host_id: 0 + host_perms: 0 + - #30 + host_id: 0 + host_perms: 0 + - #31 + host_id: 0 + host_perms: 0 + - #32 + host_id: 0 + host_perms: 0 + write_host_id: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci: 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size: 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0 + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock: 0x5A + allow_wildcard_unlock: 0x5A + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev: 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender: 0 + handover_to_host_id: 0 + rsvd: [0, 0, 0, 0] From patchwork Fri Jul 21 18:44:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811079 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: 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with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 21 Jul 2023 13:45:26 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jul 2023 13:45:26 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloM131068; Fri, 21 Jul 2023 13:45:20 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 05/23] j721e: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img Date: Sat, 22 Jul 2023 00:14:28 +0530 Message-ID: <20230721184446.5821-6-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean By providing entries in the binman node of the device tree, binman will be able to find and package board config artifacts generated by TIBoardConfig with sysfw.bin and generate the final image sysfw.itb. It will also pick out the R5 SPL and sign it with the help of TI signing entry and generate the final tiboot3.bin. Entries for A72 build have been added to k3-j721e-binman.dtsi to generate tispl.bin and u-boot.img. Support has been added for both HS-SE(SR 1.1), HS-FS(SR 2.0) and GP images In HS-SE, the encrypted system firmware binary must be signed along with the signed certificate binary. HS-SE: * tiboot3-j721e_sr1_1-hs-evm.bin * sysfw-j721e_sr1_1-hs-evm.itb * tispl.bin * u-boot.img HS-FS: * tiboot3-j721e_sr2-hs-fs-evm.bin * sysfw-j721e_sr2-hs-fs-evm.itb * tispl.bin * u-boot.img GP: * tiboot3.bin -->tiboot3-j721e-gp-evm.bin * sysfw.itb --> sysfw-j721e-gp-evm.itb * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by J721E requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs sysfw.itb: * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-j721e-binman.dtsi | 701 ++++++++++++++++++ .../k3-j721e-common-proc-board-u-boot.dtsi | 1 + .../arm/dts/k3-j721e-r5-common-proc-board.dts | 1 + arch/arm/dts/k3-j721e-sk-u-boot.dtsi | 1 + board/ti/j721e/Kconfig | 2 + 5 files changed, 706 insertions(+) create mode 100644 arch/arm/dts/k3-j721e-binman.dtsi diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi new file mode 100644 index 0000000000..7fb63d6233 --- /dev/null +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -0,0 +1,701 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-binman.dtsi" + +#ifdef CONFIG_TARGET_J721E_R5_EVM + +&binman { + tiboot3-j721e_sr1_1-hs-evm.bin { + filename = "tiboot3-j721e_sr1_1-hs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl>; + core = "public"; + load = ; + keyfile = "custMpk.pem"; + }; + u_boot_spl: u-boot-spl { + no-expanded; + }; + }; + sysfw { + filename = "sysfw.bin"; + ti-secure-rom { + content = <&ti_fs_cert>; + core = "secure"; + load = <0x40000>; + keyfile = "custMpk.pem"; + countersign; + }; + ti_fs_cert: ti-fs-cert.bin { + filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + ti-fs-firmware-j721e_sr1_1-hs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + itb { + filename = "sysfw-j721e_sr1_1-hs-evm.itb"; + fit { + description = "SYSFW and Config fragments"; + #address-cells = <1>; + images { + sysfw.bin { + description = "sysfw"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "sysfw.bin"; + }; + }; + board-cfg.bin { + description = "board-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&board_cfg>; + keyfile = "custMpk.pem"; + }; + board_cfg: board-cfg { + filename = "board-cfg.bin"; + type = "blob-ext"; + }; + + }; + pm-cfg.bin { + description = "pm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&pm_cfg>; + keyfile = "custMpk.pem"; + }; + pm_cfg: pm-cfg { + filename = "pm-cfg.bin"; + type = "blob-ext"; + }; + }; + rm-cfg.bin { + description = "rm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&rm_cfg>; + keyfile = "custMpk.pem"; + }; + rm_cfg: rm-cfg { + filename = "rm-cfg.bin"; + type = "blob-ext"; + }; + }; + sec-cfg.bin { + description = "sec-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&sec_cfg>; + keyfile = "custMpk.pem"; + }; + sec_cfg: sec-cfg { + filename = "sec-cfg.bin"; + type = "blob-ext"; + }; + }; + }; + }; + }; +}; + +&binman { + tiboot3-j721e_sr2-hs-fs-evm.bin { + filename = "tiboot3-j721e_sr2-hs-fs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_fs>; + core = "public"; + load = ; + keyfile = "custMpk.pem"; + }; + u_boot_spl_fs: u-boot-spl { + no-expanded; + }; + }; + sysfw_fs { + filename = "sysfw.bin_fs"; + ti-fs-cert-fs.bin { + filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + ti-fs-firmware-j721e-hs-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + itb_fs { + filename = "sysfw-j721e_sr2-hs-fs-evm.itb"; + fit { + description = "SYSFW and Config fragments"; + #address-cells = <1>; + images { + sysfw.bin { + description = "sysfw"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "sysfw.bin_fs"; + }; + }; + board-cfg.bin { + description = "board-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + board-cfg { + filename = "board-cfg.bin"; + type = "blob-ext"; + }; + + }; + pm-cfg.bin { + description = "pm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + pm-cfg { + filename = "pm-cfg.bin"; + type = "blob-ext"; + }; + }; + rm-cfg.bin { + description = "rm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + rm-cfg { + filename = "rm-cfg.bin"; + type = "blob-ext"; + }; + }; + sec-cfg.bin { + description = "sec-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + sec-cfg { + filename = "sec-cfg.bin"; + type = "blob-ext"; + }; + }; + }; + }; + }; +}; + +&binman { + tiboot3-j721e-gp-evm.bin { + filename = "tiboot3-j721e-gp-evm.bin"; + symlink = "tiboot3.bin"; + ti-secure-rom { + content = <&u_boot_spl_unsigned>; + core = "public"; + load = ; + sw-rev = ; + keyfile = "ti-degenerate-key.pem"; + }; + u_boot_spl_unsigned: u-boot-spl { + no-expanded; + }; + }; + sysfw_gp { + filename = "sysfw.bin_gp"; + ti-secure-rom { + content = <&ti_fs>; + core = "secure"; + load = <0x40000>; + sw-rev = ; + keyfile = "ti-degenerate-key.pem"; + }; + ti_fs: ti-fs.bin { + filename = "ti-sysfw/ti-fs-firmware-j721e-gp.bin"; + type = "blob-ext"; + optional; + }; + }; + itb_gp { + filename = "sysfw-j721e-gp-evm.itb"; + symlink = "sysfw.itb"; + fit { + description = "SYSFW and Config fragments"; + #address-cells = <1>; + images { + sysfw.bin { + description = "sysfw"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "sysfw.bin_gp"; + }; + }; + board-cfg.bin { + description = "board-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "board-cfg.bin"; + }; + }; + pm-cfg.bin { + description = "pm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "pm-cfg.bin"; + }; + }; + rm-cfg.bin { + description = "rm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "rm-cfg.bin"; + }; + }; + sec-cfg.bin { + description = "sec-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "sec-cfg.bin"; + }; + }; + }; + }; + }; +}; +#endif + +#ifdef CONFIG_TARGET_J721E_A72_EVM + +#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" +#define SPL_J721E_EVM_DTB "spl/dts/k3-j721e-common-proc-board.dtb" +#define SPL_J721E_SK_DTB "spl/dts/k3-j721e-sk.dtb" + +#define UBOOT_NODTB "u-boot-nodtb.bin" +#define J721E_EVM_DTB "arch/arm/dts/k3-j721e-common-proc-board.dtb" +#define J721E_SK_DTB "arch/arm/dts/k3-j721e-sk.dtb" + +&binman { + ti-dm { + filename = "ti-dm.bin"; + blob-ext { + filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + ti-spl { + filename = "tispl.bin"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = ; + entry = ; + ti-secure { + content = <&atf>; + keyfile = "custMpk.pem"; + }; + atf: atf-bl31 { + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + ti-secure { + content = <&tee>; + keyfile = "custMpk.pem"; + }; + tee: tee-os { + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + ti-secure { + content = <&dm>; + keyfile = "custMpk.pem"; + }; + dm: blob-ext { + filename = "ti-dm.bin"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = ; + entry = ; + ti-secure { + content = <&u_boot_spl_nodtb>; + keyfile = "custMpk.pem"; + + }; + u_boot_spl_nodtb: blob-ext { + filename = SPL_NODTB; + }; + }; + + fdt-0 { + description = "k3-j721e-common-proc-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_j721e_evm_dtb>; + keyfile = "custMpk.pem"; + }; + spl_j721e_evm_dtb: blob-ext { + filename = SPL_J721E_EVM_DTB; + }; + }; + + fdt-1 { + description = "k3-j721e-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_j721e_sk_dtb>; + keyfile = "custMpk.pem"; + + }; + spl_j721e_sk_dtb: blob-ext { + filename = SPL_J721E_SK_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j721e-common-proc-board"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + + conf-1 { + description = "k3-j721e-sk"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-1"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + filename = "u-boot.img"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for j721e board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = ; + ti-secure { + content = <&u_boot_nodtb>; + keyfile = "custMpk.pem"; + }; + u_boot_nodtb: u-boot-nodtb { + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-j721e-common-proc-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&j721e_evm_dtb>; + keyfile = "custMpk.pem"; + + }; + j721e_evm_dtb: blob-ext { + filename = J721E_EVM_DTB; + }; + hash { + algo = "crc32"; + }; + }; + + fdt-1 { + description = "k3-j721e-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&j721e_sk_dtb>; + keyfile = "custMpk.pem"; + + }; + j721e_sk_dtb: blob-ext { + filename = J721E_SK_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j721e-common-proc-board"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + + conf-1 { + description = "k3-j721e-sk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-1"; + }; + }; + }; + }; +}; + +&binman { + ti-spl_unsigned { + filename = "tispl.bin_unsigned"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = ; + entry = ; + atf-bl31 { + filename = "bl31.bin"; + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + tee-os { + filename = "tee-raw.bin"; + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + blob-ext { + filename = "ti-dm.bin"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = ; + entry = ; + blob-ext { + filename = SPL_NODTB; + }; + }; + + fdt-0 { + description = "k3-j721e-common-proc-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = SPL_J721E_EVM_DTB; + }; + }; + + fdt-1 { + description = "k3-j721e-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = SPL_J721E_SK_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j721e-common-proc-board"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + + conf-1 { + description = "k3-j721e-sk"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-1"; + }; + }; + }; + }; +}; + +&binman { + u-boot_unsigned { + filename = "u-boot.img_unsigned"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for j721e board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = ; + blob { + filename = UBOOT_NODTB; + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-j721e-common-proc-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = J721E_EVM_DTB; + }; + hash { + algo = "crc32"; + }; + }; + + fdt-1 { + description = "k3-j721e-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = J721E_SK_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j721e-common-proc-board"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + + conf-1 { + description = "k3-j721e-sk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-1"; + }; + }; + }; + }; +}; +#endif diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 867ec2bb1a..540c847eb3 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include +#include "k3-j721e-binman.dtsi" / { chosen { diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 1b40cf2580..32f71e9b6a 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -8,6 +8,7 @@ #include "k3-j721e-som-p0.dtsi" #include "k3-j721e-ddr-evm-lp4-4266.dtsi" #include "k3-j721e-ddr.dtsi" +#include "k3-j721e-binman.dtsi" #include / { diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi index 31f979f3bb..205dacff4d 100644 --- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include +#include "k3-j721e-binman.dtsi" / { chosen { diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig index 84bca32712..4a127c4a10 100644 --- a/board/ti/j721e/Kconfig +++ b/board/ti/j721e/Kconfig @@ -13,6 +13,7 @@ config TARGET_J721E_A72_EVM select BOARD_LATE_INIT imply TI_I2C_BOARD_DETECT select SYS_DISABLE_DCACHE_OPS + select BINMAN config TARGET_J721E_R5_EVM bool "TI K3 based J721E EVM running on R5" @@ -22,6 +23,7 @@ config TARGET_J721E_R5_EVM select RAM select SPL_RAM select K3_DDRSS + select BINMAN imply SYS_K3_SPL_ATF imply TI_I2C_BOARD_DETECT From patchwork Fri Jul 21 18:44:29 2023 Content-Type: text/plain; charset="utf-8" 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[10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 36LIjXAY093256 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 21 Jul 2023 13:45:33 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 21 Jul 2023 13:45:32 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jul 2023 13:45:32 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloN131068; Fri, 21 Jul 2023 13:45:27 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 06/23] j7200: yaml: Add J7200 board config files Date: Sat, 22 Jul 2023 00:14:29 +0530 Message-ID: <20230721184446.5821-7-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Added YAML configs for J7200 Signed-off-by: Neha Malcom Francis --- board/ti/j721e/board-cfg_j7200.yaml | 36 + board/ti/j721e/pm-cfg_j7200.yaml | 12 + board/ti/j721e/rm-cfg_j7200.yaml | 2065 +++++++++++++++++++++++++++ board/ti/j721e/sec-cfg_j7200.yaml | 380 +++++ 4 files changed, 2493 insertions(+) create mode 100644 board/ti/j721e/board-cfg_j7200.yaml create mode 100644 board/ti/j721e/pm-cfg_j7200.yaml create mode 100644 board/ti/j721e/rm-cfg_j7200.yaml create mode 100644 board/ti/j721e/sec-cfg_j7200.yaml diff --git a/board/ti/j721e/board-cfg_j7200.yaml b/board/ti/j721e/board-cfg_j7200.yaml new file mode 100644 index 0000000000..0ac1ae93fe --- /dev/null +++ b/board/ti/j721e/board-cfg_j7200.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for J7200 +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable : 0x5A + main_isolation_hostid : 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor : 0x1 + scaling_profile : 0x1 + disable_main_nav_secure_proxy : 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size : 0x10 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables : 0x00 + trace_src_enables : 0x00 diff --git a/board/ti/j721e/pm-cfg_j7200.yaml b/board/ti/j721e/pm-cfg_j7200.yaml new file mode 100644 index 0000000000..daaefb1318 --- /dev/null +++ b/board/ti/j721e/pm-cfg_j7200.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for J7200 +# + +--- + +pm-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 diff --git a/board/ti/j721e/rm-cfg_j7200.yaml b/board/ti/j721e/rm-cfg_j7200.yaml new file mode 100644 index 0000000000..263285ff42 --- /dev/null +++ b/board/ti/j721e/rm-cfg_j7200.yaml @@ -0,0 +1,2065 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for J7200 +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size : 356 + host_cfg_entries: + - #1 + host_id: 3 + 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/dev/null +++ b/board/ti/j721e/sec-cfg_j7200.yaml @@ -0,0 +1,380 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security management configuration for J7200 +# + +--- + +sec-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - #1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - #1 + host_id: 0 + supervisor_host_id: 0 + - #2 + host_id: 0 + supervisor_host_id: 0 + - #3 + host_id: 0 + supervisor_host_id: 0 + - #4 + host_id: 0 + supervisor_host_id: 0 + - #5 + host_id: 0 + supervisor_host_id: 0 + - #6 + host_id: 0 + supervisor_host_id: 0 + - #7 + host_id: 0 + supervisor_host_id: 0 + - #8 + host_id: 0 + supervisor_host_id: 0 + - #9 + host_id: 0 + supervisor_host_id: 0 + - #10 + host_id: 0 + supervisor_host_id: 0 + - #11 + host_id: 0 + supervisor_host_id: 0 + - #12 + host_id: 0 + supervisor_host_id: 0 + - #13 + host_id: 0 + supervisor_host_id: 0 + - #14 + host_id: 0 + supervisor_host_id: 0 + - #15 + host_id: 0 + supervisor_host_id: 0 + - #16 + host_id: 0 + supervisor_host_id: 0 + - #17 + host_id: 0 + supervisor_host_id: 0 + - #18 + host_id: 0 + supervisor_host_id: 0 + - #19 + host_id: 0 + supervisor_host_id: 0 + - #20 + host_id: 0 + supervisor_host_id: 0 + - #21 + host_id: 0 + supervisor_host_id: 0 + - #22 + host_id: 0 + supervisor_host_id: 0 + - #23 + host_id: 0 + supervisor_host_id: 0 + - #24 + host_id: 0 + supervisor_host_id: 0 + - #25 + host_id: 0 + supervisor_host_id: 0 + - #26 + host_id: 0 + supervisor_host_id: 0 + - #27 + host_id: 0 + supervisor_host_id: 0 + - #28 + host_id: 0 + supervisor_host_id: 0 + - #29 + host_id: 0 + supervisor_host_id: 0 + - #30 + host_id: 0 + supervisor_host_id: 0 + - #31 + host_id: 0 + supervisor_host_id: 0 + - #32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + write_host_id : 0 + otp_entry: + - #1 + host_id: 0 + host_perms: 0 + - #2 + host_id: 0 + host_perms: 0 + - #3 + host_id: 0 + host_perms: 0 + - #4 + host_id: 0 + host_perms: 0 + - #5 + host_id: 0 + host_perms: 0 + - #6 + host_id: 0 + host_perms: 0 + - #7 + host_id: 0 + host_perms: 0 + - #8 + host_id: 0 + host_perms: 0 + - #9 + host_id: 0 + host_perms: 0 + - #10 + host_id: 0 + host_perms: 0 + - #11 + host_id: 0 + host_perms: 0 + - #12 + host_id: 0 + host_perms: 0 + - #13 + host_id: 0 + host_perms: 0 + - #14 + host_id: 0 + host_perms: 0 + - #15 + host_id: 0 + host_perms: 0 + - #16 + host_id: 0 + host_perms: 0 + - #17 + host_id: 0 + host_perms: 0 + - #18 + host_id: 0 + host_perms: 0 + - #19 + host_id: 0 + host_perms: 0 + - #20 + host_id: 0 + host_perms: 0 + - #21 + host_id: 0 + host_perms: 0 + - #22 + host_id: 0 + host_perms: 0 + - #23 + host_id: 0 + host_perms: 0 + - #24 + host_id: 0 + host_perms: 0 + - #25 + host_id: 0 + host_perms: 0 + - #26 + host_id: 0 + host_perms: 0 + - #27 + host_id: 0 + host_perms: 0 + - #28 + host_id: 0 + host_perms: 0 + - #29 + host_id: 0 + host_perms: 0 + - #30 + host_id: 0 + host_perms: 0 + - #31 + host_id: 0 + host_perms: 0 + - #32 + host_id: 0 + host_perms: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci : 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size : 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0 + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock : 0x5A + allow_wildcard_unlock : 0x5A + allowed_debug_level_rsvd : 0 + rsvd : 0 + min_cert_rev : 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender : 0 + handover_to_host_id : 0 + rsvd: [0, 0, 0, 0] From patchwork Fri Jul 21 18:44:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811081 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de 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cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 21 Jul 2023 13:45:39 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jul 2023 13:45:39 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloO131068; Fri, 21 Jul 2023 13:45:33 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 07/23] j7200: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img Date: Sat, 22 Jul 2023 00:14:30 +0530 Message-ID: <20230721184446.5821-8-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Support has been added for both HS-SE(SR 2.0), HS-FS(SR 2.0) and GP images. HS-SE: * tiboot3-j7200_sr2-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-j7200_sr2-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-j7200-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by J7200 requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-j7200-binman.dtsi | 502 ++++++++++++++++++ .../k3-j7200-common-proc-board-u-boot.dtsi | 2 + board/ti/j721e/Kconfig | 2 + 3 files changed, 506 insertions(+) create mode 100644 arch/arm/dts/k3-j7200-binman.dtsi diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi new file mode 100644 index 0000000000..613aca5950 --- /dev/null +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -0,0 +1,502 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-binman.dtsi" + +#ifdef CONFIG_TARGET_J7200_R5_EVM + +&bcfg_yaml { + config = "board-cfg_j7200.yaml"; +}; + +&rcfg_yaml { + config = "rm-cfg_j7200.yaml"; +}; + +&pcfg_yaml { + config = "pm-cfg_j7200.yaml"; +}; + +&scfg_yaml { + config = "sec-cfg_j7200.yaml"; +}; + +&bcfg_yaml_tifs { + config = "board-cfg_j7200.yaml"; +}; + +&rcfg_yaml_tifs { + config = "rm-cfg_j7200.yaml"; +}; + +&pcfg_yaml_tifs { + config = "pm-cfg_j7200.yaml"; +}; + +&scfg_yaml_tifs { + config = "sec-cfg_j7200.yaml"; +}; + +&rcfg_yaml_dm { + config = "rm-cfg_j7200.yaml"; +}; + +&pcfg_yaml_dm { + config = "pm-cfg_j7200.yaml"; +}; + +&binman { + tiboot3-j7200_sr2-hs-evm.bin { + filename = "tiboot3-j7200_sr2-hs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>, + <&combined_dm_cfg>, <&sysfw_inner_cert>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl>; + content-sysfw = <&ti_fs_enc>; + content-sysfw-data = <&combined_tifs_cfg>; + content-sysfw-inner-cert = <&sysfw_inner_cert>; + content-dm-data = <&combined_dm_cfg>; + load = <0x41c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x7f000>; + load-dm-data = <0x41c80000>; + }; + u_boot_spl: u-boot-spl { + no-expanded; + }; + ti_fs_enc: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j7200_sr2-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-j7200_sr2-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { + tiboot3-j7200_sr2-hs-fs-evm.bin { + filename = "tiboot3-j7200_sr2-hs-fs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>, + <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs>; + content-sysfw = <&ti_fs_enc_fs>; + content-sysfw-data = <&combined_tifs_cfg_fs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; + content-dm-data = <&combined_dm_cfg_fs>; + load = <0x41c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x7f000>; + load-dm-data = <0x41c80000>; + }; + u_boot_spl_fs: u-boot-spl { + no-expanded; + }; + ti_fs_enc_fs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j7200_sr2-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_fs: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert_fs: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-j7200_sr2-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg_fs: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { + tiboot3-j7200-gp-evm.bin { + filename = "tiboot3-j7200-gp-evm.bin"; + symlink = "tiboot3.bin"; + ti-secure-rom { + content = <&u_boot_spl_unsigned>, <&ti_fs_gp>, + <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; + combined; + dm-data; + content-sbl = <&u_boot_spl_unsigned>; + load = <0x41c00000>; + content-sysfw = <&ti_fs_gp>; + load-sysfw = <0x40000>; + content-sysfw-data = <&combined_tifs_cfg_gp>; + load-sysfw-data = <0x7f000>; + content-dm-data = <&combined_dm_cfg_gp>; + load-dm-data = <0x41c80000>; + sw-rev = <1>; + keyfile = "ti-degenerate-key.pem"; + }; + u_boot_spl_unsigned: u-boot-spl { + no-expanded; + }; + ti_fs_gp: ti-fs-gp.bin { + filename = "ti-sysfw/ti-fs-firmware-j7200-gp.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + combined_dm_cfg_gp: combined-dm-cfg-gp.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +#endif + +#ifdef CONFIG_TARGET_J7200_A72_EVM + +#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" +#define SPL_J7200_EVM_DTB "spl/dts/k3-j7200-common-proc-board.dtb" + +#define UBOOT_NODTB "u-boot-nodtb.bin" +#define J7200_EVM_DTB "arch/arm/dts/k3-j7200-common-proc-board.dtb" + +&binman { + ti-dm { + filename = "ti-dm.bin"; + blob-ext { + filename = "ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + ti-spl { + filename = "tispl.bin"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = ; + entry = ; + ti-secure { + content = <&atf>; + keyfile = "custMpk.pem"; + }; + atf: atf-bl31 { + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + ti-secure { + content = <&tee>; + keyfile = "custMpk.pem"; + }; + tee: tee-os { + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + ti-secure { + content = <&dm>; + keyfile = "custMpk.pem"; + }; + + dm: blob-ext { + filename = "ti-dm.bin"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = ; + entry = ; + ti-secure { + content = <&u_boot_spl_nodtb>; + keyfile = "custMpk.pem"; + }; + u_boot_spl_nodtb: blob-ext { + filename = SPL_NODTB; + }; + }; + + fdt-0 { + description = "k3-j7200-common-proc-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_j7200_evm_dtb>; + keyfile = "custMpk.pem"; + }; + spl_j7200_evm_dtb: blob-ext { + filename = SPL_J7200_EVM_DTB; + }; + }; + + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j7200-common-proc-board"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + filename = "u-boot.img"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for J7200 board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = ; + ti-secure { + content = <&u_boot_nodtb>; + keyfile = "custMpk.pem"; + }; + u_boot_nodtb: u-boot-nodtb { + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-j7200-common-proc-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&j7200_evm_dtb>; + keyfile = "custMpk.pem"; + }; + j7200_evm_dtb: blob-ext { + filename = J7200_EVM_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j7200-common-proc-board"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + + }; + }; + }; +}; + +&binman { + ti-spl_unsigned { + filename = "tispl.bin_unsigned"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = ; + entry = ; + atf-bl31 { + filename = "bl31.bin"; + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + tee-os { + filename = "tee-raw.bin"; + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + blob-ext { + filename = "ti-dm.bin"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = ; + entry = ; + blob { + filename = SPL_NODTB; + }; + }; + + fdt-1 { + description = "k3-j7200-common-proc-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = SPL_J7200_EVM_DTB; + }; + }; + }; + + configurations { + default = "conf-1"; + + conf-1 { + description = "k3-j7200-common-proc-board"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-1"; + }; + }; + }; + }; +}; + +&binman { + u-boot_unsigned { + filename = "u-boot.img_unsigned"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for J7200 board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = ; + blob { + filename = UBOOT_NODTB; + }; + hash { + algo = "crc32"; + }; + }; + + fdt-1 { + description = "k3-j7200-common-proc-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = J7200_EVM_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-1"; + + conf-1 { + description = "k3-j7200-common-proc-board"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-1"; + }; + }; + }; + }; +}; +#endif diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index f57c2306ba..f25c7136c9 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ */ +#include "k3-j7200-binman.dtsi" + / { chosen { stdout-path = "serial2:115200n8"; diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig index 4a127c4a10..e6cb21f77b 100644 --- a/board/ti/j721e/Kconfig +++ b/board/ti/j721e/Kconfig @@ -33,6 +33,7 @@ config TARGET_J7200_A72_EVM select BOARD_LATE_INIT imply TI_I2C_BOARD_DETECT select SYS_DISABLE_DCACHE_OPS + select BINMAN config TARGET_J7200_R5_EVM bool "TI K3 based J7200 EVM running on R5" @@ -42,6 +43,7 @@ config TARGET_J7200_R5_EVM select RAM select SPL_RAM select K3_DDRSS + select BINMAN imply SYS_K3_SPL_ATF imply TI_I2C_BOARD_DETECT From patchwork Fri Jul 21 18:44:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811082 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) 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SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jul 2023 13:45:45 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloP131068; Fri, 21 Jul 2023 13:45:39 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 08/23] am65x: yaml: Add AM65x board config files Date: Sat, 22 Jul 2023 00:14:31 +0530 Message-ID: <20230721184446.5821-9-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Added YAML configs for AM65x Signed-off-by: Neha Malcom Francis --- board/ti/am65x/board-cfg.yaml | 36 + board/ti/am65x/pm-cfg.yaml | 12 + board/ti/am65x/rm-cfg.yaml | 2068 +++++++++++++++++++++++++++++++++ board/ti/am65x/sec-cfg.yaml | 379 ++++++ 4 files changed, 2495 insertions(+) create mode 100644 board/ti/am65x/board-cfg.yaml create mode 100644 board/ti/am65x/pm-cfg.yaml create mode 100644 board/ti/am65x/rm-cfg.yaml create mode 100644 board/ti/am65x/sec-cfg.yaml diff --git a/board/ti/am65x/board-cfg.yaml b/board/ti/am65x/board-cfg.yaml new file mode 100644 index 0000000000..a8e06166d5 --- /dev/null +++ b/board/ti/am65x/board-cfg.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for AM65x +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable : 0x5A + main_isolation_hostid : 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor : 0x1 + scaling_profile : 0x1 + disable_main_nav_secure_proxy : 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size : 0x10 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables : 0x00 + trace_src_enables : 0x00 diff --git a/board/ti/am65x/pm-cfg.yaml b/board/ti/am65x/pm-cfg.yaml new file mode 100644 index 0000000000..73fe86c29a --- /dev/null +++ b/board/ti/am65x/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for AM65x +# + +--- + +pm-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 diff --git a/board/ti/am65x/rm-cfg.yaml b/board/ti/am65x/rm-cfg.yaml new file mode 100644 index 0000000000..5903773e81 --- /dev/null +++ b/board/ti/am65x/rm-cfg.yaml @@ -0,0 +1,2068 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM65x +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size : 356 + host_cfg_entries: + - #1 + host_id: 3 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #2 + host_id: 5 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #3 + host_id: 12 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #4 + host_id: 13 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #5 + host_id: 0 + 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reserved: 0 + + - + start_resource: 3 + num_resource: 1 + type: 12490 + host_id: 13 + reserved: 0 + + - + start_resource: 0 + num_resource: 8 + type: 12491 + host_id: 12 + reserved: 0 + + - + start_resource: 8 + num_resource: 8 + type: 12491 + host_id: 3 + reserved: 0 + + - + start_resource: 8 + num_resource: 8 + type: 12491 + host_id: 4 + reserved: 0 + + - + start_resource: 16 + num_resource: 8 + type: 12491 + host_id: 5 + reserved: 0 + + - + start_resource: 24 + num_resource: 8 + type: 12491 + host_id: 128 + reserved: 0 diff --git a/board/ti/am65x/sec-cfg.yaml b/board/ti/am65x/sec-cfg.yaml new file mode 100644 index 0000000000..7fa12f0bed --- /dev/null +++ b/board/ti/am65x/sec-cfg.yaml @@ -0,0 +1,379 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security management configuration for AM65x +# + +--- + +sec-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - #1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - #1 + host_id: 0 + supervisor_host_id: 0 + - #2 + host_id: 0 + supervisor_host_id: 0 + - #3 + host_id: 0 + supervisor_host_id: 0 + - #4 + host_id: 0 + supervisor_host_id: 0 + - #5 + host_id: 0 + supervisor_host_id: 0 + - #6 + host_id: 0 + supervisor_host_id: 0 + - #7 + host_id: 0 + supervisor_host_id: 0 + - #8 + host_id: 0 + supervisor_host_id: 0 + - #9 + host_id: 0 + supervisor_host_id: 0 + - #10 + host_id: 0 + supervisor_host_id: 0 + - #11 + host_id: 0 + supervisor_host_id: 0 + - #12 + host_id: 0 + supervisor_host_id: 0 + - #13 + host_id: 0 + supervisor_host_id: 0 + - #14 + host_id: 0 + supervisor_host_id: 0 + - #15 + host_id: 0 + supervisor_host_id: 0 + - #16 + host_id: 0 + supervisor_host_id: 0 + - #17 + host_id: 0 + supervisor_host_id: 0 + - #18 + host_id: 0 + supervisor_host_id: 0 + - #19 + host_id: 0 + supervisor_host_id: 0 + - #20 + host_id: 0 + supervisor_host_id: 0 + - #21 + host_id: 0 + supervisor_host_id: 0 + - #22 + host_id: 0 + supervisor_host_id: 0 + - #23 + host_id: 0 + supervisor_host_id: 0 + - #24 + host_id: 0 + supervisor_host_id: 0 + - #25 + host_id: 0 + supervisor_host_id: 0 + - #26 + host_id: 0 + supervisor_host_id: 0 + - #27 + host_id: 0 + supervisor_host_id: 0 + - #28 + host_id: 0 + supervisor_host_id: 0 + - #29 + host_id: 0 + supervisor_host_id: 0 + - #30 + host_id: 0 + supervisor_host_id: 0 + - #31 + host_id: 0 + supervisor_host_id: 0 + - #32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + write_host_id : 0 + otp_entry: + - #1 + host_id: 0 + host_perms: 0 + - #2 + host_id: 0 + host_perms: 0 + - #3 + host_id: 0 + host_perms: 0 + - #4 + host_id: 0 + host_perms: 0 + - #5 + host_id: 0 + host_perms: 0 + - #6 + host_id: 0 + host_perms: 0 + - #7 + host_id: 0 + host_perms: 0 + - #8 + host_id: 0 + host_perms: 0 + - #9 + host_id: 0 + host_perms: 0 + - #10 + host_id: 0 + host_perms: 0 + - #11 + host_id: 0 + host_perms: 0 + - #12 + host_id: 0 + host_perms: 0 + - #13 + host_id: 0 + host_perms: 0 + - #14 + host_id: 0 + host_perms: 0 + - #15 + host_id: 0 + host_perms: 0 + - #16 + host_id: 0 + host_perms: 0 + - #17 + host_id: 0 + host_perms: 0 + - #18 + host_id: 0 + host_perms: 0 + - #19 + host_id: 0 + host_perms: 0 + - #20 + host_id: 0 + host_perms: 0 + - #21 + host_id: 0 + host_perms: 0 + - #22 + host_id: 0 + host_perms: 0 + - #23 + host_id: 0 + host_perms: 0 + - #24 + host_id: 0 + host_perms: 0 + - #25 + host_id: 0 + host_perms: 0 + - #26 + host_id: 0 + host_perms: 0 + - #27 + host_id: 0 + host_perms: 0 + - #28 + host_id: 0 + host_perms: 0 + - #29 + host_id: 0 + host_perms: 0 + - #30 + host_id: 0 + host_perms: 0 + - #31 + host_id: 0 + host_perms: 0 + - #32 + host_id: 0 + host_perms: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci : 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size : 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0 + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock : 0x5A + allow_wildcard_unlock : 0x5A + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev : 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender : 0 + handover_to_host_id : 0 + rsvd: [0, 0, 0, 0] From patchwork Fri Jul 21 18:44:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811083 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=nLFv9cOB; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de 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(ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloQ131068; Fri, 21 Jul 2023 13:45:46 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 09/23] am65: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img Date: Sat, 22 Jul 2023 00:14:32 +0530 Message-ID: <20230721184446.5821-10-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Support has been added for both HS-SE(SR 2.0) and GP(SR 2.0) images. HS-SE: * tiboot3-am65x_sr2-hs-evm.bin * sysfw-am65x_sr2-hs-evm.itb * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am65x_sr2-gp-evm.bin * sysfw.itb --> sysfw-am65x_sr2-gp-evm.itb * tispl.bin_unsigned * u-boot.img_unsigned Note that the bootflow followed by AM65x requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs sysfw.itb: * sysfw * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * ATF * OP-TEE * A53 SPL * A53 SPL dtbs u-boot.img: * A53 U-Boot * A53 U-Boot dtbs Reviewed-by: Simon Glass [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 1 + .../dts/k3-am654-r5-base-board-u-boot.dtsi | 1 + arch/arm/dts/k3-am65x-binman.dtsi | 518 ++++++++++++++++++ board/ti/am65x/Kconfig | 2 + 4 files changed, 522 insertions(+) create mode 100644 arch/arm/dts/k3-am65x-binman.dtsi diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index 0c1305df7e..e4cbc47c2a 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include "k3-am654-r5-base-board-u-boot.dtsi" +#include "k3-am65x-binman.dtsi" &pru0_0 { remoteproc-name = "pru0_0"; diff --git a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi index 4516ab1437..949320c91d 100644 --- a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi @@ -5,6 +5,7 @@ #include #include +#include "k3-am65x-binman.dtsi" / { chosen { diff --git a/arch/arm/dts/k3-am65x-binman.dtsi b/arch/arm/dts/k3-am65x-binman.dtsi new file mode 100644 index 0000000000..4bf08451b4 --- /dev/null +++ b/arch/arm/dts/k3-am65x-binman.dtsi @@ -0,0 +1,518 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-binman.dtsi" + +#ifdef CONFIG_TARGET_AM654_R5_EVM + +&binman { + tiboot3-am65x_sr2-hs-evm.bin { + filename = "tiboot3-am65x_sr2-hs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl>; + core = "public"; + load = ; + keyfile = "custMpk.pem"; + }; + u_boot_spl: u-boot-spl { + no-expanded; + }; + }; + sysfw { + filename = "sysfw.bin"; + ti-secure-rom { + content = <&ti_sci_cert>; + core = "secure"; + load = <0x40000>; + keyfile = "custMpk.pem"; + countersign; + }; + ti_sci_cert: ti-sci-cert.bin { + filename = "ti-sysfw/ti-sci-firmware-am65x_sr2-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + ti-sci-firmware-am65x-hs-enc.bin { + filename = "ti-sysfw/ti-sci-firmware-am65x_sr2-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + itb { + filename = "sysfw-am65x_sr2-hs-evm.itb"; + fit { + description = "SYSFW and Config fragments"; + #address-cells = <1>; + images { + sysfw.bin { + description = "sysfw"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "sysfw.bin"; + }; + }; + board-cfg.bin { + description = "board-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&board_cfg>; + keyfile = "custMpk.pem"; + }; + board_cfg: board-cfg { + filename = "board-cfg.bin"; + type = "blob-ext"; + }; + }; + pm-cfg.bin { + description = "pm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&pm_cfg>; + keyfile = "custMpk.pem"; + }; + pm_cfg: pm-cfg { + filename = "pm-cfg.bin"; + type = "blob-ext"; + }; + }; + rm-cfg.bin { + description = "rm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&rm_cfg>; + keyfile = "custMpk.pem";\ + }; + rm_cfg: rm-cfg { + filename = "rm-cfg.bin"; + type = "blob-ext"; + }; + }; + sec-cfg.bin { + description = "sec-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&sec_cfg>; + keyfile = "custMpk.pem"; + }; + sec_cfg: sec-cfg { + filename = "sec-cfg.bin"; + type = "blob-ext"; + }; + }; + }; + }; + }; +}; + +&binman { + tiboot3-am65x_sr2-gp-evm.bin { + filename = "tiboot3-am65x_sr2-gp-evm.bin"; + symlink = "tiboot3.bin"; + ti-secure-rom { + content = <&u_boot_spl_unsigned>; + core = "public"; + load = ; + sw-rev = ; + keyfile = "ti-degenerate-key.pem"; + }; + u_boot_spl_unsigned: u-boot-spl { + no-expanded; + }; + }; + sysfw_gp { + filename = "sysfw.bin_gp"; + ti-secure-rom { + content = <&ti_sci>; + core = "secure"; + load = <0x40000>; + sw-rev = ; + keyfile = "ti-degenerate-key.pem"; + }; + ti_sci: ti-sci.bin { + filename = "ti-sysfw/ti-sci-firmware-am65x_sr2-gp.bin"; + type = "blob-ext"; + optional; + }; + }; + itb_gp { + filename = "sysfw-am65x_sr2-gp-evm.itb"; + symlink = "sysfw.itb"; + fit { + description = "SYSFW and Config fragments"; + #address-cells = <1>; + images { + sysfw.bin { + description = "sysfw"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "sysfw.bin_gp"; + }; + }; + board-cfg.bin { + description = "board-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "board-cfg.bin"; + }; + }; + pm-cfg.bin { + description = "pm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "pm-cfg.bin"; + }; + }; + rm-cfg.bin { + description = "rm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "rm-cfg.bin"; + }; + }; + sec-cfg.bin { + description = "sec-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "sec-cfg.bin"; + }; + }; + }; + }; + }; +}; +#endif + +#ifdef CONFIG_TARGET_AM654_A53_EVM + +#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" +#define SPL_AM654_EVM_DTB "spl/dts/k3-am654-base-board.dtb" + +#define UBOOT_NODTB "u-boot-nodtb.bin" +#define AM654_EVM_DTB "arch/arm/dts/k3-am654-base-board.dtb" + +&binman { + ti-spl { + filename = "tispl.bin"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = ; + entry = ; + ti-secure { + content = <&atf>; + keyfile = "custMpk.pem"; + }; + atf: atf-bl31 { + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + ti-secure { + content = <&tee>; + keyfile = "custMpk.pem"; + }; + tee: tee-os { + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + blob-ext { + filename = "/dev/null"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = ; + entry = ; + ti-secure { + content = <&u_boot_spl_nodtb>; + keyfile = "custMpk.pem"; + + }; + u_boot_spl_nodtb: blob-ext { + filename = SPL_NODTB; + }; + }; + + fdt-0 { + description = "k3-am654-base-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_am65x_evm_dtb>; + keyfile = "custMpk.pem"; + }; + spl_am65x_evm_dtb: blob-ext { + filename = SPL_AM654_EVM_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am654-base-board"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + filename = "u-boot.img"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for AM65 board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = ; + ti-secure { + content = <&u_boot_nodtb>; + keyfile = "custMpk.pem"; + }; + u_boot_nodtb: u-boot-nodtb { + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-am654-base-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&am65x_evm_dtb>; + keyfile = "custMpk.pem"; + + }; + am65x_evm_dtb: blob-ext { + filename = AM654_EVM_DTB; + }; + hash { + algo = "crc32"; + }; + }; + + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am654-base-board"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + ti-spl_unsigned { + filename = "tispl.bin_unsigned"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = ; + entry = ; + atf-bl31 { + filename = "bl31.bin"; + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + tee-os { + filename = "tee-raw.bin"; + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + blob-ext { + filename = "/dev/null"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = ; + entry = ; + blob-ext { + filename = SPL_NODTB; + }; + }; + + fdt-0 { + description = "k3-j721e-common-proc-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = SPL_AM654_EVM_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am654-base-board"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot_unsigned { + filename = "u-boot.img_unsigned"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for AM65 board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = ; + blob { + filename = UBOOT_NODTB; + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-am654-base-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = AM654_EVM_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am654-base-board"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; +#endif diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig index 220dd0234c..5fd19d652a 100644 --- a/board/ti/am65x/Kconfig +++ b/board/ti/am65x/Kconfig @@ -12,6 +12,7 @@ config TARGET_AM654_A53_EVM select ARM64 select SYS_DISABLE_DCACHE_OPS select BOARD_LATE_INIT + select BINMAN imply TI_I2C_BOARD_DETECT config TARGET_AM654_R5_EVM @@ -20,6 +21,7 @@ config TARGET_AM654_R5_EVM select SYS_THUMB_BUILD select K3_LOAD_SYSFW select K3_AM654_DDRSS + select BINMAN imply SYS_K3_SPL_ATF imply TI_I2C_BOARD_DETECT From patchwork Fri Jul 21 18:44:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811084 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=aZCHa4G6; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 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fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloR131068; Fri, 21 Jul 2023 13:45:52 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 10/23] am64x: yaml: Add board configs for AM64x Date: Sat, 22 Jul 2023 00:14:33 +0530 Message-ID: <20230721184446.5821-11-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Added YAML configs for AM64xx Signed-off-by: Neha Malcom Francis --- board/ti/am64x/board-cfg.yaml | 36 + board/ti/am64x/pm-cfg.yaml | 12 + board/ti/am64x/rm-cfg.yaml | 1400 +++++++++++++++++++++++++++++++++ board/ti/am64x/sec-cfg.yaml | 380 +++++++++ 4 files changed, 1828 insertions(+) create mode 100644 board/ti/am64x/board-cfg.yaml create mode 100644 board/ti/am64x/pm-cfg.yaml create mode 100644 board/ti/am64x/rm-cfg.yaml create mode 100644 board/ti/am64x/sec-cfg.yaml diff --git a/board/ti/am64x/board-cfg.yaml b/board/ti/am64x/board-cfg.yaml new file mode 100644 index 0000000000..62947c0820 --- /dev/null +++ b/board/ti/am64x/board-cfg.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for AM64x +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable : 0x5A + main_isolation_hostid : 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor : 0x1 + scaling_profile : 0x1 + disable_main_nav_secure_proxy : 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size : 0x0 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables : 0x00 + trace_src_enables : 0x00 diff --git a/board/ti/am64x/pm-cfg.yaml b/board/ti/am64x/pm-cfg.yaml new file mode 100644 index 0000000000..83c6a039f2 --- /dev/null +++ b/board/ti/am64x/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for AM64x +# + +--- + +pm-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 diff --git a/board/ti/am64x/rm-cfg.yaml b/board/ti/am64x/rm-cfg.yaml new file mode 100644 index 0000000000..1f4c6cf770 --- /dev/null +++ b/board/ti/am64x/rm-cfg.yaml @@ -0,0 +1,1400 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM64x +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size : 356 + host_cfg_entries: + - #1 + host_id: 12 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #2 + host_id: 30 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #3 + host_id: 36 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #4 + host_id: 38 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #5 + host_id: 41 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #6 + host_id: 43 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 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num_resource: 1 + type: 1961 + host_id: 30 + reserved: 0 + + - + start_resource: 0 + num_resource: 4 + type: 1962 + host_id: 12 + reserved: 0 + + - + start_resource: 4 + num_resource: 3 + type: 1962 + host_id: 35 + reserved: 0 + + - + start_resource: 4 + num_resource: 3 + type: 1962 + host_id: 36 + reserved: 0 + + - + start_resource: 7 + num_resource: 2 + type: 1962 + host_id: 38 + reserved: 0 + + - + start_resource: 9 + num_resource: 4 + type: 1962 + host_id: 41 + reserved: 0 + + - + start_resource: 13 + num_resource: 2 + type: 1962 + host_id: 43 + reserved: 0 + + - + start_resource: 15 + num_resource: 1 + type: 1962 + host_id: 30 + reserved: 0 + + - + start_resource: 16 + num_resource: 1 + type: 1963 + host_id: 12 + reserved: 0 + + - + start_resource: 16 + num_resource: 1 + type: 1963 + host_id: 35 + reserved: 0 + + - + start_resource: 16 + num_resource: 16 + type: 1964 + host_id: 12 + reserved: 0 + + - + start_resource: 16 + num_resource: 16 + type: 1964 + host_id: 35 + reserved: 0 + + - + start_resource: 32 + num_resource: 8 + type: 1966 + host_id: 128 + reserved: 0 + + - + start_resource: 32 + num_resource: 8 + type: 1968 + host_id: 128 + reserved: 0 + + - + start_resource: 19 + num_resource: 1 + type: 1969 + host_id: 12 + reserved: 0 + + - + start_resource: 40 + num_resource: 8 + type: 1970 + host_id: 12 + reserved: 0 + + - + start_resource: 20 + num_resource: 1 + type: 1971 + host_id: 12 + reserved: 0 + + - + start_resource: 40 + num_resource: 8 + type: 1972 + host_id: 12 + reserved: 0 + + - + start_resource: 21 + num_resource: 4 + type: 1973 + host_id: 12 + reserved: 0 + + - + start_resource: 48 + num_resource: 64 + type: 1974 + host_id: 12 + reserved: 0 + + - + start_resource: 25 + num_resource: 4 + type: 1975 + host_id: 12 + reserved: 0 + + - + start_resource: 112 + num_resource: 64 + type: 1976 + host_id: 12 + reserved: 0 + + - + start_resource: 0 + num_resource: 1 + type: 2112 + host_id: 128 + reserved: 0 + + - + start_resource: 2 + num_resource: 2 + type: 2122 + host_id: 12 + reserved: 0 + + - + start_resource: 20 + num_resource: 2 + type: 2124 + host_id: 35 + reserved: 0 + + - + start_resource: 20 + num_resource: 2 + type: 2124 + host_id: 36 + reserved: 0 + + - + start_resource: 22 + num_resource: 2 + type: 2124 + host_id: 38 + reserved: 0 + + - + start_resource: 24 + num_resource: 2 + type: 2124 + host_id: 41 + reserved: 0 + + - + start_resource: 26 + num_resource: 2 + type: 2124 + host_id: 43 + reserved: 0 + + - + start_resource: 28 + num_resource: 4 + type: 2124 + host_id: 128 + reserved: 0 diff --git a/board/ti/am64x/sec-cfg.yaml b/board/ti/am64x/sec-cfg.yaml new file mode 100644 index 0000000000..7c51fd3406 --- /dev/null +++ b/board/ti/am64x/sec-cfg.yaml @@ -0,0 +1,380 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security configuration for AM64x +# + +--- + +sec-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - #1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - #1 + host_id: 0 + supervisor_host_id: 0 + - #2 + host_id: 0 + supervisor_host_id: 0 + - #3 + host_id: 0 + supervisor_host_id: 0 + - #4 + host_id: 0 + supervisor_host_id: 0 + - #5 + host_id: 0 + supervisor_host_id: 0 + - #6 + host_id: 0 + supervisor_host_id: 0 + - #7 + host_id: 0 + supervisor_host_id: 0 + - #8 + host_id: 0 + supervisor_host_id: 0 + - #9 + host_id: 0 + supervisor_host_id: 0 + - #10 + host_id: 0 + supervisor_host_id: 0 + - #11 + host_id: 0 + supervisor_host_id: 0 + - #12 + host_id: 0 + supervisor_host_id: 0 + - #13 + host_id: 0 + supervisor_host_id: 0 + - #14 + host_id: 0 + supervisor_host_id: 0 + - #15 + host_id: 0 + supervisor_host_id: 0 + - #16 + host_id: 0 + supervisor_host_id: 0 + - #17 + host_id: 0 + supervisor_host_id: 0 + - #18 + host_id: 0 + supervisor_host_id: 0 + - #19 + host_id: 0 + supervisor_host_id: 0 + - #20 + host_id: 0 + supervisor_host_id: 0 + - #21 + host_id: 0 + supervisor_host_id: 0 + - #22 + host_id: 0 + supervisor_host_id: 0 + - #23 + host_id: 0 + supervisor_host_id: 0 + - #24 + host_id: 0 + supervisor_host_id: 0 + - #25 + host_id: 0 + supervisor_host_id: 0 + - #26 + host_id: 0 + supervisor_host_id: 0 + - #27 + host_id: 0 + supervisor_host_id: 0 + - #28 + host_id: 0 + supervisor_host_id: 0 + - #29 + host_id: 0 + supervisor_host_id: 0 + - #30 + host_id: 0 + supervisor_host_id: 0 + - #31 + host_id: 0 + supervisor_host_id: 0 + - #32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + write_host_id : 0 + otp_entry: + - #1 + host_id: 0 + host_perms: 0 + - #2 + host_id: 0 + host_perms: 0 + - #3 + host_id: 0 + host_perms: 0 + - #4 + host_id: 0 + host_perms: 0 + - #5 + host_id: 0 + host_perms: 0 + - #6 + host_id: 0 + host_perms: 0 + - #7 + host_id: 0 + host_perms: 0 + - #8 + host_id: 0 + host_perms: 0 + - #9 + host_id: 0 + host_perms: 0 + - #10 + host_id: 0 + host_perms: 0 + - #11 + host_id: 0 + host_perms: 0 + - #12 + host_id: 0 + host_perms: 0 + - #13 + host_id: 0 + host_perms: 0 + - #14 + host_id: 0 + host_perms: 0 + - #15 + host_id: 0 + host_perms: 0 + - #16 + host_id: 0 + host_perms: 0 + - #17 + host_id: 0 + host_perms: 0 + - #18 + host_id: 0 + host_perms: 0 + - #19 + host_id: 0 + host_perms: 0 + - #20 + host_id: 0 + host_perms: 0 + - #21 + host_id: 0 + host_perms: 0 + - #22 + host_id: 0 + host_perms: 0 + - #23 + host_id: 0 + host_perms: 0 + - #24 + host_id: 0 + host_perms: 0 + - #25 + host_id: 0 + host_perms: 0 + - #26 + host_id: 0 + host_perms: 0 + - #27 + host_id: 0 + host_perms: 0 + - #28 + host_id: 0 + host_perms: 0 + - #29 + host_id: 0 + host_perms: 0 + - #30 + host_id: 0 + host_perms: 0 + - #31 + host_id: 0 + host_perms: 0 + - #32 + host_id: 0 + host_perms: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci : 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size : 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0 + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock : 0x5A + allow_wildcard_unlock : 0x5A + allowed_debug_level_rsvd : 0 + rsvd : 0 + min_cert_rev : 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender : 0 + handover_to_host_id : 0 + rsvd: [0, 0, 0, 0] From patchwork Fri Jul 21 18:44:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811085 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=P4/N4Zpg; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de 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(ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloS131068; Fri, 21 Jul 2023 13:45:59 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 11/23] am64x: dts: binman: Package tiboot3.bin, tispl.bin u-boot.img Date: Sat, 22 Jul 2023 00:14:34 +0530 Message-ID: <20230721184446.5821-12-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Support added for HS and GP boot binaries for AM64x. HS-SE: * tiboot3-am64x_sr2-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-am64x_sr2-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am64x-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned Note that the bootflow followed by AM64x requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * sysfw * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * ATF * OP-TEE * A53 SPL * A53 SPL dtbs u-boot.img: * A53 U-Boot * A53 U-Boot dtbs Reviewed-by: Simon Glass [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-am642-evm-u-boot.dtsi | 2 + arch/arm/dts/k3-am642-r5-evm.dts | 1 + arch/arm/dts/k3-am642-sk-u-boot.dtsi | 2 + arch/arm/dts/k3-am64x-binman.dtsi | 515 ++++++++++++++++++++++++++ board/ti/am64x/Kconfig | 2 + 5 files changed, 522 insertions(+) create mode 100644 arch/arm/dts/k3-am64x-binman.dtsi diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi index 64857b0909..73577e8cfd 100644 --- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include "k3-am64x-binman.dtsi" + / { chosen { stdout-path = "serial2:115200n8"; diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts index e870492a69..b49064181a 100644 --- a/arch/arm/dts/k3-am642-r5-evm.dts +++ b/arch/arm/dts/k3-am642-r5-evm.dts @@ -8,6 +8,7 @@ #include "k3-am642.dtsi" #include "k3-am64-evm-ddr4-1600MTs.dtsi" #include "k3-am64-ddr.dtsi" +#include "k3-am64x-binman.dtsi" / { chosen { diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi index 69dbe943bd..3d6be025bd 100644 --- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include "k3-am64x-binman.dtsi" + / { chosen { stdout-path = "serial2:115200n8"; diff --git a/arch/arm/dts/k3-am64x-binman.dtsi b/arch/arm/dts/k3-am64x-binman.dtsi new file mode 100644 index 0000000000..26e17bddf3 --- /dev/null +++ b/arch/arm/dts/k3-am64x-binman.dtsi @@ -0,0 +1,515 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + +#include "k3-binman.dtsi" + +#ifdef CONFIG_TARGET_AM642_R5_EVM + +&binman { + tiboot3-am64x_sr2-hs-evm.bin { + filename = "tiboot3-am64x_sr2-hs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl>, <&ti_sci_enc>, + <&combined_sysfw_cfg>, <&sysfw_inner_cert>; + combined; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl>; + content-sysfw = <&ti_sci_enc>; + content-sysfw-data = <&combined_sysfw_cfg>; + content-sysfw-inner-cert = <&sysfw_inner_cert>; + load = <0x70000000>; + load-sysfw = <0x44000>; + load-sysfw-data = <0x7b000>; + }; + u_boot_spl: u-boot-spl { + no-expanded; + }; + ti_sci_enc: ti-fs-enc.bin { + filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_sysfw_cfg: combined-sysfw-cfg.bin { + filename = "combined-sysfw-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert: sysfw-inner-cert { + filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + + }; +}; + +&binman { + tiboot3-am64x_sr2-hs-fs-evm.bin { + filename = "tiboot3-am64x_sr2-hs-fs-evm.bin"; + symlink = "tiboot3.bin"; + ti-secure-rom { + content = <&u_boot_spl_fs>, <&ti_sci_enc_fs>, + <&combined_sysfw_cfg_fs>, <&sysfw_inner_cert_fs>; + combined; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs>; + content-sysfw = <&ti_sci_enc_fs>; + content-sysfw-data = <&combined_sysfw_cfg_fs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; + load = <0x70000000>; + load-sysfw = <0x44000>; + load-sysfw-data = <0x7b000>; + }; + u_boot_spl_fs: u-boot-spl { + no-expanded; + }; + ti_sci_enc_fs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_sysfw_cfg_fs: combined-sysfw-cfg.bin { + filename = "combined-sysfw-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert_fs: sysfw-inner-cert { + filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + + }; +}; + +&binman { + tiboot3-am64x-gp-evm.bin { + filename = "tiboot3-am64x-gp-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_unsigned>, <&ti_sci_gp>, <&combined_sysfw_cfg_gp>; + combined; + content-sbl = <&u_boot_spl_unsigned>; + load = <0x70000000>; + content-sysfw = <&ti_sci_gp>; + load-sysfw = <0x44000>; + content-sysfw-data = <&combined_sysfw_cfg_gp>; + load-sysfw-data = <0x7b000>; + sw-rev = <1>; + keyfile = "ti-degenerate-key.pem"; + }; + u_boot_spl_unsigned: u-boot-spl { + no-expanded; + }; + ti_sci_gp: ti-sci-gp.bin { + filename = "ti-sysfw/ti-sci-firmware-am64x-gp.bin"; + type = "blob-ext"; + optional; + }; + combined_sysfw_cfg_gp: combined-sysfw-cfg-gp.bin { + filename = "combined-sysfw-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +#endif + +#ifdef CONFIG_TARGET_AM642_A53_EVM + +#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" +#define SPL_AM642_EVM_DTB "spl/dts/k3-am642-evm.dtb" +#define SPL_AM642_SK_DTB "spl/dts/k3-am642-sk.dtb" + +#define UBOOT_NODTB "u-boot-nodtb.bin" +#define AM642_EVM_DTB "arch/arm/dts/k3-am642-evm.dtb" +#define AM642_SK_DTB "arch/arm/dts/k3-am642-sk.dtb" + +&binman { + ti-spl { + filename = "tispl.bin"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = ; + entry = ; + ti-secure { + content = <&atf>; + keyfile = "custMpk.pem"; + }; + atf: atf-bl31 { + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + ti-secure { + content = <&tee>; + keyfile = "custMpk.pem"; + }; + tee: tee-os { + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + blob-ext { + filename = "/dev/null"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = ; + entry = ; + ti-secure { + content = <&u_boot_spl_nodtb>; + keyfile = "custMpk.pem"; + + }; + u_boot_spl_nodtb: blob-ext { + filename = SPL_NODTB; + }; + }; + + fdt-0 { + description = "k3-am642-evm"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_am64x_evm_dtb>; + keyfile = "custMpk.pem"; + }; + spl_am64x_evm_dtb: blob-ext { + filename = SPL_AM642_EVM_DTB; + }; + + }; + + fdt-1 { + description = "k3-am642-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_am64x_sk_dtb>; + keyfile = "custMpk.pem"; + }; + spl_am64x_sk_dtb: blob-ext { + filename = SPL_AM642_SK_DTB; + }; + + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am642-evm"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + + conf-1 { + description = "k3-am642-sk"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-1"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + filename = "u-boot.img"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for AM64 board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = ; + ti-secure { + content = <&u_boot_nodtb>; + keyfile = "custMpk.pem"; + }; + u_boot_nodtb: u-boot-nodtb { + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-am642-evm"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&am64x_evm_dtb>; + keyfile = "custMpk.pem"; + + }; + am64x_evm_dtb: blob-ext { + filename = AM642_EVM_DTB; + }; + hash { + algo = "crc32"; + }; + }; + + fdt-1 { + description = "k3-am642-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&am64x_sk_dtb>; + keyfile = "custMpk.pem"; + + }; + am64x_sk_dtb: blob-ext { + filename = AM642_SK_DTB; + }; + hash { + algo = "crc32"; + }; + }; + + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am642-evm"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + + conf-1 { + description = "k3-am642-sk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-1"; + }; + }; + }; + }; +}; + +&binman { + ti-spl_unsigned { + filename = "tispl.bin_unsigned"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = ; + entry = ; + atf-bl31 { + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + tee-os { + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + blob-ext { + filename = "/dev/null"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = ; + entry = ; + blob { + filename = "spl/u-boot-spl-nodtb.bin"; + }; + }; + + fdt-0 { + description = "k3-am642-evm"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = SPL_AM642_EVM_DTB; + }; + }; + + fdt-1 { + description = "k3-am642-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = SPL_AM642_SK_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am642-evm"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + + conf-1 { + description = "k3-am642-sk"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-1"; + }; + }; + }; + }; +}; + +&binman { + u-boot_unsigned { + filename = "u-boot.img_unsigned"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for AM64 board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = ; + blob { + filename = UBOOT_NODTB; + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-am642-evm"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = AM642_EVM_DTB; + }; + hash { + algo = "crc32"; + }; + }; + + fdt-1 { + description = "k3-am642-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = AM642_SK_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am642-evm"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + + conf-1 { + description = "k3-am642-sk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-1"; + }; + }; + }; + }; +}; +#endif diff --git a/board/ti/am64x/Kconfig b/board/ti/am64x/Kconfig index afb54f8cda..fb596e4adf 100644 --- a/board/ti/am64x/Kconfig +++ b/board/ti/am64x/Kconfig @@ -9,6 +9,7 @@ choice config TARGET_AM642_A53_EVM bool "TI K3 based AM642 EVM running on A53" select ARM64 + select BINMAN imply BOARD imply SPL_BOARD imply TI_I2C_BOARD_DETECT @@ -21,6 +22,7 @@ config TARGET_AM642_R5_EVM select RAM select SPL_RAM select K3_DDRSS + select BINMAN imply SYS_K3_SPL_ATF imply TI_I2C_BOARD_DETECT From patchwork Fri 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[10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 36LIkCoJ093557 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 21 Jul 2023 13:46:12 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 21 Jul 2023 13:46:11 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jul 2023 13:46:11 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloT131068; Fri, 21 Jul 2023 13:46:05 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 12/23] j721s2: yaml: Add board configs for J721S2 Date: Sat, 22 Jul 2023 00:14:35 +0530 Message-ID: <20230721184446.5821-13-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Added YAML configs for J721S2 Signed-off-by: Neha Malcom Francis --- board/ti/j721s2/board-cfg.yaml | 36 + board/ti/j721s2/pm-cfg.yaml | 12 + board/ti/j721s2/rm-cfg.yaml | 2901 ++++++++++++++++++++++++++++++++ board/ti/j721s2/sec-cfg.yaml | 379 +++++ 4 files changed, 3328 insertions(+) create mode 100644 board/ti/j721s2/board-cfg.yaml create mode 100644 board/ti/j721s2/pm-cfg.yaml create mode 100644 board/ti/j721s2/rm-cfg.yaml create mode 100644 board/ti/j721s2/sec-cfg.yaml diff --git a/board/ti/j721s2/board-cfg.yaml b/board/ti/j721s2/board-cfg.yaml new file mode 100644 index 0000000000..dd024110e7 --- /dev/null +++ b/board/ti/j721s2/board-cfg.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for J721S2 +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable : 0x5A + main_isolation_hostid : 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor : 0x1 + scaling_profile : 0x1 + disable_main_nav_secure_proxy : 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size : 0x0 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables : 0x00 + trace_src_enables : 0x00 diff --git a/board/ti/j721s2/pm-cfg.yaml b/board/ti/j721s2/pm-cfg.yaml new file mode 100644 index 0000000000..a640460d30 --- /dev/null +++ b/board/ti/j721s2/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for J721S2 +# + +--- + +pm-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 diff --git a/board/ti/j721s2/rm-cfg.yaml b/board/ti/j721s2/rm-cfg.yaml new file mode 100644 index 0000000000..f772832f19 --- /dev/null +++ b/board/ti/j721s2/rm-cfg.yaml @@ -0,0 +1,2901 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for J721S2 +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size : 356 + host_cfg_entries: + - #1 + host_id: 3 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #2 + host_id: 5 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #3 + host_id: 12 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #4 + host_id: 13 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #5 + host_id: 21 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #6 + host_id: 23 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #7 + host_id: 35 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #8 + host_id: 37 + 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Texas Instruments Incorporated - https://www.ti.com/ +# +# Security management configuration for J721S2 +# + +--- + +sec-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - #1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - #1 + host_id: 0 + supervisor_host_id: 0 + - #2 + host_id: 0 + supervisor_host_id: 0 + - #3 + host_id: 0 + supervisor_host_id: 0 + - #4 + host_id: 0 + supervisor_host_id: 0 + - #5 + host_id: 0 + supervisor_host_id: 0 + - #6 + host_id: 0 + supervisor_host_id: 0 + - #7 + host_id: 0 + supervisor_host_id: 0 + - #8 + host_id: 0 + supervisor_host_id: 0 + - #9 + host_id: 0 + supervisor_host_id: 0 + - #10 + host_id: 0 + supervisor_host_id: 0 + - #11 + host_id: 0 + supervisor_host_id: 0 + - #12 + host_id: 0 + supervisor_host_id: 0 + - #13 + host_id: 0 + supervisor_host_id: 0 + - #14 + host_id: 0 + supervisor_host_id: 0 + - #15 + host_id: 0 + supervisor_host_id: 0 + - #16 + host_id: 0 + supervisor_host_id: 0 + - #17 + host_id: 0 + supervisor_host_id: 0 + - #18 + host_id: 0 + supervisor_host_id: 0 + - #19 + host_id: 0 + supervisor_host_id: 0 + - #20 + host_id: 0 + supervisor_host_id: 0 + - #21 + host_id: 0 + supervisor_host_id: 0 + - #22 + host_id: 0 + supervisor_host_id: 0 + - #23 + host_id: 0 + supervisor_host_id: 0 + - #24 + host_id: 0 + supervisor_host_id: 0 + - #25 + host_id: 0 + supervisor_host_id: 0 + - #26 + host_id: 0 + supervisor_host_id: 0 + - #27 + host_id: 0 + supervisor_host_id: 0 + - #28 + host_id: 0 + supervisor_host_id: 0 + - #29 + host_id: 0 + supervisor_host_id: 0 + - #30 + host_id: 0 + supervisor_host_id: 0 + - #31 + host_id: 0 + supervisor_host_id: 0 + - #32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + write_host_id : 0 + otp_entry: + - #1 + host_id: 0 + host_perms: 0 + - #2 + host_id: 0 + host_perms: 0 + - #3 + host_id: 0 + host_perms: 0 + - #4 + host_id: 0 + host_perms: 0 + - #5 + host_id: 0 + host_perms: 0 + - #6 + host_id: 0 + host_perms: 0 + - #7 + host_id: 0 + host_perms: 0 + - #8 + host_id: 0 + host_perms: 0 + - #9 + host_id: 0 + host_perms: 0 + - #10 + host_id: 0 + host_perms: 0 + - #11 + host_id: 0 + host_perms: 0 + - #12 + host_id: 0 + host_perms: 0 + - #13 + host_id: 0 + host_perms: 0 + - #14 + host_id: 0 + host_perms: 0 + - #15 + host_id: 0 + host_perms: 0 + - #16 + host_id: 0 + host_perms: 0 + - #17 + host_id: 0 + host_perms: 0 + - #18 + host_id: 0 + host_perms: 0 + - #19 + host_id: 0 + host_perms: 0 + - #20 + host_id: 0 + host_perms: 0 + - #21 + host_id: 0 + host_perms: 0 + - #22 + host_id: 0 + host_perms: 0 + - #23 + host_id: 0 + host_perms: 0 + - #24 + host_id: 0 + host_perms: 0 + - #25 + host_id: 0 + host_perms: 0 + - #26 + host_id: 0 + host_perms: 0 + - #27 + host_id: 0 + host_perms: 0 + - #28 + host_id: 0 + host_perms: 0 + - #29 + host_id: 0 + host_perms: 0 + - #30 + host_id: 0 + host_perms: 0 + - #31 + host_id: 0 + host_perms: 0 + - #32 + host_id: 0 + host_perms: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci : 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size : 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0 + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock : 0x0 + allow_wildcard_unlock : 0x0 + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev : 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender : 0 + handover_to_host_id : 0 + rsvd: [0, 0, 0, 0] From patchwork Fri Jul 21 18:44:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811087 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: 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Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jul 2023 13:46:18 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloU131068; Fri, 21 Jul 2023 13:46:12 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 13/23] j721s2: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img Date: Sat, 22 Jul 2023 00:14:36 +0530 Message-ID: <20230721184446.5821-14-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Support has been added for both HS-SE, HS-FS and GP images. HS-SE: * tiboot3-j721s2-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-j721s2-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-j721s2-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by J721S2 requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis Signed-off-by: Neha Malcom Francis --- .../arm/dts/k3-am68-sk-base-board-u-boot.dtsi | 2 + arch/arm/dts/k3-j721s2-binman.dtsi | 546 ++++++++++++++++++ .../k3-j721s2-common-proc-board-u-boot.dtsi | 2 + .../dts/k3-j721s2-r5-common-proc-board.dts | 1 + board/ti/j721s2/Kconfig | 2 + 5 files changed, 553 insertions(+) create mode 100644 arch/arm/dts/k3-j721s2-binman.dtsi diff --git a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi index ee31b1ebe7..79faa1b573 100644 --- a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ +#include "k3-j721s2-binman.dtsi" + / { chosen { stdout-path = "serial2:115200n8"; diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi new file mode 100644 index 0000000000..1671217ec0 --- /dev/null +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -0,0 +1,546 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-binman.dtsi" + +#ifdef CONFIG_TARGET_J721S2_R5_EVM + +&binman { + tiboot3-j721s2-hs-evm.bin { + filename = "tiboot3-j721s2-hs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>, + <&combined_dm_cfg>, <&sysfw_inner_cert>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl>; + content-sysfw = <&ti_fs_enc>; + content-sysfw-data = <&combined_tifs_cfg>; + content-sysfw-inner-cert = <&sysfw_inner_cert>; + content-dm-data = <&combined_dm_cfg>; + load = <0x41c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x41c80000>; + }; + u_boot_spl: u-boot-spl { + no-expanded; + }; + ti_fs_enc: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { + tiboot3-j721s2-hs-fs-evm.bin { + filename = "tiboot3-j721s2-hs-fs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>, + <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs>; + content-sysfw = <&ti_fs_enc_fs>; + content-sysfw-data = <&combined_tifs_cfg_fs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; + content-dm-data = <&combined_dm_cfg_fs>; + load = <0x41c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x41c80000>; + }; + u_boot_spl_fs: u-boot-spl { + no-expanded; + }; + ti_fs_enc_fs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_fs: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert_fs: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg_fs: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { + tiboot3-j721s2-gp-evm.bin { + filename = "tiboot3-j721s2-gp-evm.bin"; + symlink = "tiboot3.bin"; + ti-secure-rom { + content = <&u_boot_spl_unsigned>, <&ti_fs_gp>, + <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; + combined; + dm-data; + content-sbl = <&u_boot_spl_unsigned>; + load = <0x41c00000>; + content-sysfw = <&ti_fs_gp>; + load-sysfw = <0x40000>; + content-sysfw-data = <&combined_tifs_cfg_gp>; + load-sysfw-data = <0x67000>; + content-dm-data = <&combined_dm_cfg_gp>; + load-dm-data = <0x41c80000>; + sw-rev = <1>; + keyfile = "ti-degenerate-key.pem"; + }; + u_boot_spl_unsigned: u-boot-spl { + no-expanded; + }; + ti_fs_gp: ti-fs-gp.bin { + filename = "ti-sysfw/ti-fs-firmware-j721s2-gp.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + combined_dm_cfg_gp: combined-dm-cfg-gp.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + + }; +}; + +#endif + +#ifdef CONFIG_TARGET_J721S2_A72_EVM + +#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" +#define SPL_J721S2_EVM_DTB "spl/dts/k3-j721s2-common-proc-board.dtb" +#define SPL_AM68_SK_DTB "spl/dts/k3-am68-sk-base-board.dtb" + +#define UBOOT_NODTB "u-boot-nodtb.bin" +#define J721S2_EVM_DTB "arch/arm/dts/k3-j721s2-common-proc-board.dtb" +#define AM68_SK_DTB "arch/arm/dts/k3-am68-sk-base-board.dtb" + +&binman { + ti-dm { + filename = "ti-dm.bin"; + blob-ext { + filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + ti-spl { + filename = "tispl.bin"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = ; + entry = ; + ti-secure { + content = <&atf>; + keyfile = "custMpk.pem"; + }; + atf: atf-bl31 { + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + ti-secure { + content = <&tee>; + keyfile = "custMpk.pem"; + }; + tee: tee-os { + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + ti-secure { + content = <&dm>; + keyfile = "custMpk.pem"; + }; + dm: blob-ext { + filename = "ti-dm.bin"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = ; + entry = ; + ti-secure { + content = <&u_boot_spl_nodtb>; + keyfile = "custMpk.pem"; + }; + u_boot_spl_nodtb: blob-ext { + filename = SPL_NODTB; + }; + }; + + fdt-0 { + description = "k3-j721s2-common-proc-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_j721s2_evm_dtb>; + keyfile = "custMpk.pem"; + }; + spl_j721s2_evm_dtb: blob-ext { + filename = SPL_J721S2_EVM_DTB; + }; + + }; + + fdt-1 { + description = "k3-am68-sk-base-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_am68_sk_dtb>; + keyfile = "custMpk.pem"; + }; + spl_am68_sk_dtb: blob-ext { + filename = SPL_AM68_SK_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j721s2-common-proc-board"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + + conf-1 { + description = "k3-am68-sk-base-board"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-1"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + filename = "u-boot.img"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for J721S2 board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = ; + ti-secure { + content = <&u_boot_nodtb>; + keyfile = "custMpk.pem"; + }; + u_boot_nodtb: u-boot-nodtb { + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-j721s2-common-proc-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&j721s2_evm_dtb>; + keyfile = "custMpk.pem"; + }; + j721s2_evm_dtb: blob-ext { + filename = J721S2_EVM_DTB; + }; + + hash { + algo = "crc32"; + }; + }; + + fdt-1 { + description = "k3-am68-sk-base-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&am68_sk_dtb>; + keyfile = "custMpk.pem"; + }; + am68_sk_dtb: blob-ext { + filename = AM68_SK_DTB; + }; + + hash { + algo = "crc32"; + }; + }; + + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j721s2-common-proc-board"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + conf-1 { + description = "k3-am68-sk-base-board"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-1"; + }; + + }; + }; + }; +}; + +&binman { + ti-spl_unsigned { + filename = "tispl.bin_unsigned"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = ; + entry = ; + atf-bl31 { + filename = "bl31.bin"; + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + tee-os { + filename = "tee-raw.bin"; + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + blob-ext { + filename = "ti-dm.bin"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = ; + entry = ; + blob { + filename = "spl/u-boot-spl-nodtb.bin"; + }; + }; + + fdt-0 { + description = "k3-j721s2-common-proc-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = SPL_J721S2_EVM_DTB; + }; + }; + fdt-1 { + description = "k3-am68-sk-base-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = SPL_AM68_SK_DTB; + }; + }; + + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j721s2-common-proc-board"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + conf-1 { + description = "k3-am68-sk-base-board"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-1"; + }; + }; + }; + }; +}; + +&binman { + u-boot_unsigned { + filename = "u-boot.img_unsigned"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for J721S2 board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = ; + blob { + filename = UBOOT_NODTB; + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-j721s2-common-proc-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = J721S2_EVM_DTB; + }; + hash { + algo = "crc32"; + }; + }; + fdt-1 { + description = "k3-am68-sk-base-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = AM68_SK_DTB; + }; + hash { + algo = "crc32"; + }; + }; + + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j721s2-common-proc-board"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + conf-1 { + description = "k3-am68-sk-base-board"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-1"; + }; + }; + }; + }; +}; +#endif diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi index 4fd6d36417..f940ffee87 100644 --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include "k3-j721s2-binman.dtsi" + / { chosen { stdout-path = "serial2:115200n8"; diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts index e02b334d10..c74e8e58ae 100644 --- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts @@ -8,6 +8,7 @@ #include "k3-j721s2-som-p0.dtsi" #include "k3-j721s2-ddr-evm-lp4-4266.dtsi" #include "k3-j721s2-ddr.dtsi" +#include "k3-j721s2-binman.dtsi" / { chosen { diff --git a/board/ti/j721s2/Kconfig b/board/ti/j721s2/Kconfig index a24641f8cf..f6d1cb5765 100644 --- a/board/ti/j721s2/Kconfig +++ b/board/ti/j721s2/Kconfig @@ -13,6 +13,7 @@ config TARGET_J721S2_A72_EVM select BOARD_LATE_INIT imply TI_I2C_BOARD_DETECT select SYS_DISABLE_DCACHE_OPS + select BINMAN config TARGET_J721S2_R5_EVM bool "TI K3 based J721S2 EVM running on R5" @@ -22,6 +23,7 @@ config TARGET_J721S2_R5_EVM select RAM select SPL_RAM select K3_DDRSS + select BINMAN imply SYS_K3_SPL_ATF imply TI_I2C_BOARD_DETECT From patchwork Fri Jul 21 18:44:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811088 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) 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cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jul 2023 13:46:24 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloV131068; Fri, 21 Jul 2023 13:46:18 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 14/23] am62: yaml: Add board configs for AM62 Date: Sat, 22 Jul 2023 00:14:37 +0530 Message-ID: <20230721184446.5821-15-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Added YAML configs for AM62 Signed-off-by: Neha Malcom Francis --- board/ti/am62x/board-cfg.yaml | 36 ++ board/ti/am62x/pm-cfg.yaml | 12 + board/ti/am62x/rm-cfg.yaml | 1088 +++++++++++++++++++++++++++++++++ board/ti/am62x/sec-cfg.yaml | 379 ++++++++++++ 4 files changed, 1515 insertions(+) create mode 100644 board/ti/am62x/board-cfg.yaml create mode 100644 board/ti/am62x/pm-cfg.yaml create mode 100644 board/ti/am62x/rm-cfg.yaml create mode 100644 board/ti/am62x/sec-cfg.yaml diff --git a/board/ti/am62x/board-cfg.yaml b/board/ti/am62x/board-cfg.yaml new file mode 100644 index 0000000000..36cfb550ad --- /dev/null +++ b/board/ti/am62x/board-cfg.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for AM62 +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable : 0x5A + main_isolation_hostid : 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor : 0x1 + scaling_profile : 0x1 + disable_main_nav_secure_proxy : 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size : 0x0 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables : 0x00 + trace_src_enables : 0x00 diff --git a/board/ti/am62x/pm-cfg.yaml b/board/ti/am62x/pm-cfg.yaml new file mode 100644 index 0000000000..5d04cf82ef --- /dev/null +++ b/board/ti/am62x/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for AM62 +# + +--- + +pm-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 diff --git a/board/ti/am62x/rm-cfg.yaml b/board/ti/am62x/rm-cfg.yaml new file mode 100644 index 0000000000..c28707be8e --- /dev/null +++ b/board/ti/am62x/rm-cfg.yaml @@ -0,0 +1,1088 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62 +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size : 356 + host_cfg_entries: + - #1 + host_id: 12 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #2 + host_id: 30 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #3 + host_id: 36 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #4 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #5 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #6 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #7 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #8 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #9 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #10 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #11 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #12 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #13 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #14 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #15 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #16 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #17 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #18 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #19 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #20 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #21 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #22 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #23 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #24 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #25 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #26 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #27 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 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43 + num_resource: 8 + type: 1972 + host_id: 12 + reserved: 0 + + - + start_resource: 0 + num_resource: 1 + type: 2112 + host_id: 128 + reserved: 0 + + - + start_resource: 2 + num_resource: 2 + type: 2122 + host_id: 12 + reserved: 0 diff --git a/board/ti/am62x/sec-cfg.yaml b/board/ti/am62x/sec-cfg.yaml new file mode 100644 index 0000000000..07081ce06c --- /dev/null +++ b/board/ti/am62x/sec-cfg.yaml @@ -0,0 +1,379 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security management configuration for AM62 +# + +--- + +sec-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - #1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - #1 + host_id: 0 + supervisor_host_id: 0 + - #2 + host_id: 0 + supervisor_host_id: 0 + - #3 + host_id: 0 + supervisor_host_id: 0 + - #4 + host_id: 0 + supervisor_host_id: 0 + - #5 + host_id: 0 + supervisor_host_id: 0 + - #6 + host_id: 0 + supervisor_host_id: 0 + - #7 + host_id: 0 + supervisor_host_id: 0 + - #8 + host_id: 0 + supervisor_host_id: 0 + - #9 + host_id: 0 + supervisor_host_id: 0 + - #10 + host_id: 0 + supervisor_host_id: 0 + - #11 + host_id: 0 + supervisor_host_id: 0 + - #12 + host_id: 0 + supervisor_host_id: 0 + - #13 + host_id: 0 + supervisor_host_id: 0 + - #14 + host_id: 0 + supervisor_host_id: 0 + - #15 + host_id: 0 + supervisor_host_id: 0 + - #16 + host_id: 0 + supervisor_host_id: 0 + - #17 + host_id: 0 + supervisor_host_id: 0 + - #18 + host_id: 0 + supervisor_host_id: 0 + - #19 + host_id: 0 + supervisor_host_id: 0 + - #20 + host_id: 0 + supervisor_host_id: 0 + - #21 + host_id: 0 + supervisor_host_id: 0 + - #22 + host_id: 0 + supervisor_host_id: 0 + - #23 + host_id: 0 + supervisor_host_id: 0 + - #24 + host_id: 0 + supervisor_host_id: 0 + - #25 + host_id: 0 + supervisor_host_id: 0 + - #26 + host_id: 0 + supervisor_host_id: 0 + - #27 + host_id: 0 + supervisor_host_id: 0 + - #28 + host_id: 0 + supervisor_host_id: 0 + - #29 + host_id: 0 + supervisor_host_id: 0 + - #30 + host_id: 0 + supervisor_host_id: 0 + - #31 + host_id: 0 + supervisor_host_id: 0 + - #32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + write_host_id : 0 + otp_entry: + - #1 + host_id: 0 + host_perms: 0 + - #2 + host_id: 0 + host_perms: 0 + - #3 + host_id: 0 + host_perms: 0 + - #4 + host_id: 0 + host_perms: 0 + - #5 + host_id: 0 + host_perms: 0 + - #6 + host_id: 0 + host_perms: 0 + - #7 + host_id: 0 + host_perms: 0 + - #8 + host_id: 0 + host_perms: 0 + - #9 + host_id: 0 + host_perms: 0 + - #10 + host_id: 0 + host_perms: 0 + - #11 + host_id: 0 + host_perms: 0 + - #12 + host_id: 0 + host_perms: 0 + - #13 + host_id: 0 + host_perms: 0 + - #14 + host_id: 0 + host_perms: 0 + - #15 + host_id: 0 + host_perms: 0 + - #16 + host_id: 0 + host_perms: 0 + - #17 + host_id: 0 + host_perms: 0 + - #18 + host_id: 0 + host_perms: 0 + - #19 + host_id: 0 + host_perms: 0 + - #20 + host_id: 0 + host_perms: 0 + - #21 + host_id: 0 + host_perms: 0 + - #22 + host_id: 0 + host_perms: 0 + - #23 + host_id: 0 + host_perms: 0 + - #24 + host_id: 0 + host_perms: 0 + - #25 + host_id: 0 + host_perms: 0 + - #26 + host_id: 0 + host_perms: 0 + - #27 + host_id: 0 + host_perms: 0 + - #28 + host_id: 0 + host_perms: 0 + - #29 + host_id: 0 + host_perms: 0 + - #30 + host_id: 0 + host_perms: 0 + - #31 + host_id: 0 + host_perms: 0 + - #32 + host_id: 0 + host_perms: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci : 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size : 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0x5A + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock : 0x5A + allow_wildcard_unlock : 0x5A + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev : 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender : 0 + handover_to_host_id : 0 + rsvd: [0, 0, 0, 0] From patchwork Fri Jul 21 18:44:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811091 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=I3314ATm; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R6z8W6bpsz20Fh for ; Sat, 22 Jul 2023 04:48:11 +1000 (AEST) Received: from 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ESMTPS id 36LIkVNs077270 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 21 Jul 2023 13:46:31 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 21 Jul 2023 13:46:30 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jul 2023 13:46:30 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloW131068; Fri, 21 Jul 2023 13:46:25 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 15/23] am625: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img Date: Sat, 22 Jul 2023 00:14:38 +0530 Message-ID: <20230721184446.5821-16-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Support added for HS-SE, HS-FS and GP boot binaries for AM62. HS-SE: * tiboot3-am62x-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-am62x-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am62x-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by AM62 requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-am625-r5-sk.dts | 1 + arch/arm/dts/k3-am625-sk-binman.dtsi | 463 +++++++++++++++++++++++++++ arch/arm/dts/k3-am625-sk-u-boot.dtsi | 2 + board/ti/am62x/Kconfig | 2 + 4 files changed, 468 insertions(+) create mode 100644 arch/arm/dts/k3-am625-sk-binman.dtsi diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts index 78df7cec3f..3ec5bad735 100644 --- a/arch/arm/dts/k3-am625-r5-sk.dts +++ b/arch/arm/dts/k3-am625-r5-sk.dts @@ -9,6 +9,7 @@ #include "k3-am62-ddr.dtsi" #include "k3-am625-sk-u-boot.dtsi" +#include "k3-am625-sk-binman.dtsi" / { aliases { diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi new file mode 100644 index 0000000000..b468d959b5 --- /dev/null +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -0,0 +1,463 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-binman.dtsi" + +#ifdef CONFIG_TARGET_AM625_R5_EVM + +&binman { + tiboot3-am62x-hs-evm.bin { + filename = "tiboot3-am62x-hs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>, + <&combined_dm_cfg>, <&sysfw_inner_cert>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl>; + content-sysfw = <&ti_fs_enc>; + content-sysfw-data = <&combined_tifs_cfg>; + content-sysfw-inner-cert = <&sysfw_inner_cert>; + content-dm-data = <&combined_dm_cfg>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c3a800>; + }; + u_boot_spl: u-boot-spl { + no-expanded; + }; + ti_fs_enc: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-am62x-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-am62x-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { + tiboot3-am62x-hs-fs-evm.bin { + filename = "tiboot3-am62x-hs-fs-evm.bin"; + symlink = "tiboot3.bin"; + ti-secure-rom { + content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>, + <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs>; + content-sysfw = <&ti_fs_enc_fs>; + content-sysfw-data = <&combined_tifs_cfg_fs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; + content-dm-data = <&combined_dm_cfg_fs>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c3a800>; + }; + u_boot_spl_fs: u-boot-spl { + no-expanded; + }; + ti_fs_enc_fs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_fs: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert_fs: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg_fs: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { + tiboot3-am62x-gp-evm.bin { + filename = "tiboot3-am62x-gp-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_unsigned>, <&ti_fs_gp>, + <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; + combined; + dm-data; + content-sbl = <&u_boot_spl_unsigned>; + load = <0x43c00000>; + content-sysfw = <&ti_fs_gp>; + load-sysfw = <0x40000>; + content-sysfw-data = <&combined_tifs_cfg_gp>; + load-sysfw-data = <0x67000>; + content-dm-data = <&combined_dm_cfg_gp>; + load-dm-data = <0x43c3a800>; + sw-rev = <1>; + keyfile = "ti-degenerate-key.pem"; + }; + u_boot_spl_unsigned: u-boot-spl { + no-expanded; + }; + ti_fs_gp: ti-fs-gp.bin { + filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + combined_dm_cfg_gp: combined-dm-cfg-gp.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + + }; +}; + +#endif + +#ifdef CONFIG_TARGET_AM625_A53_EVM + +#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" +#define SPL_AM625_SK_DTB "spl/dts/k3-am625-sk.dtb" + +#define UBOOT_NODTB "u-boot-nodtb.bin" +#define AM625_SK_DTB "arch/arm/dts/k3-am625-sk.dtb" + +&binman { + ti-dm { + filename = "ti-dm.bin"; + blob-ext { + filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + ti-spl { + filename = "tispl.bin"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = ; + entry = ; + ti-secure { + content = <&atf>; + keyfile = "custMpk.pem"; + }; + atf: atf-bl31 { + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + ti-secure { + content = <&tee>; + keyfile = "custMpk.pem"; + }; + tee: tee-os { + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + ti-secure { + content = <&dm>; + keyfile = "custMpk.pem"; + }; + dm: blob-ext { + filename = "ti-dm.bin"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = ; + entry = ; + ti-secure { + content = <&u_boot_spl_nodtb>; + keyfile = "custMpk.pem"; + }; + u_boot_spl_nodtb: blob-ext { + filename = SPL_NODTB; + }; + }; + + fdt-0 { + description = "k3-am625-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_am625_sk_dtb>; + keyfile = "custMpk.pem"; + }; + spl_am625_sk_dtb: blob-ext { + filename = SPL_AM625_SK_DTB; + }; + + }; + + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am625-sk"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + filename = "u-boot.img"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for AM625 board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = ; + ti-secure { + content = <&u_boot_nodtb>; + keyfile = "custMpk.pem"; + }; + u_boot_nodtb: u-boot-nodtb { + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-am625-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&am625_sk_dtb>; + keyfile = "custMpk.pem"; + }; + am625_sk_dtb: blob-ext { + filename = AM625_SK_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am625-sk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + + }; + }; + }; +}; + +&binman { + ti-spl_unsigned { + filename = "tispl.bin_unsigned"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = ; + entry = ; + atf-bl31 { + filename = "bl31.bin"; + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + tee-os { + filename = "tee-raw.bin"; + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + blob-ext { + filename = "ti-dm.bin"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = ; + entry = ; + blob { + filename = "spl/u-boot-spl-nodtb.bin"; + }; + }; + + fdt-0 { + description = "k3-am625-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = SPL_AM625_SK_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am625-sk"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot_unsigned { + filename = "u-boot.img_unsigned"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for AM625 board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = ; + blob { + filename = UBOOT_NODTB; + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-am625-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = AM625_SK_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am625-sk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; +#endif diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi index 249155733a..a60c37f1db 100644 --- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi @@ -4,6 +4,8 @@ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ */ +#include "k3-am625-sk-binman.dtsi" + / { chosen { stdout-path = "serial2:115200n8"; diff --git a/board/ti/am62x/Kconfig b/board/ti/am62x/Kconfig index 5e8dfa3cc4..cd17e939e5 100644 --- a/board/ti/am62x/Kconfig +++ b/board/ti/am62x/Kconfig @@ -10,6 +10,7 @@ choice config TARGET_AM625_A53_EVM bool "TI K3 based AM625 EVM running on A53" select ARM64 + select BINMAN config TARGET_AM625_R5_EVM bool "TI K3 based AM625 EVM running on R5" @@ -19,6 +20,7 @@ config TARGET_AM625_R5_EVM select RAM select SPL_RAM select K3_DDRSS + select BINMAN imply SYS_K3_SPL_ATF endchoice From patchwork Fri Jul 21 18:44:39 2023 Content-Type: text/plain; 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22 Jul 2023 00:14:39 +0530 Message-ID: <20230721184446.5821-17-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Added YAML configs for AM62ax Signed-off-by: Neha Malcom Francis --- board/ti/am62ax/board-cfg.yaml | 36 + board/ti/am62ax/pm-cfg.yaml | 12 + board/ti/am62ax/rm-cfg.yaml | 1151 ++++++++++++++++++++++++++++++ board/ti/am62ax/sec-cfg.yaml | 379 ++++++++++ board/ti/am62ax/tifs-rm-cfg.yaml | 1011 ++++++++++++++++++++++++++ 5 files changed, 2589 insertions(+) create mode 100644 board/ti/am62ax/board-cfg.yaml create mode 100644 board/ti/am62ax/pm-cfg.yaml create mode 100644 board/ti/am62ax/rm-cfg.yaml create mode 100644 board/ti/am62ax/sec-cfg.yaml create mode 100644 board/ti/am62ax/tifs-rm-cfg.yaml diff --git a/board/ti/am62ax/board-cfg.yaml b/board/ti/am62ax/board-cfg.yaml new file mode 100644 index 0000000000..4aa8ddd104 --- /dev/null +++ b/board/ti/am62ax/board-cfg.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for AM62ax +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable : 0x5A + main_isolation_hostid : 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor : 0x1 + scaling_profile : 0x1 + disable_main_nav_secure_proxy : 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size : 0x10 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables : 0x00 + trace_src_enables : 0x00 diff --git a/board/ti/am62ax/pm-cfg.yaml b/board/ti/am62ax/pm-cfg.yaml new file mode 100644 index 0000000000..3ad182ae17 --- /dev/null +++ b/board/ti/am62ax/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for AM62ax +# + +--- + +pm-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 diff --git a/board/ti/am62ax/rm-cfg.yaml b/board/ti/am62ax/rm-cfg.yaml new file mode 100644 index 0000000000..15c4017bda --- /dev/null +++ b/board/ti/am62ax/rm-cfg.yaml @@ -0,0 +1,1151 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62ax +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size : 356 + host_cfg_entries: + - #1 + host_id: 12 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #2 + host_id: 30 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #3 + host_id: 36 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #4 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #5 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #6 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #7 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #8 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #9 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #10 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #11 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #12 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #13 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #14 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #15 + host_id: 0 + allowed_atype : 0 + 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+ host_id: 128 + reserved: 0 + + - + start_resource: 0 + num_resource: 1 + type: 12739 + host_id: 128 + reserved: 0 + + - + start_resource: 0 + num_resource: 6 + type: 12750 + host_id: 12 + reserved: 0 + + - + start_resource: 0 + num_resource: 6 + type: 12769 + host_id: 12 + reserved: 0 + + - + start_resource: 0 + num_resource: 8 + type: 12810 + host_id: 12 + reserved: 0 + + - + start_resource: 12288 + num_resource: 128 + type: 12813 + host_id: 12 + reserved: 0 + + - + start_resource: 3072 + num_resource: 6 + type: 12828 + host_id: 128 + reserved: 0 + + - + start_resource: 3584 + num_resource: 6 + type: 12829 + host_id: 128 + reserved: 0 + + - + start_resource: 4096 + num_resource: 6 + type: 12830 + host_id: 128 + reserved: 0 diff --git a/board/ti/am62ax/sec-cfg.yaml b/board/ti/am62ax/sec-cfg.yaml new file mode 100644 index 0000000000..f0ad20c5a6 --- /dev/null +++ b/board/ti/am62ax/sec-cfg.yaml @@ -0,0 +1,379 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security configuration for AM62ax +# + +--- + +sec-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - #1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - #1 + host_id: 0 + supervisor_host_id: 0 + - #2 + host_id: 0 + supervisor_host_id: 0 + - #3 + host_id: 0 + supervisor_host_id: 0 + - #4 + host_id: 0 + supervisor_host_id: 0 + - #5 + host_id: 0 + supervisor_host_id: 0 + - #6 + host_id: 0 + supervisor_host_id: 0 + - #7 + host_id: 0 + supervisor_host_id: 0 + - #8 + host_id: 0 + supervisor_host_id: 0 + - #9 + host_id: 0 + supervisor_host_id: 0 + - #10 + host_id: 0 + supervisor_host_id: 0 + - #11 + host_id: 0 + supervisor_host_id: 0 + - #12 + host_id: 0 + supervisor_host_id: 0 + - #13 + host_id: 0 + supervisor_host_id: 0 + - #14 + host_id: 0 + supervisor_host_id: 0 + - #15 + host_id: 0 + supervisor_host_id: 0 + - #16 + host_id: 0 + supervisor_host_id: 0 + - #17 + host_id: 0 + supervisor_host_id: 0 + - #18 + host_id: 0 + supervisor_host_id: 0 + - #19 + host_id: 0 + supervisor_host_id: 0 + - #20 + host_id: 0 + supervisor_host_id: 0 + - #21 + host_id: 0 + supervisor_host_id: 0 + - #22 + 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host_perms: 0 + - #13 + host_id: 0 + host_perms: 0 + - #14 + host_id: 0 + host_perms: 0 + - #15 + host_id: 0 + host_perms: 0 + - #16 + host_id: 0 + host_perms: 0 + - #17 + host_id: 0 + host_perms: 0 + - #18 + host_id: 0 + host_perms: 0 + - #19 + host_id: 0 + host_perms: 0 + - #20 + host_id: 0 + host_perms: 0 + - #21 + host_id: 0 + host_perms: 0 + - #22 + host_id: 0 + host_perms: 0 + - #23 + host_id: 0 + host_perms: 0 + - #24 + host_id: 0 + host_perms: 0 + - #25 + host_id: 0 + host_perms: 0 + - #26 + host_id: 0 + host_perms: 0 + - #27 + host_id: 0 + host_perms: 0 + - #28 + host_id: 0 + host_perms: 0 + - #29 + host_id: 0 + host_perms: 0 + - #30 + host_id: 0 + host_perms: 0 + - #31 + host_id: 0 + host_perms: 0 + - #32 + host_id: 0 + host_perms: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci : 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size : 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0x5A + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock : 0x5A + allow_wildcard_unlock : 0x5A + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev : 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender : 0 + handover_to_host_id : 0 + rsvd: [0, 0, 0, 0] diff --git a/board/ti/am62ax/tifs-rm-cfg.yaml b/board/ti/am62ax/tifs-rm-cfg.yaml new file mode 100644 index 0000000000..0b1980eb7b --- /dev/null +++ b/board/ti/am62ax/tifs-rm-cfg.yaml @@ -0,0 +1,1011 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62AX +# + +--- + +tifs-rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size : 356 + host_cfg_entries: + - #1 + host_id: 12 + allowed_atype : 0x2A + allowed_qos : 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host_id: 12 + reserved: 0 + + - + start_resource: 23 + num_resource: 1 + type: 1971 + host_id: 12 + reserved: 0 + + - + start_resource: 43 + num_resource: 8 + type: 1972 + host_id: 12 + reserved: 0 + + - + start_resource: 0 + num_resource: 1 + type: 2112 + host_id: 128 + reserved: 0 + + - + start_resource: 2 + num_resource: 2 + type: 2122 + host_id: 12 + reserved: 0 + + - + start_resource: 0 + num_resource: 6 + type: 12750 + host_id: 12 + reserved: 0 + + - + start_resource: 0 + num_resource: 6 + type: 12769 + host_id: 12 + reserved: 0 + + - + start_resource: 0 + num_resource: 8 + type: 12810 + host_id: 12 + reserved: 0 + + - + start_resource: 3072 + num_resource: 6 + type: 12828 + host_id: 128 + reserved: 0 + + - + start_resource: 3584 + num_resource: 6 + type: 12829 + host_id: 128 + reserved: 0 + + - + start_resource: 4096 + num_resource: 6 + type: 12830 + host_id: 128 + reserved: 0 From patchwork Fri Jul 21 18:44:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811094 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=yvTlCURs; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R6z8y4ZwWz20Fh for ; Sat, 22 Jul 2023 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lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 36LIkihM006334 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 21 Jul 2023 13:46:44 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 21 Jul 2023 13:46:43 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jul 2023 13:46:43 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloY131068; Fri, 21 Jul 2023 13:46:37 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 17/23] am62a: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img Date: Sat, 22 Jul 2023 00:14:40 +0530 Message-ID: <20230721184446.5821-18-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Support added for HS-SE, HS-FS and GP boot binaries for AM62ax. HS-SE: * tiboot3-am62ax-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-am62ax-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am62ax-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by AM62ax requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-am62a-sk-binman.dtsi | 466 +++++++++++++++++++++++++++ arch/arm/dts/k3-am62a7-r5-sk.dts | 1 + arch/arm/dts/k3-am62a7-sk.dts | 1 + board/ti/am62ax/Kconfig | 2 + 4 files changed, 470 insertions(+) create mode 100644 arch/arm/dts/k3-am62a-sk-binman.dtsi diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi new file mode 100644 index 0000000000..a79d3f1127 --- /dev/null +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -0,0 +1,466 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-binman.dtsi" + +#ifdef CONFIG_TARGET_AM62A7_R5_EVM + +&rcfg_yaml_tifs { + config = "tifs-rm-cfg.yaml"; +}; + +&binman { + tiboot3-am62ax-hs-evm.bin { + filename = "tiboot3-am62ax-hs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>, + <&combined_dm_cfg>, <&sysfw_inner_cert>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl>; + content-sysfw = <&ti_fs_enc>; + content-sysfw-data = <&combined_tifs_cfg>; + content-sysfw-inner-cert = <&sysfw_inner_cert>; + content-dm-data = <&combined_dm_cfg>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c3a800>; + }; + u_boot_spl: u-boot-spl { + no-expanded; + }; + ti_fs_enc: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { + tiboot3-am62ax-hs-fs-evm.bin { + filename = "tiboot3-am62ax-hs-fs-evm.bin"; + symlink = "tiboot3.bin"; + ti-secure-rom { + content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>, + <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs>; + content-sysfw = <&ti_fs_enc_fs>; + content-sysfw-data = <&combined_tifs_cfg_fs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; + content-dm-data = <&combined_dm_cfg_fs>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c3a800>; + }; + u_boot_spl_fs: u-boot-spl { + no-expanded; + }; + ti_fs_enc_fs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_fs: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert_fs: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg_fs: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { + tiboot3-am62ax-gp-evm.bin { + filename = "tiboot3-am62ax-gp-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_unsigned>, <&ti_fs_gp>, + <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; + combined; + dm-data; + content-sbl = <&u_boot_spl_unsigned>; + load = <0x43c00000>; + content-sysfw = <&ti_fs_gp>; + load-sysfw = <0x40000>; + content-sysfw-data = <&combined_tifs_cfg_gp>; + load-sysfw-data = <0x67000>; + content-dm-data = <&combined_dm_cfg_gp>; + load-dm-data = <0x43c3a800>; + sw-rev = <1>; + keyfile = "ti-degenerate-key.pem"; + }; + u_boot_spl_unsigned: u-boot-spl { + no-expanded; + }; + ti_fs_gp: ti-fs-gp.bin { + filename = "ti-sysfw/ti-fs-firmware-am62ax-gp.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + combined_dm_cfg_gp: combined-dm-cfg-gp.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +#endif + +#ifdef CONFIG_TARGET_AM62A7_A53_EVM + +#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" +#define SPL_AM62A7_SK_DTB "spl/dts/k3-am62a7-sk.dtb" + +#define UBOOT_NODTB "u-boot-nodtb.bin" +#define AM62A7_SK_DTB "arch/arm/dts/k3-am62a7-sk.dtb" + +&binman { + ti-dm { + filename = "ti-dm.bin"; + blob-ext { + filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + ti-spl { + filename = "tispl.bin"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = ; + entry = ; + ti-secure { + content = <&atf>; + keyfile = "custMpk.pem"; + }; + atf: atf-bl31 { + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + ti-secure { + content = <&tee>; + keyfile = "custMpk.pem"; + }; + tee: tee-os { + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + ti-secure { + content = <&dm>; + keyfile = "custMpk.pem"; + }; + dm: blob-ext { + filename = "ti-dm.bin"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = ; + entry = ; + ti-secure { + content = <&u_boot_spl_nodtb>; + keyfile = "custMpk.pem"; + }; + u_boot_spl_nodtb: blob-ext { + filename = SPL_NODTB; + }; + }; + + fdt-0 { + description = "k3-am62a7-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_am62a7_sk_dtb>; + keyfile = "custMpk.pem"; + }; + spl_am62a7_sk_dtb: blob-ext { + filename = SPL_AM62A7_SK_DTB; + }; + + }; + + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62a7-sk"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + filename = "u-boot.img"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for AM62Ax board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = ; + ti-secure { + content = <&u_boot_nodtb>; + keyfile = "custMpk.pem"; + }; + u_boot_nodtb: u-boot-nodtb { + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-am62a7-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&am62a7_sk_dtb>; + keyfile = "custMpk.pem"; + }; + am62a7_sk_dtb: blob-ext { + filename = AM62A7_SK_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62a7-sk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + + }; + }; + }; +}; + +&binman { + ti-spl_unsigned { + filename = "tispl.bin_unsigned"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = ; + entry = ; + atf-bl31 { + filename = "bl31.bin"; + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + tee-os { + filename = "tee-raw.bin"; + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + blob-ext { + filename = "ti-dm.bin"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = ; + entry = ; + blob { + filename = "spl/u-boot-spl-nodtb.bin"; + }; + }; + + fdt-0 { + description = "k3-am62a7-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = SPL_AM62A7_SK_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62a7-sk"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot_unsigned { + filename = "u-boot.img_unsigned"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for AM62Ax board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = ; + blob { + filename = UBOOT_NODTB; + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-am62a7-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = AM62A7_SK_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62a7-sk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; +#endif diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts index cc4b179e27..bbbd9e51d6 100644 --- a/arch/arm/dts/k3-am62a7-r5-sk.dts +++ b/arch/arm/dts/k3-am62a7-r5-sk.dts @@ -7,6 +7,7 @@ #include "k3-am62a7-sk.dts" #include "k3-am62a-ddr-1866mhz-32bit.dtsi" #include "k3-am62a-ddr.dtsi" +#include "k3-am62a-sk-binman.dtsi" #include "k3-am62a7-sk-u-boot.dtsi" diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts index b08a083d72..270e669f65 100644 --- a/arch/arm/dts/k3-am62a7-sk.dts +++ b/arch/arm/dts/k3-am62a7-sk.dts @@ -10,6 +10,7 @@ #include #include #include "k3-am62a7.dtsi" +#include "k3-am62a-sk-binman.dtsi" / { compatible = "ti,am62a7-sk", "ti,am62a7"; diff --git a/board/ti/am62ax/Kconfig b/board/ti/am62ax/Kconfig index 9b868e4553..61f289facc 100644 --- a/board/ti/am62ax/Kconfig +++ b/board/ti/am62ax/Kconfig @@ -10,6 +10,7 @@ choice config TARGET_AM62A7_A53_EVM bool "TI K3 based AM62A7 EVM running on A53" select ARM64 + select BINMAN imply BOARD imply SPL_BOARD imply TI_I2C_BOARD_DETECT @@ -22,6 +23,7 @@ config TARGET_AM62A7_R5_EVM select RAM select SPL_RAM select K3_DDRSS + select BINMAN imply SYS_K3_SPL_ATF imply TI_I2C_BOARD_DETECT From patchwork Fri Jul 21 18:44:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811096 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Fri, 21 Jul 2023 13:46:50 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloZ131068; Fri, 21 Jul 2023 13:46:44 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 18/23] arm: k3-am65x-iot2050: Use binman for tispl.bin for iot2050 Date: Sat, 22 Jul 2023 00:14:41 +0530 Message-ID: <20230721184446.5821-19-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Move to using binman to generate tispl.bin which is used to generate the final flash.bin bootloader for iot2050 boards. Cc: Jan Kiszka Reviewed-by: Simon Glass Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-am65-iot2050-boot-image.dtsi | 75 +++++++++++++++++++- 1 file changed, 74 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi index 03ccc54329..7bfa4eebb9 100644 --- a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi @@ -26,9 +26,82 @@ missing-msg = "iot2050-seboot"; }; - blob@0x180000 { + fit@0x180000 { offset = <0x180000>; filename = "tispl.bin"; + pad-byte = <0xff>; + description = "Configuration to load ATF and SPL"; + + images { + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = ; + entry = ; + atf: atf-bl31 { + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + tee: tee-os { + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + blob-ext { + filename = "/dev/null"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = ; + entry = ; + u_boot_spl_nodtb: blob-ext { + filename = "spl/u-boot-spl-nodtb.bin"; + }; + }; + + fdt-0 { + description = "k3-am65-iot2050-spl.dtb"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + spl_am65x_evm_dtb: blob-ext { + filename = "spl/dts/k3-am65-iot2050-spl.dtb"; + }; + }; + }; + + configurations { + default = "spl"; + spl { + fdt = "fdt-0"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + }; + }; }; fit@0x380000 { From patchwork Fri Jul 21 18:44:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811095 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Fri, 21 Jul 2023 13:46:56 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jul 2023 13:46:56 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloa131068; Fri, 21 Jul 2023 13:46:51 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 19/23] k3: tools: config.mk: Update makefile and remove scripts Date: Sat, 22 Jul 2023 00:14:42 +0530 Message-ID: <20230721184446.5821-20-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Since binman is used to package bootloader images for all K3 devices, we do not have to rely on the earlier methods to package them. Scripts that were used to generate x509 certificate for tiboot3.bin and generate tispl.bin, u-boot.img have been removed. Reviewed-by: Simon Glass Signed-off-by: Neha Malcom Francis --- arch/arm/mach-k3/config.mk | 103 --------------- tools/k3_fit_atf.sh | 123 ----------------- tools/k3_gen_x509_cert.sh | 262 ------------------------------------- 3 files changed, 488 deletions(-) delete mode 100644 arch/arm/mach-k3/config.mk delete mode 100755 tools/k3_fit_atf.sh delete mode 100755 tools/k3_gen_x509_cert.sh diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk deleted file mode 100644 index cbf9c10210..0000000000 --- a/arch/arm/mach-k3/config.mk +++ /dev/null @@ -1,103 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ -# Lokesh Vutla - -ifdef CONFIG_SPL_BUILD - -# Openssl is required to generate x509 certificate. -# Error out if openssl is not available. -ifeq ($(shell which openssl),) -$(error "No openssl in $(PATH), consider installing openssl") -endif - -IMAGE_SIZE= $(shell cat $(obj)/u-boot-spl.bin | wc -c) -MAX_SIZE= $(shell printf "%d" $(CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE)) - -ifeq ($(CONFIG_SYS_K3_KEY), "") -KEY="" -# On HS use real key or warn if not available -ifeq ($(CONFIG_TI_SECURE_DEVICE),y) -ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/keys/custMpk.pem),) -KEY=$(TI_SECURE_DEV_PKG)/keys/custMpk.pem -else -$(warning "WARNING: signing key not found. Random key will NOT work on HS hardware!") -endif -endif -else -KEY=$(patsubst "%",$(srctree)/%,$(CONFIG_SYS_K3_KEY)) -endif - -# X509 SWRV default -SWRV = $(CONFIG_K3_X509_SWRV) -# On HS use SECDEV provided software revision or warn if not available -ifeq ($(CONFIG_TI_SECURE_DEVICE),y) -ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/keys/swrv.txt),) -SWRV= $(shell cat $(TI_SECURE_DEV_PKG)/keys/swrv.txt) -else -$(warning "WARNING: Software revision file not found. Default may not work on HS hardware.") -endif -endif - -# tiboot3.bin is mandated by ROM and ROM only supports R5 boot. -# So restrict tiboot3.bin creation for CPU_V7R. -ifdef CONFIG_CPU_V7R -image_check: $(obj)/u-boot-spl.bin FORCE - @if [ $(IMAGE_SIZE) -gt $(MAX_SIZE) ]; then \ - echo "===============================================" >&2; \ - echo "ERROR: Final Image too big. " >&2; \ - echo "$< size = $(IMAGE_SIZE), max size = $(MAX_SIZE)" >&2; \ - echo "===============================================" >&2; \ - exit 1; \ - fi - -tiboot3.bin: image_check FORCE - $(srctree)/tools/k3_gen_x509_cert.sh -c 16 -b $(obj)/u-boot-spl.bin \ - -o $@ -l $(CONFIG_SPL_TEXT_BASE) -r $(SWRV) -k $(KEY) - -INPUTS-y += tiboot3.bin -endif - -ifdef CONFIG_ARM64 - -ifeq ($(CONFIG_SOC_K3_J721E),) -export DM := /dev/null -endif - -ifeq ($(CONFIG_TI_SECURE_DEVICE),y) -SPL_ITS := u-boot-spl-k3_HS.its -$(SPL_ITS): export IS_HS=1 -INPUTS-y += tispl.bin_HS -INPUTS-y += tispl.bin -tispl.bin: $(obj)/u-boot-spl-nodtb.bin_HS $(patsubst %,$(obj)/dts/%.dtb_HS,$(subst ",,$(CONFIG_SPL_OF_LIST))) -else -SPL_ITS := u-boot-spl-k3.its -INPUTS-y += tispl.bin -endif - -ifeq ($(CONFIG_SPL_OF_LIST),) -LIST_OF_DTB := $(CONFIG_DEFAULT_DEVICE_TREE) -else -LIST_OF_DTB := $(CONFIG_SPL_OF_LIST) -endif - -quiet_cmd_k3_mkits = MKITS $@ -cmd_k3_mkits = \ - $(srctree)/tools/k3_fit_atf.sh \ - $(CONFIG_K3_ATF_LOAD_ADDR) \ - $(patsubst %,$(obj)/dts/%.dtb,$(subst ",,$(LIST_OF_DTB))) > $@ - -$(SPL_ITS): FORCE - $(call cmd,k3_mkits) -endif - -else - -ifeq ($(CONFIG_TI_SECURE_DEVICE),y) -INPUTS-y += u-boot.img_HS -else -INPUTS-y += u-boot.img -endif -endif - -include $(srctree)/arch/arm/mach-k3/config_secure.mk diff --git a/tools/k3_fit_atf.sh b/tools/k3_fit_atf.sh deleted file mode 100755 index 7bc07ad074..0000000000 --- a/tools/k3_fit_atf.sh +++ /dev/null @@ -1,123 +0,0 @@ -#!/bin/sh -# SPDX-License-Identifier: GPL-2.0+ -# -# script to generate FIT image source for K3 Family boards with -# ATF, OPTEE, SPL and multiple device trees (given on the command line). -# Inspired from board/sunxi/mksunxi_fit_atf.sh -# -# usage: $0 [ [&2 - ATF=/dev/null -fi - -[ -z "$TEE" ] && TEE="bl32.bin" - -if [ ! -f $TEE ]; then - echo "WARNING OPTEE file $TEE NOT found, resulting might be non-functional" >&2 - TEE=/dev/null -fi - -[ -z "$DM" ] && DM="dm.bin" - -if [ ! -e $DM ]; then - echo "WARNING DM file $DM NOT found, resulting might be non-functional" >&2 - DM=/dev/null -fi - -if [ ! -z "$IS_HS" ]; then - HS_APPEND=_HS -fi - -cat << __HEADER_EOF -/dts-v1/; - -/ { - description = "Configuration to load ATF and SPL"; - #address-cells = <1>; - - images { - atf { - description = "ARM Trusted Firmware"; - data = /incbin/("$ATF"); - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <$1>; - entry = <$1>; - }; - tee { - description = "OPTEE"; - data = /incbin/("$TEE"); - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - }; - dm { - description = "DM binary"; - data = /incbin/("$DM"); - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; - }; - spl { - description = "SPL (64-bit)"; - data = /incbin/("spl/u-boot-spl-nodtb.bin$HS_APPEND"); - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <0x80080000>; - entry = <0x80080000>; - }; -__HEADER_EOF - -# shift through ATF load address in the command line arguments -shift - -for dtname in $* -do - cat << __FDT_IMAGE_EOF - $(basename $dtname) { - description = "$(basename $dtname .dtb)"; - data = /incbin/("$dtname$HS_APPEND"); - type = "flat_dt"; - arch = "arm"; - compression = "none"; - }; -__FDT_IMAGE_EOF -done - -cat << __CONF_HEADER_EOF - }; - configurations { - default = "$(basename $1)"; - -__CONF_HEADER_EOF - -for dtname in $* -do - cat << __CONF_SECTION_EOF - $(basename $dtname) { - description = "$(basename $dtname .dtb)"; - firmware = "atf"; - loadables = "tee", "dm", "spl"; - fdt = "$(basename $dtname)"; - }; -__CONF_SECTION_EOF -done - -cat << __ITS_EOF - }; -}; -__ITS_EOF diff --git a/tools/k3_gen_x509_cert.sh b/tools/k3_gen_x509_cert.sh deleted file mode 100755 index d9cde07417..0000000000 --- a/tools/k3_gen_x509_cert.sh +++ /dev/null @@ -1,262 +0,0 @@ -#!/bin/bash -# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -# -# Script to add K3 specific x509 cetificate to a binary. -# - -# Variables -OUTPUT=tiboot3.bin -TEMP_X509=x509-temp.cert -CERT=certificate.bin -RAND_KEY=eckey.pem -LOADADDR=0x41c00000 -BOOTCORE_OPTS=0 -BOOTCORE=16 -DEBUG_TYPE=0 -SWRV=1 - -gen_degen_template() { -cat << 'EOF' > degen-template.txt - -asn1=SEQUENCE:rsa_key - -[rsa_key] -version=INTEGER:0 -modulus=INTEGER:0xDEGEN_MODULUS -pubExp=INTEGER:1 -privExp=INTEGER:1 -p=INTEGER:0xDEGEN_P -q=INTEGER:0xDEGEN_Q -e1=INTEGER:1 -e2=INTEGER:1 -coeff=INTEGER:0xDEGEN_COEFF -EOF -} - -# Generate x509 Template -gen_template() { -cat << 'EOF' > x509-template.txt - [ req ] - distinguished_name = req_distinguished_name - x509_extensions = v3_ca - prompt = no - dirstring_type = nobmp - - [ req_distinguished_name ] - C = US - ST = TX - L = Dallas - O = Texas Instruments Incorporated - OU = Processors - CN = TI support - emailAddress = support@ti.com - - [ v3_ca ] - basicConstraints = CA:true - 1.3.6.1.4.1.294.1.1 = ASN1:SEQUENCE:boot_seq - 1.3.6.1.4.1.294.1.2 = ASN1:SEQUENCE:image_integrity - 1.3.6.1.4.1.294.1.3 = ASN1:SEQUENCE:swrv -# 1.3.6.1.4.1.294.1.4 = ASN1:SEQUENCE:encryption - 1.3.6.1.4.1.294.1.8 = ASN1:SEQUENCE:debug - - [ boot_seq ] - certType = INTEGER:TEST_CERT_TYPE - bootCore = INTEGER:TEST_BOOT_CORE - bootCoreOpts = INTEGER:TEST_BOOT_CORE_OPTS - destAddr = FORMAT:HEX,OCT:TEST_BOOT_ADDR - imageSize = INTEGER:TEST_IMAGE_LENGTH - - [ image_integrity ] - shaType = OID:2.16.840.1.101.3.4.2.3 - shaValue = FORMAT:HEX,OCT:TEST_IMAGE_SHA_VAL - - [ swrv ] - swrv = INTEGER:TEST_SWRV - -# [ encryption ] -# initalVector = FORMAT:HEX,OCT:TEST_IMAGE_ENC_IV -# randomString = FORMAT:HEX,OCT:TEST_IMAGE_ENC_RS -# iterationCnt = INTEGER:TEST_IMAGE_KEY_DERIVE_INDEX -# salt = FORMAT:HEX,OCT:TEST_IMAGE_KEY_DERIVE_SALT - - [ debug ] - debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000 - debugType = INTEGER:TEST_DEBUG_TYPE - coreDbgEn = INTEGER:0 - coreDbgSecEn = INTEGER:0 -EOF -} - -parse_key() { - sed '/ /s/://g' key.txt | \ - awk '!/ / {printf("\n%s\n", $0)}; / / {printf("%s", $0)}' | \ - sed 's/ //g' | \ - awk "/$1:/{getline; print}" -} - -gen_degen_key() { -# Generate a 4096 bit RSA Key - openssl genrsa -out key.pem 1024 >>/dev/null 2>&1 - openssl rsa -in key.pem -text -out key.txt >>/dev/null 2>&1 - DEGEN_MODULUS=$( parse_key 'modulus' ) - DEGEN_P=$( parse_key 'prime1' ) - DEGEN_Q=$( parse_key 'prime2' ) - DEGEN_COEFF=$( parse_key 'coefficient' ) - gen_degen_template - - sed -e "s/DEGEN_MODULUS/$DEGEN_MODULUS/"\ - -e "s/DEGEN_P/$DEGEN_P/" \ - -e "s/DEGEN_Q/$DEGEN_Q/" \ - -e "s/DEGEN_COEFF/$DEGEN_COEFF/" \ - degen-template.txt > degenerateKey.txt - - openssl asn1parse -genconf degenerateKey.txt -out degenerateKey.der >>/dev/null 2>&1 - openssl rsa -in degenerateKey.der -inform DER -outform PEM -out $RAND_KEY >>/dev/null 2>&1 - KEY=$RAND_KEY - rm key.pem key.txt degen-template.txt degenerateKey.txt degenerateKey.der -} - -declare -A options_help -usage() { - if [ -n "$*" ]; then - echo "ERROR: $*" - fi - echo -n "Usage: $0 " - for option in "${!options_help[@]}" - do - arg=`echo ${options_help[$option]}|cut -d ':' -f1` - if [ -n "$arg" ]; then - arg=" $arg" - fi - echo -n "[-$option$arg] " - done - echo - echo -e "\nWhere:" - for option in "${!options_help[@]}" - do - arg=`echo ${options_help[$option]}|cut -d ':' -f1` - txt=`echo ${options_help[$option]}|cut -d ':' -f2` - tb="\t\t\t" - if [ -n "$arg" ]; then - arg=" $arg" - tb="\t" - fi - echo -e " -$option$arg:$tb$txt" - done - echo - echo "Examples of usage:-" - echo "# Example of signing the SYSFW binary with rsa degenerate key" - echo " $0 -c 0 -b ti-sci-firmware-am6x.bin -o sysfw.bin -l 0x40000" - echo "# Example of signing the SPL binary with rsa degenerate key" - echo " $0 -c 16 -b spl/u-boot-spl.bin -o tiboot3.bin -l 0x41c00000" -} - -options_help[b]="bin_file:Bin file that needs to be signed" -options_help[k]="key_file:file with key inside it. If not provided script generates a rsa degenerate key." -options_help[o]="output_file:Name of the final output file. default to $OUTPUT" -options_help[c]="core_id:target core id on which the image would be running. Default to $BOOTCORE" -options_help[l]="loadaddr: Target load address of the binary in hex. Default to $LOADADDR" -options_help[d]="debug_type: Debug type, set to 4 to enable early JTAG. Default to $DEBUG_TYPE" -options_help[r]="SWRV: Software Rev for X509 certificate" - -while getopts "b:k:o:c:l:d:h:r:" opt -do - case $opt in - b) - BIN=$OPTARG - ;; - k) - KEY=$OPTARG - ;; - o) - OUTPUT=$OPTARG - ;; - l) - LOADADDR=$OPTARG - ;; - c) - BOOTCORE=$OPTARG - ;; - d) - DEBUG_TYPE=$OPTARG - ;; - r) - SWRV=$OPTARG - ;; - h) - usage - exit 0 - ;; - \?) - usage "Invalid Option '-$OPTARG'" - exit 1 - ;; - :) - usage "Option '-$OPTARG' Needs an argument." - exit 1 - ;; - esac -done - -if [ "$#" -eq 0 ]; then - usage "Arguments missing" - exit 1 -fi - -if [ -z "$BIN" ]; then - usage "Bin file missing in arguments" - exit 1 -fi - -# Generate rsa degenerate key if user doesn't provide a key -if [ -z "$KEY" ]; then - gen_degen_key -fi - -if [ $BOOTCORE == 0 ]; then # BOOTCORE M3, loaded by ROM - CERTTYPE=2 -elif [ $BOOTCORE == 16 ]; then # BOOTCORE R5, loaded by ROM - CERTTYPE=1 -else # Non BOOTCORE, loaded by SYSFW - BOOTCORE_OPTS_VER=$(printf "%01x" 1) - # Add input args option for SET and CLR flags. - BOOTCORE_OPTS_SETFLAG=$(printf "%08x" 0) - BOOTCORE_OPTS_CLRFLAG=$(printf "%08x" 0x100) # Clear FLAG_ARMV8_AARCH32 - BOOTCORE_OPTS="0x$BOOTCORE_OPTS_VER$BOOTCORE_OPTS_SETFLAG$BOOTCORE_OPTS_CLRFLAG" - # Set the cert type to zero. - # We are not using public/private key store now - CERTTYPE=$(printf "0x%08x" 0) -fi - -SHA_VAL=`openssl dgst -sha512 -hex $BIN | sed -e "s/^.*= //g"` -BIN_SIZE=`cat $BIN | wc -c` -ADDR=`printf "%08x" $LOADADDR` - -gen_cert() { - #echo "Certificate being generated :" - #echo " LOADADDR = 0x$ADDR" - #echo " IMAGE_SIZE = $BIN_SIZE" - #echo " CERT_TYPE = $CERTTYPE" - #echo " DEBUG_TYPE = $DEBUG_TYPE" - #echo " SWRV = $SWRV" - sed -e "s/TEST_IMAGE_LENGTH/$BIN_SIZE/" \ - -e "s/TEST_IMAGE_SHA_VAL/$SHA_VAL/" \ - -e "s/TEST_CERT_TYPE/$CERTTYPE/" \ - -e "s/TEST_BOOT_CORE_OPTS/$BOOTCORE_OPTS/" \ - -e "s/TEST_BOOT_CORE/$BOOTCORE/" \ - -e "s/TEST_BOOT_ADDR/$ADDR/" \ - -e "s/TEST_DEBUG_TYPE/$DEBUG_TYPE/" \ - -e "s/TEST_SWRV/$SWRV/" \ - x509-template.txt > $TEMP_X509 - openssl req -new -x509 -key $KEY -nodes -outform DER -out $CERT -config $TEMP_X509 -sha512 -} - -gen_template -gen_cert -cat $CERT $BIN > $OUTPUT - -# Remove all intermediate files -rm $TEMP_X509 $CERT x509-template.txt -if [ "$KEY" == "$RAND_KEY" ]; then - rm $RAND_KEY -fi From patchwork Fri Jul 21 18:44:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811097 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=hhQdUmfA; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R6z9b5njTz20Fh for ; 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Fri, 21 Jul 2023 13:47:03 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jul 2023 13:47:03 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIilob131068; Fri, 21 Jul 2023 13:46:57 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 20/23] doc: board: ti: Update documentation for binman flow Date: Sat, 22 Jul 2023 00:14:43 +0530 Message-ID: <20230721184446.5821-21-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Earlier documentation specified builds for generating bootloader images using an external TI repository k3-image-gen and core-secdev-k3. Modify this to using the binman flow so that user understands how to build the final boot images. Reviewed-by: Simon Glass Signed-off-by: Neha Malcom Francis --- board/ti/am65x/README | 350 ------------------------------- doc/board/ti/am62x_sk.rst | 75 ++++--- doc/board/ti/am65x_evm.rst | 420 +++++++++++++++++++++++++++++++++++++ doc/board/ti/j7200_evm.rst | 74 ++++--- doc/board/ti/j721e_evm.rst | 75 ++++--- doc/board/ti/k3.rst | 112 ++++------ 6 files changed, 584 insertions(+), 522 deletions(-) delete mode 100644 board/ti/am65x/README create mode 100644 doc/board/ti/am65x_evm.rst diff --git a/board/ti/am65x/README b/board/ti/am65x/README deleted file mode 100644 index 67081ce349..0000000000 --- a/board/ti/am65x/README +++ /dev/null @@ -1,350 +0,0 @@ -Introduction: -------------- -The AM65x family of SoCs is the first device family from K3 Multicore -SoC architecture, targeted for broad market and industrial control with -aim to meet the complex processing needs of modern embedded products. - -The device is built over three domains, each containing specific processing -cores, voltage domains and peripherals: -1. Wake-up (WKUP) domain: - - Device Management and Security Controller (DMSC) -2. Microcontroller (MCU) domain: - - Dual Core ARM Cortex-R5F processor -3. MAIN domain: - - Quad core 64-bit ARM Cortex-A53 - -More info can be found in TRM: http://www.ti.com/lit/pdf/spruid7 - -Boot Flow: ----------- -On AM65x family devices, ROM supports boot only via MCU(R5). This means that -bootloader has to run on R5 core. In order to meet this constraint, and for -the following reasons the boot flow is designed as mentioned: -1. Need to move away from R5 asap, so that we want to start *any* -firmware on the r5 cores like.... autosar can be loaded to receive CAN -response and other safety operations to be started. This operation is -very time critical and is applicable for all automotive use cases. -2. U-Boot on A53 should start other remotecores for various -applications. This should happen before running Linux. -3. In production boot flow, we might not like to use full u-boot, -instead use Flacon boot flow to reduce boot time. - -+------------------------------------------------------------------------+ -| DMSC | R5 | A53 | -+------------------------------------------------------------------------+ -| +--------+ | | | -| | Reset | | | | -| +--------+ | | | -| : | | | -| +--------+ | +-----------+ | | -| | *ROM* |----------|-->| Reset rls | | | -| +--------+ | +-----------+ | | -| | | | : | | -| | ROM | | : | | -| |services| | : | | -| | | | +-------------+ | | -| | | | | *R5 ROM* | | | -| | | | +-------------+ | | -| | |<---------|---|Load and auth| | | -| | | | | tiboot3.bin | | | -| | | | +-------------+ | | -| | | | : | | -| | | | : | | -| | | | : | | -| | | | +-------------+ | | -| | | | | *R5 SPL* | | | -| | | | +-------------+ | | -| | | | | Load | | | -| | | | | sysfw.itb | | | -| | Start | | +-------------+ | | -| | System |<---------|---| Start | | | -| |Firmware| | | SYSFW | | | -| +--------+ | +-------------+ | | -| : | | | | | -| +---------+ | | Load | | | -| | *SYSFW* | | | system | | | -| +---------+ | | Config data | | | -| | |<--------|---| | | | -| | | | +-------------+ | | -| | | | | | | | -| | | | | DDR | | | -| | | | | config | | | -| | | | +-------------+ | | -| | | | | | | | -| | |<--------|---| Start A53 | | | -| | | | | and Reset | | | -| | | | +-------------+ | | -| | | | | +-----------+ | -| | |---------|-----------------------|---->| Reset rls | | -| | | | | +-----------+ | -| | DMSC | | | : | -| |Services | | | +-----------+ | -| | |<--------|-----------------------|---->|*ATF/OPTEE*| | -| | | | | +-----------+ | -| | | | | : | -| | | | | +-----------+ | -| | |<--------|-----------------------|---->| *A53 SPL* | | -| | | | | +-----------+ | -| | | | | | Load | | -| | | | | | u-boot.img| | -| | | | | +-----------+ | -| | | | | : | -| | | | | +-----------+ | -| | |<--------|-----------------------|---->| *U-Boot* | | -| | | | | +-----------+ | -| | | | | | prompt | | -| | | | | +-----------+ | -| +---------+ | | | -| | | | -+------------------------------------------------------------------------+ - -- Here DMSC acts as master and provides all the critical services. R5/A53 -requests DMSC to get these services done as shown in the above diagram. - -Sources: --------- -1. SYSFW: - Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git - Branch: master - -2. ATF: - Tree: https://github.com/ARM-software/arm-trusted-firmware.git - Branch: master - -3. OPTEE: - Tree: https://github.com/OP-TEE/optee_os.git - Branch: master - -4. U-Boot: - Tree: http://git.denx.de/u-boot.git - Branch: master - -Build procedure: ----------------- -1. SYSFW: -$ make CROSS_COMPILE=arm-linux-gnueabihf- - -2. ATF: -$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed - -3. OPTEE: -$ make PLATFORM=k3-am65x CFG_ARM64_core=y - -4. U-Boot: - -4.1. R5: -$ make CROSS_COMPILE=arm-linux-gnueabihf- am65x_evm_r5_defconfig O=/tmp/r5 -$ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5 - -4.2. A53: -$ make CROSS_COMPILE=aarch64-linux-gnu- am65x_evm_a53_defconfig O=/tmp/a53 -$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a53 - -Target Images --------------- -Copy the below images to an SD card and boot: -- sysfw.itb from step 1 -- tiboot3.bin from step 4.1 -- tispl.bin, u-boot.img from 4.2 - -Image formats: --------------- - -- tiboot3.bin: - +-----------------------+ - | X.509 | - | Certificate | - | +-------------------+ | - | | | | - | | R5 | | - | | u-boot-spl.bin | | - | | | | - | +-------------------+ | - | | | | - | | FIT header | | - | | +---------------+ | | - | | | | | | - | | | DTB 1...N | | | - | | +---------------+ | | - | +-------------------+ | - +-----------------------+ - -- tispl.bin - +-----------------------+ - | | - | FIT HEADER | - | +-------------------+ | - | | | | - | | A53 ATF | | - | +-------------------+ | - | | | | - | | A53 OPTEE | | - | +-------------------+ | - | | | | - | | A53 SPL | | - | +-------------------+ | - | | | | - | | SPL DTB 1...N | | - | +-------------------+ | - +-----------------------+ - -- sysfw.itb - +-----------------------+ - | | - | FIT HEADER | - | +-------------------+ | - | | | | - | | sysfw.bin | | - | +-------------------+ | - | | | | - | | board config | | - | +-------------------+ | - | | | | - | | PM config | | - | +-------------------+ | - | | | | - | | RM config | | - | +-------------------+ | - | | | | - | | Secure config | | - | +-------------------+ | - +-----------------------+ - -eMMC: ------ -ROM supports booting from eMMC from boot0 partition offset 0x0 - -Flashing images to eMMC: - -The following commands can be used to download tiboot3.bin, tispl.bin, -u-boot.img, and sysfw.itb from an SD card and write them to the eMMC boot0 -partition at respective addresses. - -=> mmc dev 0 1 -=> fatload mmc 1 ${loadaddr} tiboot3.bin -=> mmc write ${loadaddr} 0x0 0x400 -=> fatload mmc 1 ${loadaddr} tispl.bin -=> mmc write ${loadaddr} 0x400 0x1000 -=> fatload mmc 1 ${loadaddr} u-boot.img -=> mmc write ${loadaddr} 0x1400 0x2000 -=> fatload mmc 1 ${loadaddr} sysfw.itb -=> mmc write ${loadaddr} 0x3600 0x800 - -To give the ROM access to the boot partition, the following commands must be -used for the first time: -=> mmc partconf 0 1 1 1 -=> mmc bootbus 0 1 0 0 - -To create a software partition for the rootfs, the following command can be -used: -=> gpt write mmc 0 ${partitions} - -eMMC layout: - - boot0 partition (8 MB) user partition - 0x0+----------------------------------+ 0x0+-------------------------+ - | tiboot3.bin (512 KB) | | | - 0x400+----------------------------------+ | | - | tispl.bin (2 MB) | | | -0x1400+----------------------------------+ | rootfs | - | u-boot.img (4 MB) | | | -0x3400+----------------------------------+ | | - | environment (128 KB) | | | -0x3500+----------------------------------+ | | - | backup environment (128 KB) | | | -0x3600+----------------------------------+ | | - | sysfw (1 MB) | | | -0x3E00+----------------------------------+ +-------------------------+ - -Kernel image and DT are expected to be present in the /boot folder of rootfs. -To boot kernel from eMMC, use the following commands: -=> setenv mmcdev 0 -=> setenv bootpart 0 -=> boot - -OSPI: ------ -ROM supports booting from OSPI from offset 0x0. - -Flashing images to OSPI: - -Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img, -and sysfw.itb over tftp and then flash those to OSPI at their respective -addresses. - -=> sf probe -=> tftp ${loadaddr} tiboot3.bin -=> sf update $loadaddr 0x0 $filesize -=> tftp ${loadaddr} tispl.bin -=> sf update $loadaddr 0x80000 $filesize -=> tftp ${loadaddr} u-boot.img -=> sf update $loadaddr 0x280000 $filesize -=> tftp ${loadaddr} sysfw.itb -=> sf update $loadaddr 0x6C0000 $filesize - -Flash layout for OSPI: - - 0x0 +----------------------------+ - | ospi.tiboot3(512K) | - | | - 0x80000 +----------------------------+ - | ospi.tispl(2M) | - | | - 0x280000 +----------------------------+ - | ospi.u-boot(4M) | - | | - 0x680000 +----------------------------+ - | ospi.env(128K) | - | | - 0x6A0000 +----------------------------+ - | ospi.env.backup (128K) | - | | - 0x6C0000 +----------------------------+ - | ospi.sysfw(1M) | - | | - 0x7C0000 +----------------------------+ - | padding (256k) | - 0x800000 +----------------------------+ - | ospi.rootfs(UBIFS) | - | | - +----------------------------+ - -Kernel Image and DT are expected to be present in the /boot folder of UBIFS -ospi.rootfs just like in SD card case. U-Boot looks for UBI volume named -"rootfs" for rootfs. - -To boot kernel from OSPI, at the U-Boot prompt: -=> setenv boot ubi -=> boot - -UART: ------ -ROM supports booting from MCU_UART0 via X-Modem protocol. The entire UART-based -boot process up to U-Boot (proper) prompt goes through different stages and uses -different UART peripherals as follows: - - WHO | Loading WHAT | HW Module | Protocol -----------+---------------+-------------+------------ -Boot ROM | tiboot3.bin | MCU_UART0 | X-Modem(*) -R5 SPL | sysfw.itb | MCU_UART0 | Y-Modem(*) -R5 SPL | tispl.bin | MAIN_UART0 | Y-Modem -A53 SPL | u-boot.img | MAIN_UART0 | Y-Modem - -(*) Note that in addition to X/Y-Modem related protocol timeouts the DMSC - watchdog timeout of 3min (typ.) needs to be observed until System Firmware - is fully loaded (from sysfw.itb) and started. - -Example bash script sequence for running on a Linux host PC feeding all boot -artifacts needed to the device: - -MCU_DEV=/dev/ttyUSB1 -MAIN_DEV=/dev/ttyUSB0 - -stty -F $MCU_DEV 115200 cs8 -cstopb -parenb -stty -F $MAIN_DEV 115200 cs8 -cstopb -parenb - -sb --xmodem tiboot3.bin > $MCU_DEV < $MCU_DEV -sb --ymodem sysfw.itb > $MCU_DEV < $MCU_DEV -sb --ymodem tispl.bin > $MAIN_DEV < $MAIN_DEV -sleep 1 -sb --xmodem u-boot.img > $MAIN_DEV < $MAIN_DEV diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst index 27d7b527c6..54e761c654 100644 --- a/doc/board/ti/am62x_sk.rst +++ b/doc/board/ti/am62x_sk.rst @@ -90,9 +90,9 @@ Below is the pictorial representation of boot flow: | | |----------|-----------------------|---->| Reset rls | | | | | | | +-----------+ | | | TIFS | | | : | - | |Services| | | +-----------+ | - | | |<---------|-----------------------|---->|*ATF/OPTEE*| | - | | | | | +-----------+ | + | |Services| | | +-------------+ | + | | |<---------|-----------------------|---->|*TF-A/OP-TEE*| | + | | | | | +-------------+ | | | | | | : | | | | | | +-----------+ | | | |<---------|-----------------------|---->| *A53 SPL* | | @@ -115,65 +115,76 @@ Below is the pictorial representation of boot flow: Sources: -------- -1. SYSFW: - Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git - Branch: master - -2. ATF: - Tree: https://github.com/ARM-software/arm-trusted-firmware.git +1. Trusted Firmware-A: + Tree: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/ Branch: master -3. OPTEE: +2. OP-TEE: Tree: https://github.com/OP-TEE/optee_os.git Branch: master -4. U-Boot: +3. U-Boot: Tree: https://source.denx.de/u-boot/u-boot Branch: master -5. TI Linux Firmware: +4. TI Linux Firmware: Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git Branch: ti-linux-firmware Build procedure: ---------------- -1. ATF: +1. Trusted Firmware-A: -.. code-block:: text +.. code-block:: bash - $ make CROSS_COMPILE=aarch64-none-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=lite SPD=opteed + $ make CROSS_COMPILE=aarch64-none-linux-gnu- ARCH=aarch64 PLAT=k3 \ + TARGET_BOARD=lite SPD=opteed -2. OPTEE: +2. OP-TEE: -.. code-block:: text +.. code-block:: bash - $ make PLATFORM=k3 CFG_ARM64_core=y CROSS_COMPILE=arm-none-linux-gnueabihf- CROSS_COMPILE64=aarch64-none-linux-gnu- + $ make PLATFORM=k3 CFG_ARM64_core=y CROSS_COMPILE=arm-none-linux-gnueabihf- \ + CROSS_COMPILE64=aarch64-none-linux-gnu- 3. U-Boot: * 3.1 R5: -.. code-block:: text - - $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- am62x_evm_r5_defconfig O=/tmp/r5 - $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- O=/tmp/r5 - $ cd - $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- SOC=am62x SBL=/tmp/r5/spl/u-boot-spl.bin SYSFW_PATH=/ti-sysfw/ti-fs-firmware-am62x-gp.bin +.. code-block:: bash -Use the tiboot3.bin generated from last command + $ make ARCH=arm am62x_evm_r5_defconfig + $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- \ + BINMAN_INDIRS= * 3.2 A53: -.. code-block:: text +.. code-block:: bash - $ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- am62x_evm_a53_defconfig O=/tmp/a53 - $ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- ATF=/build/k3/lite/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin DM=/ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f O=/tmp/a53 + $ make ARCH=arm am62x_evm_a53_defconfig + $ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- \ + BL31=/build/k3/lite/release/bl31.bin \ + TEE=/out/arm-plat-k3/core/tee-raw.bin \ + BINMAN_INDIRS= Target Images -------------- Copy the below images to an SD card and boot: - - tiboot3.bin from step 3.1 - - tispl.bin, u-boot.img from 3.2 + + - GP + + * tiboot3-am62x-gp-evm.bin from step 3.1 + * tispl.bin_unsigned, u-boot.img_unsigned from step 3.2 + + - HS-FS + + * tiboot3-am62x-hs-fs-evm.bin from step 3.1 + * tispl.bin, u-boot.img from step 3.2 + + - HS-SE + + * tiboot3-am62x-hs-evm.bin from step 3.1 + * tispl.bin, u-boot.img from step 3.2 Image formats: -------------- @@ -214,10 +225,10 @@ Image formats: | FIT HEADER | | +-------------------+ | | | | | - | | A53 ATF | | + | | A53 TF-A | | | +-------------------+ | | | | | - | | A53 OPTEE | | + | | A53 OP-TEE | | | +-------------------+ | | | | | | | R5 DM FW | | diff --git a/doc/board/ti/am65x_evm.rst b/doc/board/ti/am65x_evm.rst new file mode 100644 index 0000000000..300cd3e9b9 --- /dev/null +++ b/doc/board/ti/am65x_evm.rst @@ -0,0 +1,420 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Neha Francis + +AM65x Platforms +=============== + +Introduction: +------------- +The AM65x family of SoCs is the first device family from K3 Multicore +SoC architecture, targeted for broad market and industrial control with +aim to meet the complex processing needs of modern embedded products. + +The device is built over three domains, each containing specific processing +cores, voltage domains and peripherals: + +1. Wake-up (WKUP) domain: + * Device Management and Security Controller (DMSC) + +2. Microcontroller (MCU) domain: + * Dual Core ARM Cortex-R5F processor + +3. MAIN domain: + * Quad core 64-bit ARM Cortex-A53 + +More info can be found in TRM: http://www.ti.com/lit/pdf/spruid7 + +Boot Flow: +---------- +On AM65x family devices, ROM supports boot only via MCU(R5). This means that +bootloader has to run on R5 core. In order to meet this constraint, and for +the following reasons the boot flow is designed as mentioned: + +1. Need to move away from R5 asap, so that we want to start *any* +firmware on the R5 cores for example autosar can be loaded to receive CAN +response and other safety operations to be started. This operation is +very time critical and is applicable for all automotive use cases. + +2. U-Boot on A53 should start other remotecores for various +applications. This should happen before running Linux. + +3. In production boot flow, we might not like to use full U-Boot, +instead use Falcon boot flow to reduce boot time. + +.. code-block:: text + + +------------------------------------------------------------------------+ + | DMSC | R5 | A53 | + +------------------------------------------------------------------------+ + | +--------+ | | | + | | Reset | | | | + | +--------+ | | | + | : | | | + | +--------+ | +-----------+ | | + | | *ROM* |----------|-->| Reset rls | | | + | +--------+ | +-----------+ | | + | | | | : | | + | | ROM | | : | | + | |services| | : | | + | | | | +-------------+ | | + | | | | | *R5 ROM* | | | + | | | | +-------------+ | | + | | |<---------|---|Load and auth| | | + | | | | | tiboot3.bin | | | + | | | | +-------------+ | | + | | | | : | | + | | | | : | | + | | | | : | | + | | | | +-------------+ | | + | | | | | *R5 SPL* | | | + | | | | +-------------+ | | + | | | | | Load | | | + | | | | | sysfw.itb | | | + | | Start | | +-------------+ | | + | | System |<---------|---| Start | | | + | |Firmware| | | SYSFW | | | + | +--------+ | +-------------+ | | + | : | | | | | + | +---------+ | | Load | | | + | | *SYSFW* | | | system | | | + | +---------+ | | Config data | | | + | | |<--------|---| | | | + | | | | +-------------+ | | + | | | | | | | | + | | | | | DDR | | | + | | | | | config | | | + | | | | +-------------+ | | + | | | | | | | | + | | |<--------|---| Start A53 | | | + | | | | | and Reset | | | + | | | | +-------------+ | | + | | | | | +-----------+ | + | | |---------|-----------------------|---->| Reset rls | | + | | | | | +-----------+ | + | | DMSC | | | : | + | |Services | | | +------------+ | + | | |<--------|-----------------------|---->|*ATF/OP-TEE*| | + | | | | | +------------+ | + | | | | | : | + | | | | | +-----------+ | + | | |<--------|-----------------------|---->| *A53 SPL* | | + | | | | | +-----------+ | + | | | | | | Load | | + | | | | | | u-boot.img| | + | | | | | +-----------+ | + | | | | | : | + | | | | | +-----------+ | + | | |<--------|-----------------------|---->| *U-Boot* | | + | | | | | +-----------+ | + | | | | | | prompt | | + | | | | | +-----------+ | + | +---------+ | | | + | | | | + +------------------------------------------------------------------------+ + +- Here DMSC acts as master and provides all the critical services. R5/A53 + requests DMSC to get these services done as shown in the above diagram. + +Sources: +-------- +1. Trusted Firmware-A: + Tree: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/ + Branch: master + +2. OP-TEE: + Tree: https://github.com/OP-TEE/optee_os.git + Branch: master + +3. U-Boot: + Tree: https://source.denx.de/u-boot/u-boot + Branch: master + +4. TI Linux Firmware: + Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git + Branch: ti-linux-firmware + +Build procedure: +---------------- +1. Trusted Firmware-A: + +.. code-block:: bash + + $ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 \ + TARGET_BOARD=generic SPD=opteed + +2. OP-TEE: + +.. code-block:: bash + + $ make PLATFORM=k3-am65x CFG_ARM64_core=y + +3. U-Boot: + +* 4.1 R5: + +.. code-block:: bash + + $ make am65x_evm_r5_defconfig + $ make CROSS_COMPILE=arm-linux-gnueabihf- \ + BINMAN_INDIRS= + +* 4.2 A53: + +.. code-block:: bash + + $ make am65x_evm_a53_defconfig + $ make CROSS_COMPILE=aarch64-linux-gnu- \ + BL31=/build/k3/generic/release/bl31.bin \ + TEE=/out/arm-plat-k3/core/tee-raw.bin \ + BINMAN_INDIRS= + +Target Images +-------------- +Copy the below images to an SD card and boot: + +- GP + + * tiboot3-am65x_sr2-gp-evm.bin, sysfw-am65x_sr2-gp-evm.itb from step 4.1 + * tispl.bin_unsigned, u-boot.img_unsigned from step 4.2 + +- HS + + * tiboot3-am65x_sr2-hs-evm.bin, sysfw-am65x_sr2-hs-evm.itb from step 4.1 + * tispl.bin, u-boot.img from step 4.2 + +Image formats: +-------------- + +- tiboot3.bin: + +.. code-block:: text + + +-----------------------+ + | X.509 | + | Certificate | + | +-------------------+ | + | | | | + | | R5 | | + | | u-boot-spl.bin | | + | | | | + | +-------------------+ | + | | | | + | | FIT header | | + | | +---------------+ | | + | | | | | | + | | | DTB 1...N | | | + | | +---------------+ | | + | +-------------------+ | + +-----------------------+ + +- tispl.bin + +.. code-block:: text + + +-----------------------+ + | | + | FIT HEADER | + | +-------------------+ | + | | | | + | | A53 ATF | | + | +-------------------+ | + | | | | + | | A53 OP-TEE | | + | +-------------------+ | + | | | | + | | A53 SPL | | + | +-------------------+ | + | | | | + | | SPL DTB 1...N | | + | +-------------------+ | + +-----------------------+ + +- sysfw.itb + +.. code-block:: text + + +-----------------------+ + | | + | FIT HEADER | + | +-------------------+ | + | | | | + | | sysfw.bin | | + | +-------------------+ | + | | | | + | | board config | | + | +-------------------+ | + | | | | + | | PM config | | + | +-------------------+ | + | | | | + | | RM config | | + | +-------------------+ | + | | | | + | | Secure config | | + | +-------------------+ | + +-----------------------+ + +eMMC: +----- +ROM supports booting from eMMC from boot0 partition offset 0x0 + +Flashing images to eMMC: + +The following commands can be used to download tiboot3.bin, tispl.bin, +u-boot.img, and sysfw.itb from an SD card and write them to the eMMC boot0 +partition at respective addresses. + +.. code-block:: text + + => mmc dev 0 1 + => fatload mmc 1 ${loadaddr} tiboot3.bin + => mmc write ${loadaddr} 0x0 0x400 + => fatload mmc 1 ${loadaddr} tispl.bin + => mmc write ${loadaddr} 0x400 0x1000 + => fatload mmc 1 ${loadaddr} u-boot.img + => mmc write ${loadaddr} 0x1400 0x2000 + => fatload mmc 1 ${loadaddr} sysfw.itb + => mmc write ${loadaddr} 0x3600 0x800 + +To give the ROM access to the boot partition, the following commands must be +used for the first time: + +.. code-block:: text + + => mmc partconf 0 1 1 1 + => mmc bootbus 0 1 0 0 + +To create a software partition for the rootfs, the following command can be +used: + +.. code-block:: text + + => gpt write mmc 0 ${partitions} + +eMMC layout: + +.. code-block:: text + + boot0 partition (8 MB) user partition + 0x0+----------------------------------+ 0x0+-------------------------+ + | tiboot3.bin (512 KB) | | | + 0x400+----------------------------------+ | | + | tispl.bin (2 MB) | | | + 0x1400+----------------------------------+ | rootfs | + | u-boot.img (4 MB) | | | + 0x3400+----------------------------------+ | | + | environment (128 KB) | | | + 0x3500+----------------------------------+ | | + | backup environment (128 KB) | | | + 0x3600+----------------------------------+ | | + | sysfw (1 MB) | | | + 0x3E00+----------------------------------+ +-------------------------+ + +Kernel image and DT are expected to be present in the /boot folder of rootfs. +To boot kernel from eMMC, use the following commands: + +.. code-block:: text + + => setenv mmcdev 0 + => setenv bootpart 0 + => boot + +OSPI: +----- +ROM supports booting from OSPI from offset 0x0. + +Flashing images to OSPI: + +Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img, +and sysfw.itb over tftp and then flash those to OSPI at their respective +addresses. + +.. code-block:: text + + => sf probe + => tftp ${loadaddr} tiboot3.bin + => sf update $loadaddr 0x0 $filesize + => tftp ${loadaddr} tispl.bin + => sf update $loadaddr 0x80000 $filesize + => tftp ${loadaddr} u-boot.img + => sf update $loadaddr 0x280000 $filesize + => tftp ${loadaddr} sysfw.itb + => sf update $loadaddr 0x6C0000 $filesize + +Flash layout for OSPI: + +.. code-block:: text + + 0x0 +----------------------------+ + | ospi.tiboot3(512K) | + | | + 0x80000 +----------------------------+ + | ospi.tispl(2M) | + | | + 0x280000 +----------------------------+ + | ospi.u-boot(4M) | + | | + 0x680000 +----------------------------+ + | ospi.env(128K) | + | | + 0x6A0000 +----------------------------+ + | ospi.env.backup (128K) | + | | + 0x6C0000 +----------------------------+ + | ospi.sysfw(1M) | + | | + 0x7C0000 +----------------------------+ + | padding (256k) | + 0x800000 +----------------------------+ + | ospi.rootfs(UBIFS) | + | | + +----------------------------+ + +Kernel Image and DT are expected to be present in the /boot folder of UBIFS +ospi.rootfs just like in SD card case. U-Boot looks for UBI volume named +"rootfs" for rootfs. + +To boot kernel from OSPI, at the U-Boot prompt: + +.. code-block:: text + + => setenv boot ubi + => boot + +UART: +----- +ROM supports booting from MCU_UART0 via X-Modem protocol. The entire UART-based +boot process up to U-Boot (proper) prompt goes through different stages and uses +different UART peripherals as follows: + +.. code-block:: text + + +---------+---------------+-------------+------------+ + | WHO | Loading WHAT | HW Module | Protocol | + +---------+---------------+-------------+------------+ + |Boot ROM | tiboot3.bin | MCU_UART0 | X-Modem(*)| + |R5 SPL | sysfw.itb | MCU_UART0 | Y-Modem(*)| + |R5 SPL | tispl.bin | MAIN_UART0 | Y-Modem | + |A53 SPL | u-boot.img | MAIN_UART0 | Y-Modem | + +---------+---------------+-------------+------------+ + +Note that in addition to X/Y-Modem related protocol timeouts the DMSC +watchdog timeout of 3min (typ.) needs to be observed until System Firmware +is fully loaded (from sysfw.itb) and started. + +Example bash script sequence for running on a Linux host PC feeding all boot +artifacts needed to the device: + +.. code-block:: text + + MCU_DEV=/dev/ttyUSB1 + MAIN_DEV=/dev/ttyUSB0 + + stty -F $MCU_DEV 115200 cs8 -cstopb -parenb + stty -F $MAIN_DEV 115200 cs8 -cstopb -parenb + + sb --xmodem tiboot3.bin > $MCU_DEV < $MCU_DEV + sb --ymodem sysfw.itb > $MCU_DEV < $MCU_DEV + sb --ymodem tispl.bin > $MAIN_DEV < $MAIN_DEV + sleep 1 + sb --xmodem u-boot.img > $MAIN_DEV < $MAIN_DEV diff --git a/doc/board/ti/j7200_evm.rst b/doc/board/ti/j7200_evm.rst index 0d3a526516..5e3d75059c 100644 --- a/doc/board/ti/j7200_evm.rst +++ b/doc/board/ti/j7200_evm.rst @@ -83,9 +83,9 @@ Below is the pictorial representation of boot flow: | | |---------|-----------------------|---->| Reset rls | | | | | | | | +-----------+ | | | | TIFS | | | : | | - | |Services | | | +-----------+ | | - | | |<--------|-----------------------|---->|*ATF/OPTEE*| | | - | | | | | +-----------+ | | + | |Services | | | +-------------+ | | + | | |<--------|-----------------------|---->|*TF-A/OP-TEE*| | | + | | | | | +-------------+ | | | | | | | : | | | | | | | +-----------+ | | | | |<--------|-----------------------|---->| *A72 SPL* | | | @@ -120,68 +120,74 @@ Below is the pictorial representation of boot flow: Sources: -------- -1. SYSFW: - Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git +1. Trusted Firmware-A: + Tree: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/ Branch: master -2. ATF: - Tree: https://github.com/ARM-software/arm-trusted-firmware.git +2. OP-TEE: + Tree: https://github.com/OP-TEE/optee_os.git Branch: master -3. OPTEE: - Tree: https://github.com/OP-TEE/optee_os.git +3. U-Boot: + Tree: https://source.denx.de/u-boot/u-boot Branch: master -4. DM Firmware: +4. TI Linux Firmware: Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git Branch: ti-linux-firmware -5. U-Boot: - Tree: https://source.denx.de/u-boot/u-boot - Branch: master - Build procedure: ---------------- -1. SYSFW: +1. Trusted Firmware-A: .. code-block:: bash - make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- SOC=j7200 SBL=u-boot-spl.bin SYSFW_PATH=/ti-fs-firmware-j7200-gp.bin - u-boot-spl.bin is generated at step 4. + $ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed -2. ATF: +2. OP-TEE: .. code-block:: bash - make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed + $ make PLATFORM=k3-j7200 CFG_ARM64_core=y -3. OPTEE: - -.. code-block:: bash - - make PLATFORM=k3-j7200 CFG_ARM64_core=y - -4. U-Boot: +3. U-Boot: * 4.1 R5: .. code-block:: bash - make CROSS_COMPILE=arm-linux-gnueabihf- j7200_evm_r5_defconfig O=build/r5 - make CROSS_COMPILE=arm-linux-gnueabihf- O=build/r5 + $ make CROSS_COMPILE=arm-linux-gnueabihf- j7200_evm_r5_defconfig O=build/r5 + $ make CROSS_COMPILE=arm-linux-gnueabihf- \ + BINMAN_INDIRS= * 4.2 A72: .. code-block:: bash - make CROSS_COMPILE=aarch64-linux-gnu- j7200_evm_a72_defconfig O=build/a72 - make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin DM=/ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f O=build/a72 + $ make CROSS_COMPILE=aarch64-linux-gnu- j7200_evm_a72_defconfig O=build/a72 + $ make CROSS_COMPILE=aarch64-linux-gnu- \ + BL31=/build/k3/generic/release/bl31.bin \ + TEE=/out/arm-plat-k3/core/tee-raw.bin \ + BINMAN_INDIRS= Target Images -------------- Copy the below images to an SD card and boot: - - tiboot3.bin from step 1 - - tispl.bin, u-boot.img from 4.2 + + - GP + + * tiboot3-j7200-gp-evm.bin from step 4.1 + * tispl.bin_unsigned, u-boot.img_unsigned from step 4.2 + + - HS-FS + + * tiboot3-j7200_sr2-hs-fs-evm.bin from step 4.1 + * tispl.bin, u-boot.img from step 4.2 + + - HS-SE + + * tiboot3-j7200_sr2-hs-evm.bin from step 4.1 + * tispl.bin, u-boot.img from step 4.2 Image formats: -------------- @@ -236,10 +242,10 @@ Image formats: | FIT HEADER | | +-------------------+ | | | | | - | | A72 ATF | | + | | A72 TF-A | | | +-------------------+ | | | | | - | | A72 OPTEE | | + | | A72 OP-TEE | | | +-------------------+ | | | | | | | R5 DM FW | | diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst index feaa2da5e9..46244197f3 100644 --- a/doc/board/ti/j721e_evm.rst +++ b/doc/board/ti/j721e_evm.rst @@ -90,9 +90,9 @@ support. Below is the pictorial representation of boot flow: | | |---------|-----------------------|---->| Reset rls | | | | | | | | +-----------+ | | | | TIFS | | | : | | - | |Services | | | +-----------+ | | - | | |<--------|-----------------------|---->|*ATF/OPTEE*| | | - | | | | | +-----------+ | | + | |Services | | | +-------------+ | | + | | |<--------|-----------------------|---->|*TF-A/OP-TEE*| | | + | | | | | +-------------+ | | | | | | | : | | | | | | | +-----------+ | | | | |<--------|-----------------------|---->| *A72 SPL* | | | @@ -130,68 +130,75 @@ support. Below is the pictorial representation of boot flow: Sources: -------- -1. SYSFW: - Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git +1. Trusted Firmware-A: + Tree: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/ Branch: master -2. ATF: - Tree: https://github.com/ARM-software/arm-trusted-firmware.git +2. OP-TEE: + Tree: https://github.com/OP-TEE/optee_os.git Branch: master -3. OPTEE: - Tree: https://github.com/OP-TEE/optee_os.git +3. U-Boot: + Tree: https://source.denx.de/u-boot/u-boot Branch: master -4. DM Firmware: +4. TI Linux Firmware: Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git Branch: ti-linux-firmware -5. U-Boot: - Tree: https://source.denx.de/u-boot/u-boot - Branch: master - Build procedure: ---------------- -1. SYSFW: +1. Trusted Firmware-A: .. code-block:: bash - make CROSS_COMPILE=arm-linux-gnueabihf- SOC=j721e + $ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 \ + TARGET_BOARD=generic SPD=opteed -2. ATF: +2. OP-TEE: .. code-block:: bash - make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed + $ make PLATFORM=k3-j721e CFG_ARM64_core=y -3. OPTEE: - -.. code-block:: bash - - make PLATFORM=k3-j721e CFG_ARM64_core=y - -4. U-Boot: +3. U-Boot: * 4.1 R5: .. code-block:: bash - make CROSS_COMPILE=arm-linux-gnueabihf- j721e_evm_r5_defconfig O=build/r5 - make CROSS_COMPILE=arm-linux-gnueabihf- O=build/r5 + $ make j721e_evm_r5_defconfig + $ make CROSS_COMPILE=arm-linux-gnueabihf- \ + BINMAN_INDIRS= * 4.2 A72: .. code-block:: bash - make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=build/a72 - make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin DM=/ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f O=build/a72 + $ make j721e_evm_a72_defconfig + $ make CROSS_COMPILE=aarch64-linux-gnu- \ + BL31=/build/k3/generic/release/bl31.bin \ + TEE=/out/arm-plat-k3/core/tee-raw.bin \ + BINMAN_INDIRS= Target Images -------------- Copy the below images to an SD card and boot: - - sysfw.itb from step 1 - - tiboot3.bin from step 4.1 - - tispl.bin, u-boot.img from 4.2 + + - GP + + * tiboot3-j721e-gp-evm.bin, sysfw-j721e-gp-evm.itb from step 4.1 + * tispl.bin_unsigned, u-boot.img_unsigned from step 4.2 + + - HS-FS + + * tiboot3-j721e_sr2-hs-fs-evm.bin, sysfw-j721e_sr2-hs-fs-evm.itb from step 4.1 + * tispl.bin, u-boot.img from step 4.2 + + - HS-SE + + * tiboot3-j721e_sr2-hs-evm.bin, sysfw-j721e_sr2-hs-evm.itb from step 4.1 + * tispl.bin, u-boot.img from step 4.2 Image formats: -------------- @@ -227,10 +234,10 @@ Image formats: | FIT HEADER | | +-------------------+ | | | | | - | | A72 ATF | | + | | A72 TF-A | | | +-------------------+ | | | | | - | | A72 OPTEE | | + | | A72 OP-TEE | | | +-------------------+ | | | | | | | R5 DM FW | | diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index 2b2f4bb8bb..7390e0305e 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -33,6 +33,7 @@ K3 Based SoCs j721e_evm j7200_evm am62x_sk + am65x_evm Boot Flow Overview ------------------ @@ -53,13 +54,13 @@ The wakeup SPL, running on a wakeup domain core, will initialize DDR and any peripherals needed load the larger binaries inside the `tispl.bin` into DDR. Once loaded the wakeup SPL will start one of the 'big' application cores inside the main domain to initialize the main domain, -starting with ARM Trusted Firmware (ATF), before moving on to start -OPTEE and the main domain's U-Boot SPL. +starting with Trusted Firmware-A (TF-A), before moving on to start +OP-TEE and the main domain's U-Boot SPL. .. code-block:: text | WKUP Domain | Main Domain -> - ROM -> WKUP SPL -> ATF -> OPTEE -> Main SPL + ROM -> WKUP SPL -> TF-A -> OP-TEE -> Main SPL The main domain's SPL, running on a 64bit application core, has virtually unlimited space (billions of bytes now that DDR is working) to @@ -70,7 +71,7 @@ finally prepare the main domain to run Linux. .. code-block:: text | WKUP Domain | Main Domain -> - ROM -> WKUP SPL -> ATF -> OPTEE -> Main SPL -> UBoot -> Linux + ROM -> WKUP SPL -> TF-A -> OP-TEE -> Main SPL -> UBoot -> Linux This is the typical boot flow for all K3 based SoCs, however this flow offers quite a lot in the terms of flexibility, especially on High @@ -115,17 +116,12 @@ online | **source:** https://source.denx.de/u-boot/u-boot.git | **branch:** master -* **K3 Image Gen** +* **Trusted Firmware-A (TF-A)** - | **source:** https://git.ti.com/git/k3-image-gen/k3-image-gen.git + | **source:** https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/ | **branch:** master -* **ARM Trusted Firmware (ATF)** - - | **source:** https://github.com/ARM-software/arm-trusted-firmware.git - | **branch:** master - -* **Open Portable Trusted Execution Environment (OPTEE)** +* **Open Portable Trusted Execution Environment (OP-TEE)** | **source:** https://github.com/OP-TEE/optee_os.git | **branch:** master @@ -135,11 +131,6 @@ online | **source:** https://git.ti.com/git/processor-firmware/ti-linux-firmware.git | **branch:** ti-linux-firmware -* **TI's Security Development Tools** - - | **source:** https://git.ti.com/git/security-development-tools/core-secdev-k3.git - | **branch:** master - Build Procedure --------------- @@ -161,54 +152,37 @@ All of that to say you will need both a 32bit and 64bit cross compiler .. code-block:: bash - export CC32=arm-linux-gnueabihf- - export CC64=aarch64-linux-gnu- + $ export CC32=arm-linux-gnueabihf- + $ export CC64=aarch64-linux-gnu- Building tiboot3.bin ^^^^^^^^^^^^^^^^^^^^^ 1. To generate the U-Boot SPL for the wakeup domain, use the following commands, substituting :code:`{SOC}` for the name of your device (eg: - am62x) - -.. code-block:: bash - - # inside u-boot source - make ARCH=arm O=build/wkup CROSS_COMPILE=$CC32 {SOC}_evm_r5_defconfig - make ARCH=arm O=build/wkup CROSS_COMPILE=$CC32 + am62x) to package the various firmware and the wakeup UBoot SPL into + the final `tiboot3.bin` binary. (or the `sysfw.itb` if your device + uses the split binary flow) -2. Next we will use the K3 Image Gen scripts to package the various - firmware and the wakeup UBoot SPL into the final `tiboot3.bin` - binary. (or the `sysfw.itb` if your device uses the split binary - flow) .. code-block:: bash - # inside k3-image-gen source - make CROSS_COMPILE=$CC32 SOC={SOC} SOC_TYPE={hs,gp} \ - TI_SECURE_DEV_PKG= \ - SYSFW_PATH= \ - SYSFW_HS_INNER_CERT_PATH= + $ # inside u-boot source + $ make ARCH=arm {SOC}_evm_r5_defconfig + $ make ARCH=arm CROSS_COMPILE=$CC32 \ + BINMAN_INDIRS= At this point you should have all the needed binaries to boot the wakeup domain of your K3 SoC. **Combined Binary Boot Flow** (eg: am62x, am64x, ... ) - `k3-image-gen/tiboot3-{SOC}-{hs,gp}-evm.bin` + `tiboot3-{SOC}-{gp/hs-fs/hs}.bin` **Split Binary Boot Flow** (eg: j721e, am65x) - | `u-boot/build/wkup/tiboot3.bin` - | `k3-image-gen/sysfw-{SOC}-evm.bin` + | `tiboot3-{SOC}-{gp/hs-fs/hs}.bin` + | `sysfw-{SOC}-{gp/hs-fs/hs}-evm.itb` .. note :: @@ -223,53 +197,47 @@ The `tispl.bin` is a standard fitImage combining the firmware need for the main domain to function properly as well as Device Management (DM) firmware if your device using a split firmware. -3. We will first need ATF, as it's the first thing to run on the 'big' +2. We will first need TF-A, as it's the first thing to run on the 'big' application cores on the main domain. .. code-block:: bash - # inside arm-trusted-firmware source - make CROSS_COMPILE=$CC64 ARCH=aarch64 PLAT=k3 \ - TARGET_BOARD={lite|generic} \ - SPD=opteed \ + $ # inside trusted-firmware-a source + $ make CROSS_COMPILE=$CC64 ARCH=aarch64 PLAT=k3 \ + TARGET_BOARD={lite|generic|j784s4} \ + SPD=opteed -Typically all `j7*` devices will use `TARGET_BOARD=generic` while all -Sitara (`am6*`) devices use the `lite` option. +Typically all `j7*` devices will use `TARGET_BOARD=generic` or `TARGET_BOARD +=j784s4` (if it is a J784S4 device), while all Sitara (`am6*`) devices +use the `lite` option. -4. The Open Portable Trusted Execution Environment (OPTEE) is designed +3. The Open Portable Trusted Execution Environment (OP-TEE) is designed to run as a companion to a non-secure Linux kernel for Cortex-A cores using the TrustZone technology built into the core. .. code-block:: bash - # inside optee_os source - make CROSS_COMPILE=$CC32 CROSS_COMPILE64=$CC64 \ + $ # inside optee_os source + $ make CROSS_COMPILE=$CC32 CROSS_COMPILE64=$CC64 \ PLATFORM=k3 CFG_ARM64_core=y -5. Finally, after ATF has initialized the main domain and OPTEE has +4. Finally, after TF-A has initialized the main domain and OP-TEE has finished, we can jump back into U-Boot again, this time running on a 64bit core in the main domain. .. code-block:: bash - # inside u-boot source - make ARCH=arm O=build/main CROSS_COMPILE=$CC64 {SOC}_evm_a{53,72}_defconfig - make ARCH=arm O=build/main CROSS_COMPILE=$CC64 \ - ATF= + $ # inside u-boot source + $ make ARCH=arm {SOC}_evm_a{53,72}_defconfig + $ make ARCH=arm CROSS_COMPILE=$CC64 \ + BINMAN_INDIRS= \ + BL31=/build/k3/generic/release/bl31.bin \ + TEE=/out/arm-plat-k3/core/tee-raw.bin At this point you should have every binary needed initialize both the wakeup and main domain and to boot to the U-Boot prompt **Main Domain Bootloader** - | `u-boot/build/main/tispl.bin` - | `u-boot/build/main/u-boot.img` + | `tispl.bin` for HS devices or `tispl.bin_unsigned` for GP devices + | `u-boot.img` for HS devices or `u-boot.img_unsigned` for GP devices From patchwork Fri Jul 21 18:44:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811099 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Fri, 21 Jul 2023 13:47:09 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jul 2023 13:47:10 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloc131068; Fri, 21 Jul 2023 13:47:03 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 21/23] binman: Overwrite symlink if it already exists Date: Sat, 22 Jul 2023 00:14:44 +0530 Message-ID: <20230721184446.5821-22-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Andrew Davis Without this re-building will fail with an error when trying to create the symlink for the second time with an already exists error. Signed-off-by: Andrew Davis [n-francis@ti.com: Added support for test output dir and testcase] Signed-off-by: Neha Malcom Francis Reviewed-by: Simon Glass --- tools/binman/ftest.py | 18 ++++++++++++++++-- tools/binman/image.py | 2 ++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index f4bff50aaf..6280eb92c4 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -353,7 +353,7 @@ class TestFunctional(unittest.TestCase): use_expanded=False, verbosity=None, allow_missing=False, allow_fake_blobs=False, extra_indirs=None, threads=None, test_section_timeout=False, update_fdt_in_elf=None, - force_missing_bintools='', ignore_missing=False): + force_missing_bintools='', ignore_missing=False, output_dir=None): """Run binman with a given test file Args: @@ -384,6 +384,7 @@ class TestFunctional(unittest.TestCase): update_fdt_in_elf: Value to pass with --update-fdt-in-elf=xxx force_missing_tools (str): comma-separated list of bintools to regard as missing + output_dir: Specific output directory to use for image using -O Returns: int return code, 0 on success @@ -430,6 +431,8 @@ class TestFunctional(unittest.TestCase): if extra_indirs: for indir in extra_indirs: args += ['-I', indir] + if output_dir: + args += ['-O', output_dir] return self._DoBinman(*args) def _SetupDtb(self, fname, outfile='u-boot.dtb'): @@ -6113,7 +6116,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap str(e.exception)) def testSymlink(self): - """Test that image files can be named""" + """Test that image files can be symlinked""" retcode = self._DoTestFile('259_symlink.dts', debug=True, map=True) self.assertEqual(0, retcode) image = control.images['test_image'] @@ -6122,6 +6125,17 @@ fdt fdtmap Extract the devicetree blob from the fdtmap self.assertTrue(os.path.islink(sname)) self.assertEqual(os.readlink(sname), fname) + def testSymlinkOverwrite(self): + """Test that symlinked images can be overwritten""" + testdir = TestFunctional._MakeInputDir('symlinktest') + self._DoTestFile('259_symlink.dts', debug=True, map=True, output_dir=testdir) + # build the same image again in the same directory so that existing symlink is present + self._DoTestFile('259_symlink.dts', debug=True, map=True, output_dir=testdir) + fname = tools.get_output_filename('test_image.bin') + sname = tools.get_output_filename('symlink_to_test.bin') + self.assertTrue(os.path.islink(sname)) + self.assertEqual(os.readlink(sname), fname) + def testSymbolsElf(self): """Test binman can assign symbols embedded in an ELF file""" if not elf.ELF_TOOLS: diff --git a/tools/binman/image.py b/tools/binman/image.py index 8ebf71d61a..e77b5d0d97 100644 --- a/tools/binman/image.py +++ b/tools/binman/image.py @@ -182,6 +182,8 @@ class Image(section.Entry_section): # Create symlink to file if symlink given if self._symlink is not None: sname = tools.get_output_filename(self._symlink) + if os.path.islink(sname): + os.remove(sname) os.symlink(fname, sname) def WriteMap(self): From patchwork Fri Jul 21 18:44:45 2023 Content-Type: text/plain; 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Fri, 21 Jul 2023 13:47:15 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jul 2023 13:47:16 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIilod131068; Fri, 21 Jul 2023 13:47:10 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 22/23] buildman: Create a requirements.txt file Date: Sat, 22 Jul 2023 00:14:45 +0530 Message-ID: <20230721184446.5821-23-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tom Rini At this point, buildman requires a few different modules and so we need a requirements.txt to track what modules are needed. Cc: Simon Glass Cc: Neha Malcom Francis Signed-off-by: Tom Rini Reviewed-by: Simon Glass Signed-off-by: Neha Malcom Francis --- tools/buildman/requirements.txt | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 tools/buildman/requirements.txt diff --git a/tools/buildman/requirements.txt b/tools/buildman/requirements.txt new file mode 100644 index 0000000000..a1efcb9d4b --- /dev/null +++ b/tools/buildman/requirements.txt @@ -0,0 +1,2 @@ +jsonschema==4.17.3 +pyyaml==6.0 From patchwork Fri Jul 21 18:44:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1811100 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; 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Fri, 21 Jul 2023 13:47:22 -0500 Received: from ula0497641.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36LIiloe131068; Fri, 21 Jul 2023 13:47:16 -0500 From: Neha Malcom Francis To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v8 23/23] CI: Make use of buildman requirements.txt Date: Sat, 22 Jul 2023 00:14:46 +0530 Message-ID: <20230721184446.5821-24-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721184446.5821-1-n-francis@ti.com> References: <20230721184446.5821-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tom Rini Now that buildman has a requirements.txt file we need to make use of it. Signed-off-by: Tom Rini Reviewed-by: Simon Glass [n-francis@ti.com: Adding missing command from .azure-pipelines.yml] Signed-off-by: Neha Malcom Francis --- .azure-pipelines.yml | 4 ++++ .gitlab-ci.yml | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 06c46b681c..8626b27d4b 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -162,6 +162,7 @@ stages: virtualenv -p /usr/bin/python3 /tmp/venv . /tmp/venv/bin/activate pip install -r test/py/requirements.txt + pip install -r tools/buildman/requirements.txt export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH} @@ -209,6 +210,7 @@ stages: git config --global --add safe.directory $(work_dir) export USER=azure pip install -r test/py/requirements.txt + pip install -r tools/buildman/requirements.txt pip install asteval pylint==2.12.2 pyopenssl export PATH=${PATH}:~/.local/bin echo "[MASTER]" >> .pylintrc @@ -404,6 +406,7 @@ stages: if [ -n "${BUILD_ENV}" ]; then export ${BUILD_ENV}; fi + pip install -r tools/buildman/requirements.txt tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board ${TEST_PY_BD} ${OVERRIDE} cp ~/grub_x86.efi ${UBOOT_TRAVIS_BUILD_DIR}/ cp ~/grub_x64.efi ${UBOOT_TRAVIS_BUILD_DIR}/ @@ -583,6 +586,7 @@ stages: # make environment variables available as tests are running inside a container export BUILDMAN="${BUILDMAN}" git config --global --add safe.directory ${WORK_DIR} + pip install -r tools/buildman/requirements.txt EOF cat << "EOF" >> build.sh if [[ "${BUILDMAN}" != "" ]]; then diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index cfd58513c3..07d8ba5ac2 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -97,6 +97,7 @@ build all 32bit ARM platforms: script: - ret=0; git config --global --add safe.directory "${CI_PROJECT_DIR}"; + pip install -r tools/buildman/requirements.txt; ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 || ret=$?; if [[ $ret -ne 0 ]]; then ./tools/buildman/buildman -o /tmp -seP; @@ -110,6 +111,7 @@ build all 64bit ARM platforms: - . /tmp/venv/bin/activate - ret=0; git config --global --add safe.directory "${CI_PROJECT_DIR}"; + pip install -r tools/buildman/requirements.txt; ./tools/buildman/buildman -o /tmp -PEWM aarch64 || ret=$?; if [[ $ret -ne 0 ]]; then ./tools/buildman/buildman -o /tmp -seP; @@ -208,6 +210,7 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites: virtualenv -p /usr/bin/python3 /tmp/venv; . /tmp/venv/bin/activate; pip install -r test/py/requirements.txt; + pip install -r tools/buildman/requirements.txt; export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl; export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"; export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}"; @@ -240,6 +243,7 @@ Run pylint: script: - git config --global --add safe.directory "${CI_PROJECT_DIR}" - pip install -r test/py/requirements.txt + - pip install -r tools/buildman/requirements.txt - pip install asteval pylint==2.12.2 pyopenssl - export PATH=${PATH}:~/.local/bin - echo "[MASTER]" >> .pylintrc