From patchwork Wed Mar 28 12:51:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 892169 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="J00+/puO"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40B79V3TR5z9s2t for ; Wed, 28 Mar 2018 23:53:50 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=I3/OhUlSYPnTNBFrc7UjfGxdwWSzlG5U4x70G0KI6Pk=; b=J00+/puOT9KFk+ Tod/eNcwlQR90u6/91J9+1N5ey+78arZnKeMFxxL6XGQlkjukUwz99OjmjOCRh8hS8xaAKnfnm60o asI6xAqVBf3FO855EM+ak7gcU1gWjWgTAGP3te0NMqpFZV1YgtczkGx9nIh6KHEPpmGmZ9tdbgP04 4s2ania/l/31Mzsjiq1JWkTUwMTS+gvIKrLnw3vATVZX7UsOHtP9R9h96FzFEjlFpmWZ7xmIdFvdf CeZJ7bjotPllJJw4ADB7Oc5e/9kAqWHgC3u4XjOIMRQVrcsGoYTIoTeNe0GVEUQP6xeWsGW/qkxFm PFSg1QnQCkl7TTy48APA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1f1AaI-0003IC-FN; Wed, 28 Mar 2018 12:53:46 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1f1AZp-0002xr-Dq for linux-arm-kernel@lists.infradead.org; Wed, 28 Mar 2018 12:53:19 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 01DC11596; Wed, 28 Mar 2018 05:53:05 -0700 (PDT) Received: from approximate.cambridge.arm.com (approximate.cambridge.arm.com [10.1.206.75]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 02EA73F25D; Wed, 28 Mar 2018 05:53:00 -0700 (PDT) From: Marc Zyngier To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Subject: [GIT PULL] KVM/ARM updates for v4.17 Date: Wed, 28 Mar 2018 13:51:29 +0100 Message-Id: <20180328125254.31380-1-marc.zyngier@arm.com> X-Mailer: git-send-email 2.14.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180328_055317_479452_E2C6469B X-CRM114-Status: GOOD ( 20.05 ) X-Spam-Score: -5.0 (-----) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-5.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [217.140.101.70 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Christoffer Dall , Andrew Jones , Christoffer Dall , Shunyong Yang , Julien Thierry , Peter Maydell , Andre Przywara , Suzuki K Poulose , Will Deacon , Alvise Rigo , Eric Auger , Julien Grall , James Morse , Shih-Wei Li , Catalin Marinas , =?utf-8?b?SsOpcsOpbXkgRmFu?= =?utf-8?b?Z3XDqGRl?= , Dave Martin , Shanker Donthineni Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Paolo, Radim, This is the (rather big) set of updates for KVM/ARM for v4.17. The main features are the set of VHE optimizations taking advantage of CPUs implementing ARMv8.1, together with the EL2 randomization patches that are the foundation for mitigating the so-called variant 3a security issue (affecting Cortex-A57 and A72). The rest is the usual mix of vgic fixes and minor improvements. Note that the breakup below is slightly misleading, as it includes fixes that have already landed in mainline (I've done a direct merge of the fixes branch in order to spare everyone some horrible conflicts). Also, we've had to revert a pretty important patch for Qualcomm servers due to some more conflicts with the arm64 tree). That patch will be resent once both trees have been pulled into Linus' (the sooner, the better). Please pull. M. The following changes since commit 4a3928c6f8a53fa1aed28ccba227742486e8ddcb: Linux 4.16-rc3 (2018-02-25 18:50:41 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git tags/kvm-arm-for-v4.17 for you to fetch changes up to dc6ed61d2f824a595033744fc1f3bf4cb98768b5: arm64: Add temporary ERRATA_MIDR_ALL_VERSIONS compatibility macro (2018-03-28 12:57:23 +0100) ---------------------------------------------------------------- KVM/ARM updates for v4.17 - VHE optimizations - EL2 address space randomization - Variant 3a mitigation for Cortex-A57 and A72 - The usual vgic fixes - Various minor tidying-up ---------------------------------------------------------------- Andre Przywara (1): KVM: arm/arm64: vgic: Add missing irq_lock to vgic_mmio_read_pending Ard Biesheuvel (1): KVM: arm/arm64: Reduce verbosity of KVM init log Arnd Bergmann (1): ARM: kvm: fix building with gcc-8 Christoffer Dall (42): KVM: arm/arm64: Fix arch timers with userspace irqchips KVM: arm/arm64: Avoid vcpu_load for other vcpu ioctls than KVM_RUN KVM: arm/arm64: Reset mapped IRQs on VM reset KVM: arm/arm64: Avoid vcpu_load for other vcpu ioctls than KVM_RUN KVM: arm/arm64: Move vcpu_load call after kvm_vcpu_first_run_init KVM: arm64: Avoid storing the vcpu pointer on the stack KVM: arm64: Rework hyp_panic for VHE and non-VHE KVM: arm/arm64: Get rid of vcpu->arch.irq_lines KVM: arm/arm64: Add kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs KVM: arm/arm64: Introduce vcpu_el1_is_32bit KVM: arm64: Move debug dirty flag calculation out of world switch KVM: arm64: Slightly improve debug save/restore functions KVM: arm64: Improve debug register save/restore flow KVM: arm64: Factor out fault info population and gic workarounds KVM: arm64: Introduce VHE-specific kvm_vcpu_run KVM: arm64: Remove kern_hyp_va() use in VHE switch function KVM: arm64: Don't deactivate VM on VHE systems KVM: arm64: Remove noop calls to timer save/restore from VHE switch KVM: arm64: Move userspace system registers into separate function KVM: arm64: Rewrite sysreg alternatives to static keys KVM: arm64: Introduce separate VHE/non-VHE sysreg save/restore functions KVM: arm/arm64: Remove leftover comment from kvm_vcpu_run_vhe KVM: arm64: Unify non-VHE host/guest sysreg save and restore functions KVM: arm64: Don't save the host ELR_EL2 and SPSR_EL2 on VHE systems KVM: arm64: Change 32-bit handling of VM system registers KVM: arm64: Rewrite system register accessors to read/write functions KVM: arm64: Introduce framework for accessing deferred sysregs KVM: arm/arm64: Prepare to handle deferred save/restore of SPSR_EL1 KVM: arm64: Prepare to handle deferred save/restore of ELR_EL1 KVM: arm64: Defer saving/restoring 64-bit sysregs to vcpu load/put on VHE KVM: arm64: Prepare to handle deferred save/restore of 32-bit registers KVM: arm64: Defer saving/restoring 32-bit sysregs to vcpu load/put KVM: arm64: Move common VHE/non-VHE trap config in separate functions KVM: arm64: Directly call VHE and non-VHE FPSIMD enabled functions KVM: arm64: Configure c15, PMU, and debug register traps on cpu load/put for VHE KVM: arm64: Cleanup __activate_traps and __deactive_traps for VHE and non-VHE KVM: arm/arm64: Get rid of vgic_elrsr KVM: arm/arm64: Handle VGICv2 save/restore from the main VGIC code KVM: arm/arm64: Move arm64-only vgic-v2-sr.c file to arm64 KVM: arm/arm64: Handle VGICv3 save/restore from the main VGIC code on VHE KVM: arm/arm64: Move VGIC APR save/restore to vgic put/load KVM: arm/arm64: Avoid VGICv3 save/restore on VHE with no IRQs Dave Martin (1): arm64: KVM: Move CPU ID reg trap setup off the world switch path Jérémy Fanguède (2): KVM: arm64: Enable the EL1 physical timer for AArch32 guests KVM: arm: Enable emulation of the physical timer Marc Zyngier (33): KVM: arm/arm64: vgic: Don't populate multiple LRs with the same vintid kvm: arm/arm64: vgic-v3: Tighten synchronization for guests using v2 on v3 arm64: alternatives: Add dynamic patching feature arm64: insn: Add N immediate encoding arm64: insn: Add encoder for bitwise operations using literals arm64: KVM: Dynamically patch the kernel/hyp VA mask arm64: cpufeatures: Drop the ARM64_HYP_OFFSET_LOW feature flag KVM: arm/arm64: Do not use kern_hyp_va() with kvm_vgic_global_state KVM: arm/arm64: Demote HYP VA range display to being a debug feature KVM: arm/arm64: Move ioremap calls to create_hyp_io_mappings KVM: arm/arm64: Keep GICv2 HYP VAs in kvm_vgic_global_state KVM: arm/arm64: Fix idmap size and alignment KVM: arm64: Fix HYP idmap unmap when using 52bit PA KVM: arm/arm64: Move HYP IO VAs to the "idmap" range arm64; insn: Add encoder for the EXTR instruction arm64: insn: Allow ADD/SUB (immediate) with LSL #12 arm64: KVM: Dynamically compute the HYP VA mask arm64: KVM: Introduce EL2 VA randomisation arm64: Update the KVM memory map documentation arm64: KVM: Move vector offsetting from hyp-init.S to kvm_get_hyp_vector arm64: KVM: Move stashing of x0/x1 into the vector code itself arm64: KVM: Move BP hardening vectors into .hyp.text section arm64: KVM: Reserve 4 additional instructions in the BPI template arm64: KVM: Allow far branches from vector slots to the main vectors arm/arm64: KVM: Introduce EL2-specific executable mappings arm64: Make BP hardening slot counter available arm64: KVM: Allow mapping of vectors outside of the RAM region arm64: Enable ARM64_HARDEN_EL2_VECTORS on Cortex-A57 and A72 Merge tag 'kvm-arm-fixes-for-v4.16-2' into HEAD KVM: arm/arm64: vgic: Disallow Active+Pending for level interrupts KVM: arm/arm64: vgic-its: Fix potential overrun in vgic_copy_lpi_list Revert "arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening" arm64: Add temporary ERRATA_MIDR_ALL_VERSIONS compatibility macro Mark Rutland (1): arm64/kvm: Prohibit guest LOR accesses Peter Maydell (1): KVM: arm: Reserve bit in KVM_REG_ARM encoding for secure/nonsecure Shanker Donthineni (2): KVM: arm/arm64: No need to zero CNTVOFF in kvm_timer_vcpu_put() for VHE arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening Shih-Wei Li (1): KVM: arm64: Move HCR_INT_OVERRIDE to default HCR_EL2 guest flag Documentation/arm64/memory.txt | 9 +- arch/arm/include/asm/kvm_asm.h | 5 +- arch/arm/include/asm/kvm_emulate.h | 21 +- arch/arm/include/asm/kvm_host.h | 6 +- arch/arm/include/asm/kvm_hyp.h | 4 + arch/arm/include/asm/kvm_mmu.h | 16 +- arch/arm/include/uapi/asm/kvm.h | 9 + arch/arm/kvm/coproc.c | 61 +++++ arch/arm/kvm/emulate.c | 4 +- arch/arm/kvm/hyp/Makefile | 6 +- arch/arm/kvm/hyp/banked-sr.c | 4 + arch/arm/kvm/hyp/switch.c | 16 +- arch/arm64/Kconfig | 16 ++ arch/arm64/include/asm/alternative.h | 41 +++- arch/arm64/include/asm/cpucaps.h | 2 +- arch/arm64/include/asm/insn.h | 16 ++ arch/arm64/include/asm/kvm_arm.h | 6 +- arch/arm64/include/asm/kvm_asm.h | 19 +- arch/arm64/include/asm/kvm_emulate.h | 78 +++++-- arch/arm64/include/asm/kvm_host.h | 53 ++++- arch/arm64/include/asm/kvm_hyp.h | 29 +-- arch/arm64/include/asm/kvm_mmu.h | 165 +++++++++---- arch/arm64/include/asm/mmu.h | 8 +- arch/arm64/include/asm/sysreg.h | 6 + arch/arm64/kernel/Makefile | 4 +- arch/arm64/kernel/alternative.c | 43 +++- arch/arm64/kernel/asm-offsets.c | 1 + arch/arm64/kernel/bpi.S | 67 ++++-- arch/arm64/kernel/cpu_errata.c | 25 +- arch/arm64/kernel/cpufeature.c | 19 -- arch/arm64/kernel/head.S | 7 + arch/arm64/kernel/insn.c | 190 ++++++++++++++- arch/arm64/kvm/Kconfig | 3 + arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/debug.c | 29 ++- arch/arm64/kvm/guest.c | 3 - arch/arm64/kvm/hyp-init.S | 1 - arch/arm64/kvm/hyp/Makefile | 2 +- arch/arm64/kvm/hyp/debug-sr.c | 88 ++++--- arch/arm64/kvm/hyp/entry.S | 6 +- arch/arm64/kvm/hyp/hyp-entry.S | 86 +++---- arch/arm64/kvm/hyp/switch.c | 382 ++++++++++++++++++------------- arch/arm64/kvm/hyp/sysreg-sr.c | 172 +++++++++++--- arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c | 78 +++++++ arch/arm64/kvm/inject_fault.c | 24 +- arch/arm64/kvm/regmap.c | 67 ++++-- arch/arm64/kvm/sys_regs.c | 199 +++++++++++++--- arch/arm64/kvm/sys_regs.h | 4 +- arch/arm64/kvm/sys_regs_generic_v8.c | 4 +- arch/arm64/kvm/va_layout.c | 227 ++++++++++++++++++ include/kvm/arm_vgic.h | 15 +- include/linux/irqchip/arm-gic-v3.h | 1 + include/linux/irqchip/arm-gic.h | 1 + virt/kvm/arm/aarch32.c | 2 +- virt/kvm/arm/arch_timer.c | 132 ++++++----- virt/kvm/arm/arm.c | 57 ++--- virt/kvm/arm/hyp/timer-sr.c | 44 ++-- virt/kvm/arm/hyp/vgic-v2-sr.c | 159 ------------- virt/kvm/arm/hyp/vgic-v3-sr.c | 246 ++++++++++++-------- virt/kvm/arm/mmu.c | 180 ++++++++++++--- virt/kvm/arm/pmu.c | 36 +-- virt/kvm/arm/vgic/vgic-init.c | 17 -- virt/kvm/arm/vgic/vgic-its.c | 15 +- virt/kvm/arm/vgic/vgic-mmio.c | 3 + virt/kvm/arm/vgic/vgic-v2.c | 163 ++++++++----- virt/kvm/arm/vgic/vgic-v3.c | 75 +++--- virt/kvm/arm/vgic/vgic.c | 120 ++++++++-- virt/kvm/arm/vgic/vgic.h | 6 + 68 files changed, 2508 insertions(+), 1097 deletions(-) create mode 100644 arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c create mode 100644 arch/arm64/kvm/va_layout.c delete mode 100644 virt/kvm/arm/hyp/vgic-v2-sr.c From patchwork Wed Mar 28 12:51:34 2018 Content-Type: text/plain; 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Wed, 28 Mar 2018 12:56:07 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1f1AZz-00033o-Nw for linux-arm-kernel@lists.infradead.org; Wed, 28 Mar 2018 12:53:29 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 95A7B15AB; Wed, 28 Mar 2018 05:53:25 -0700 (PDT) Received: from approximate.cambridge.arm.com (approximate.cambridge.arm.com [10.1.206.75]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C61ED3F25D; Wed, 28 Mar 2018 05:53:21 -0700 (PDT) From: Marc Zyngier To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Subject: [PATCH 05/85] KVM: arm64: Enable the EL1 physical timer for AArch32 guests Date: Wed, 28 Mar 2018 13:51:34 +0100 Message-Id: <20180328125254.31380-6-marc.zyngier@arm.com> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20180328125254.31380-1-marc.zyngier@arm.com> References: <20180328125254.31380-1-marc.zyngier@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180328_055327_813418_403CC75A X-CRM114-Status: GOOD ( 11.74 ) X-Spam-Score: -5.0 (-----) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-5.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [217.140.101.70 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Christoffer Dall , Andrew Jones , Christoffer Dall , Shunyong Yang , Julien Thierry , Peter Maydell , Andre Przywara , Suzuki K Poulose , Will Deacon , Alvise Rigo , Eric Auger , Julien Grall , James Morse , Shih-Wei Li , Catalin Marinas , =?utf-8?b?SsOpcsOpbXkgRmFu?= =?utf-8?b?Z3XDqGRl?= , Dave Martin , Shanker Donthineni Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org From: Jérémy Fanguède Some 32bits guest OS can use the CNTP timer, however KVM does not handle the accesses, injecting a fault instead. Use the proper handlers to emulate the EL1 Physical Timer (CNTP) register accesses of AArch32 guests. Signed-off-by: Jérémy Fanguède Signed-off-by: Alvise Rigo Signed-off-by: Christoffer Dall --- arch/arm64/kvm/sys_regs.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 55982b565eb2..6feb4a2215cb 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1565,6 +1565,11 @@ static const struct sys_reg_desc cp15_regs[] = { { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID }, + /* CNTP_TVAL */ + { Op1( 0), CRn(14), CRm( 2), Op2( 0), access_cntp_tval }, + /* CNTP_CTL */ + { Op1( 0), CRn(14), CRm( 2), Op2( 1), access_cntp_ctl }, + /* PMEVCNTRn */ PMU_PMEVCNTR(0), PMU_PMEVCNTR(1), @@ -1638,6 +1643,7 @@ static const struct sys_reg_desc cp15_64_regs[] = { { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr }, { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 }, + { Op1( 2), CRn( 0), CRm(14), Op2( 0), access_cntp_cval }, }; /* Target specific emulation tables */ From patchwork Wed Mar 28 12:51:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 892178 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="jSR++iCB"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40B7HD1CrXz9s3v for ; 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Wed, 28 Mar 2018 12:58:40 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1f1AaB-00038H-SL for linux-arm-kernel@lists.infradead.org; Wed, 28 Mar 2018 12:53:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A471F164F; Wed, 28 Mar 2018 05:53:29 -0700 (PDT) Received: from approximate.cambridge.arm.com (approximate.cambridge.arm.com [10.1.206.75]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D50383F25D; Wed, 28 Mar 2018 05:53:25 -0700 (PDT) From: Marc Zyngier To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Subject: [PATCH 06/85] KVM: arm: Enable emulation of the physical timer Date: Wed, 28 Mar 2018 13:51:35 +0100 Message-Id: <20180328125254.31380-7-marc.zyngier@arm.com> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20180328125254.31380-1-marc.zyngier@arm.com> References: <20180328125254.31380-1-marc.zyngier@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180328_055339_929999_B5D9A72C X-CRM114-Status: GOOD ( 14.45 ) X-Spam-Score: -5.0 (-----) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-5.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [217.140.101.70 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Christoffer Dall , Andrew Jones , Christoffer Dall , Shunyong Yang , Julien Thierry , Peter Maydell , Andre Przywara , Suzuki K Poulose , Will Deacon , Alvise Rigo , Eric Auger , Julien Grall , James Morse , Shih-Wei Li , Catalin Marinas , =?utf-8?b?SsOpcsOpbXkgRmFu?= =?utf-8?b?Z3XDqGRl?= , Dave Martin , Shanker Donthineni Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org From: Jérémy Fanguède Set the handlers to emulate read and write operations for CNTP_CTL, CNTP_CVAL and CNTP_TVAL registers in such a way that VMs can use the physical timer. Signed-off-by: Jérémy Fanguède Signed-off-by: Christoffer Dall --- arch/arm/kvm/coproc.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c index 6d1d2e26dfe5..3a02e76699a6 100644 --- a/arch/arm/kvm/coproc.c +++ b/arch/arm/kvm/coproc.c @@ -270,6 +270,60 @@ static bool access_gic_sre(struct kvm_vcpu *vcpu, return true; } +static bool access_cntp_tval(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + const struct coproc_reg *r) +{ + u64 now = kvm_phys_timer_read(); + u64 val; + + if (p->is_write) { + val = *vcpu_reg(vcpu, p->Rt1); + kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL, val + now); + } else { + val = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL); + *vcpu_reg(vcpu, p->Rt1) = val - now; + } + + return true; +} + +static bool access_cntp_ctl(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + const struct coproc_reg *r) +{ + u32 val; + + if (p->is_write) { + val = *vcpu_reg(vcpu, p->Rt1); + kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CTL, val); + } else { + val = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CTL); + *vcpu_reg(vcpu, p->Rt1) = val; + } + + return true; +} + +static bool access_cntp_cval(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + const struct coproc_reg *r) +{ + u64 val; + + if (p->is_write) { + val = (u64)*vcpu_reg(vcpu, p->Rt2) << 32; + val |= *vcpu_reg(vcpu, p->Rt1); + kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL, val); + } else { + val = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL); + *vcpu_reg(vcpu, p->Rt1) = val; + *vcpu_reg(vcpu, p->Rt2) = val >> 32; + } + + return true; +} + /* * We could trap ID_DFR0 and tell the guest we don't support performance * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was @@ -423,10 +477,17 @@ static const struct coproc_reg cp15_regs[] = { { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32, NULL, reset_unknown, c13_TID_PRIV }, + /* CNTP */ + { CRm64(14), Op1( 2), is64, access_cntp_cval}, + /* CNTKCTL: swapped by interrupt.S. */ { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32, NULL, reset_val, c14_CNTKCTL, 0x00000000 }, + /* CNTP */ + { CRn(14), CRm( 2), Op1( 0), Op2( 0), is32, access_cntp_tval }, + { CRn(14), CRm( 2), Op1( 0), Op2( 1), is32, access_cntp_ctl }, + /* The Configuration Base Address Register. */ { CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar}, }; From patchwork Wed Mar 28 12:51:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 892181 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; 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Wed, 28 Mar 2018 05:53:29 -0700 (PDT) From: Marc Zyngier To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Subject: [PATCH 07/85] KVM: arm/arm64: No need to zero CNTVOFF in kvm_timer_vcpu_put() for VHE Date: Wed, 28 Mar 2018 13:51:36 +0100 Message-Id: <20180328125254.31380-8-marc.zyngier@arm.com> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20180328125254.31380-1-marc.zyngier@arm.com> References: <20180328125254.31380-1-marc.zyngier@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180328_055340_009014_13A968E5 X-CRM114-Status: GOOD ( 11.80 ) X-Spam-Score: -5.0 (-----) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-5.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [217.140.101.70 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Christoffer Dall , Andrew Jones , Christoffer Dall , Shunyong Yang , Julien Thierry , Peter Maydell , Andre Przywara , Suzuki K Poulose , Will Deacon , Alvise Rigo , Eric Auger , Julien Grall , James Morse , Shih-Wei Li , Catalin Marinas , =?utf-8?b?SsOpcsOpbXkgRmFu?= =?utf-8?b?Z3XDqGRl?= , Dave Martin , Shanker Donthineni Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org From: Shanker Donthineni In AArch64/AArch32, the virtual counter uses a fixed virtual offset of zero in the following situations as per ARMv8 specifications: 1) HCR_EL2.E2H is 1, and CNTVCT_EL0/CNTVCT are read from EL2. 2) HCR_EL2.{E2H, TGE} is {1, 1}, and either: — CNTVCT_EL0 is read from Non-secure EL0 or EL2. — CNTVCT is read from Non-secure EL0. So, no need to zero CNTVOFF_EL2/CNTVOFF for VHE case. Acked-by: Marc Zyngier Acked-by: Christoffer Dall Signed-off-by: Shanker Donthineni Signed-off-by: Christoffer Dall --- virt/kvm/arm/arch_timer.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c index 70268c0bec79..86eca32474cc 100644 --- a/virt/kvm/arm/arch_timer.c +++ b/virt/kvm/arm/arch_timer.c @@ -541,9 +541,11 @@ void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu) * The kernel may decide to run userspace after calling vcpu_put, so * we reset cntvoff to 0 to ensure a consistent read between user * accesses to the virtual counter and kernel access to the physical - * counter. + * counter of non-VHE case. For VHE, the virtual counter uses a fixed + * virtual offset of zero, so no need to zero CNTVOFF_EL2 register. */ - set_cntvoff(0); + if (!has_vhe()) + set_cntvoff(0); } /*