From patchwork Tue Mar 27 09:28:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891439 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="C59g4YV9"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409Qhh5HHMz9s1R for ; Tue, 27 Mar 2018 20:29:55 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1098EC21F88; Tue, 27 Mar 2018 09:29:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AC0C8C21EF7; Tue, 27 Mar 2018 09:29:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8E638C21F2B; Tue, 27 Mar 2018 09:29:47 +0000 (UTC) Received: from mail-pl0-f65.google.com (mail-pl0-f65.google.com [209.85.160.65]) by lists.denx.de (Postfix) with ESMTPS id D8B1CC21E2B for ; Tue, 27 Mar 2018 09:29:46 +0000 (UTC) Received: by mail-pl0-f65.google.com with SMTP id p9-v6so13741371pls.2 for ; Tue, 27 Mar 2018 02:29:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=BoPBD3nyNIYu3uylLlInvqpokWuHZb07U/gzKjCqLRA=; b=C59g4YV9ZnjYsGMp6mLq3q6bW7gZfL1MFKS9tL/tvP3JV88Y5E04kmC4C6iUEKGelX 8TGJg/7RovPKMovwENiWvqVzKUUGOmQHJVIlDVzsVVaHN9P89oYLsCX5VpbnOFZamOO4 gAVPUlMLsFx01fUo3jjq+PqHOCYykdp+CWz07wnGIWe1e1C6beRwpXJhVjB1HbwrnYLY Gcs2ZoE+NDFK+kFwSAqH6SW4KzHaVO3qthnq79NHALEJwqjH6yQtZwMSn+8bJFsC7BTv Am2s4MU07uGUjpKdPxa+7HoH7WZmFZHdSJpPqC4V7LGE0uFbCB9JY+MF9aeRWzhTTjU1 5nCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=BoPBD3nyNIYu3uylLlInvqpokWuHZb07U/gzKjCqLRA=; b=XMNuETDvNBR8ubLTKkLzAXV5f/cUtc2m0XU+XvzbRMP1z9bdDFvdh8bHreR0p1/pfc Qxte4TURmmmK04gd/Z1xfPmqVpVtShQLYdDJ0mayMMTFaW9gkuZOtxiCormoyLV4ZFmf GccfBHPcoi6jAHrf3p28VZH/KgFmJPNDzAIvHG8YnToPoRd1+YpN4Vb7XNEw//1C7yl7 ehPMR1FTSbVhc2GY331bSx2RYgbD5KFTq/8+NY1qqf+yBGoTGtYX7leKucP61FbYfCp3 uMm1Os+gLPxw1WY2auyZW4vDvwes59+M6kgo+N59GSjZtBfhyLId3EQOinbeGnGC6ESC 7tCQ== X-Gm-Message-State: AElRT7G4afK8DqNRmQfQ0UrbrbCenlHhykNOq4koN0fSH9pUqmqLnTFz AkpAUUHLae42z6Lig3rpYQiTwg== X-Google-Smtp-Source: AIpwx48JjYYG8A5Ra0/B9OYyFHlQUDCjplVdYNyuj6K8h1o6C5E6WlWPORDardiNRIkVBaIoniwDFQ== X-Received: by 2002:a17:902:768a:: with SMTP id m10-v6mr2982274pll.325.1522142985103; Tue, 27 Mar 2018 02:29:45 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.29.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:29:44 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:28:55 +0800 Message-Id: <1522142971-20739-2-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 01/36] rockchip: rk3288: move configure_l2ctlr back to rk3288 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The configure_l2ctlr() is used only by rk3288, do not need to locate in sys_proto.h Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/sys_proto.h | 22 ---------------------- arch/arm/mach-rockchip/rk3288/rk3288.c | 26 +++++++++++++++++++++++++- 2 files changed, 25 insertions(+), 23 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h index e428d59..3617ac2 100644 --- a/arch/arm/include/asm/arch-rockchip/sys_proto.h +++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h @@ -7,27 +7,5 @@ #ifndef _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H -#ifdef CONFIG_ROCKCHIP_RK3288 -#include - -static void configure_l2ctlr(void) -{ - uint32_t l2ctlr; - - l2ctlr = read_l2ctlr(); - l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ - - /* - * Data RAM write latency: 2 cycles - * Data RAM read latency: 2 cycles - * Data RAM setup latency: 1 cycle - * Tag RAM write latency: 1 cycle - * Tag RAM read latency: 1 cycle - * Tag RAM setup latency: 1 cycle - */ - l2ctlr |= (1 << 3 | 1 << 0); - write_l2ctlr(l2ctlr); -} -#endif /* CONFIG_ROCKCHIP_RK3288 */ #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index acc3b79..1e1c6be 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -3,15 +3,39 @@ * * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #define GRF_SOC_CON2 0xff77024c +#ifdef CONFIG_SPL_BUILD +static void configure_l2ctlr(void) +{ + u32 l2ctlr; + + l2ctlr = read_l2ctlr(); + l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ + + /* + * Data RAM write latency: 2 cycles + * Data RAM read latency: 2 cycles + * Data RAM setup latency: 1 cycle + * Tag RAM write latency: 1 cycle + * Tag RAM read latency: 1 cycle + * Tag RAM setup latency: 1 cycle + */ + l2ctlr |= (1 << 3 | 1 << 0); + write_l2ctlr(l2ctlr); +} +#endif + int arch_cpu_init(void) { /* We do some SoC one time setting here. */ - +#ifdef CONFIG_SPL_BUILD + configure_l2ctlr(); +#else /* Use rkpwm by default */ rk_setreg(GRF_SOC_CON2, 1 << 0); From patchwork Tue Mar 27 09:28:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891442 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SUSdwIZ8"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409Qkq1QKCz9s1P for ; Tue, 27 Mar 2018 20:31:47 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E2245C22006; Tue, 27 Mar 2018 09:30:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 06B7EC21F80; Tue, 27 Mar 2018 09:30:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6CD6CC21F9B; Tue, 27 Mar 2018 09:29:55 +0000 (UTC) Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by lists.denx.de (Postfix) with ESMTPS id 76984C21F80 for ; Tue, 27 Mar 2018 09:29:51 +0000 (UTC) Received: by mail-pf0-f196.google.com with SMTP id g14so2116530pfh.3 for ; Tue, 27 Mar 2018 02:29:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=eMkZO4ByXVC9yEnA8EwkUaY0C2+b9KOrn2l9V51ZlEE=; b=SUSdwIZ8VdL99BigDxI3Nd9HZCfD6c8b/jj4P/faUacIuvV/+8eVhuYDzvsGxSoxqz YmvJO//rF6M1mk01ixffxj6nP8Z6EjqoccowS8zP49K89Y16CawaW8GP+n5pLB00goIw 7vbLzarjSq8ROnbF1BnRcnTsgE3l62r7w032LU+AZsVyF2mbGw3uqPQOCNtGI03tzF9s B69S2UTJplH81ICtFhEOK5LXm2HYNUJDftr1AH/w6FRptF07usscoFK1L/y8/9BINGmq qPa9X/bC6DoxMQaAUebdd5QoqPOScHTbEhf6wqL8bhRnLWs7XQe7caqVzZ4aZh5KP+bV T1hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=eMkZO4ByXVC9yEnA8EwkUaY0C2+b9KOrn2l9V51ZlEE=; b=N+59G/SSSnSkzJhyPy1gLEJphWCPjgx+BsW7qLP8gizoAHfY73qme1hIzAsoW/xCyc XFaLZn8ByJpGPPGt2e3pG0+x80royzeIkf+Lp/OP3jLE3/Qcm7nLpDi8TFl1jmFOk52H TQNHltA4j1cYKUf5IVgZTMTsurIV5+PQWdi+hCdJZw4ApU6q9/d+aPzfR0vnPTgT69Fi hUkBkTUdvlw/wgmga54BEDZVYsiMp3TOW8HJzaWoBg5QlvyohsanuCShnqEWpM7AFCHl 9sNEu6d4UvZT9OFCC5h2aed5mQBF97C7TWv5RnqFJcoUby+tNXb90qgoelCYDPcHWnbU NwTw== X-Gm-Message-State: AElRT7Eq6qDppT3hZ/g1XJ4sgPtU4kPkeMxULgygwUDVT8wYMlcupz9V U9eolEm/iqySxIBYwBJKf6SHnw== X-Google-Smtp-Source: AG47ELtf/b+Y4U7jBf6Z1h88xaMVu+c/D2YwORLdJc4/EEdUozenXcDt7wZ4z5fZnc6VqRf9LdhAHg== X-Received: by 10.98.50.130 with SMTP id y124mr36019763pfy.147.1522142989398; Tue, 27 Mar 2018 02:29:49 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.29.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:29:48 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:28:56 +0800 Message-Id: <1522142971-20739-3-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: Thomas Petazzoni , Chris Packham , Klaus Goger , Andy Yan , Maxime Ripard , =?utf-8?q?Andreas_F=C3=A4rber?= Subject: [U-Boot] [PATCH 02/36] rockchip: add common MACRO to enable sys arch timer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" All rockchip SoCs can use ARM arch timer, let's enable it in common header file Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- include/configs/rk3368_common.h | 2 -- include/configs/rk3399_common.h | 2 -- include/configs/rockchip-common.h | 4 ++++ 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 10f643f..a7fe4ca 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -22,8 +22,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT -#define COUNTER_FREQUENCY 24000000 - #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index d700bf2..fe8c675 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -17,8 +17,6 @@ #define CONFIG_SPL_SPI_LOAD #endif -#define COUNTER_FREQUENCY 24000000 - #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 26d41b5..24651ce 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -8,6 +8,10 @@ #define _ROCKCHIP_COMMON_H_ #include +#define COUNTER_FREQUENCY 24000000 +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ_CLOCK 24000000 + #ifndef CONFIG_SPL_BUILD /* First try to boot from SD (index 0), then eMMC (index 1) */ From patchwork Tue Mar 27 09:28:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891440 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Q97nPgJr"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409Qjc0gRqz9s1P for ; Tue, 27 Mar 2018 20:30:44 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A4876C21FA5; Tue, 27 Mar 2018 09:30:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BDE3EC21FB8; Tue, 27 Mar 2018 09:30:09 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 94073C21EF7; Tue, 27 Mar 2018 09:30:00 +0000 (UTC) Received: from mail-pf0-f193.google.com (mail-pf0-f193.google.com [209.85.192.193]) by lists.denx.de (Postfix) with ESMTPS id AD1AAC21F98 for ; Tue, 27 Mar 2018 09:29:56 +0000 (UTC) Received: by mail-pf0-f193.google.com with SMTP id t16so4413377pfh.4 for ; Tue, 27 Mar 2018 02:29:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=JAUEJ4PqCogPvDPZ9p/+qUyhQGauyLk0zsagcDQsVeE=; b=Q97nPgJrT/3VNqxdgIO3XfRysFovdDpGpqMga8rDDYUGXnnphNjVmLpmJq/f292uif VPwGC0A7UILwAPglwTCcGnzWbGbKMogONAoRct1PsJXPWSiFSiJl53F0jT8eFooIwgmK 1/cWoezhEUGZjXHQF5nryxSEP5SRG8d30sxkq2cHRfkhajTI2Vpi6n3IbOKAx9A3v3E2 FKtdiLrPm0KdGqcUiQmdhkB5afEI2/paCGuVm3xq+X5zz8hrSZwPANOAB/uA9i3I/7m6 FMXIWiphJ2+EykI9r3KM0qaP9eL8f/JYuPHyZCwO8ZenWNUSZVHzy/euIpz5ljuVqdd9 4kfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=JAUEJ4PqCogPvDPZ9p/+qUyhQGauyLk0zsagcDQsVeE=; b=doI/CjEoeNQ/Mkq922biEQkpLteRKPdb+Wto0PDUbdW3ft71o0xbMRhjjraNj4DEZ7 uShUuWDCM1BlrxO3zpxJQ1VIE8T0fNUEtrlj/q54zVBp+oYafrOw/0PSGylA07y3li+Y ftOniaUexphVGlpiHPNHBALdlDlESVZBUDaBAKXBogh5y01iSmiWWjFhBAXORq4RjrAu 7BplWTNHoygvr+IWcspa0ua/pK7eu2rIV57oCTZyVY/H8in+t354RZIoKF1UorAn7rsP Ex790RpChK5LpOyED7S5PtdtBQKgACLe87joAIFe3Trz+8aWOiM9k6GJN1bXiDtt/Eh7 qtgw== X-Gm-Message-State: AElRT7HbsvPjDFTNH4gz7GcbQKVtbvXqwWQBYPRNbw7NiDR76Rq3cQX2 6Lc/tkruz2K3FMd+zMZ9OGTFeA== X-Google-Smtp-Source: AG47ELu6EAdYfW9znogL6Xsefmkg2dCU8a290W1GrWx+hdBd/TfsaHS0UDMsf/t942tBX8kTjrw54A== X-Received: by 10.101.90.203 with SMTP id d11mr30212451pgt.20.1522142994818; Tue, 27 Mar 2018 02:29:54 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.29.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:29:53 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:28:57 +0800 Message-Id: <1522142971-20739-4-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: Thomas Petazzoni , Chris Packham , Klaus Goger , Andy Yan , Maxime Ripard , =?utf-8?q?Andreas_F=C3=A4rber?= Subject: [U-Boot] [PATCH 03/36] rockchip: enable SYS_NS16550 for all SoCs by default X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" All rockchip SoCs can use ns16550 driver, enable it for all and set SYS_NS16550_MEM32 for all SoCs. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- arch/arm/Kconfig | 1 + arch/arm/mach-rockchip/Kconfig | 1 - include/configs/rk3036_common.h | 3 --- include/configs/rk3128_common.h | 2 -- include/configs/rk3188_common.h | 2 -- include/configs/rk322x_common.h | 1 - include/configs/rk3288_common.h | 2 -- include/configs/rk3328_common.h | 2 -- include/configs/rk3368_common.h | 2 -- include/configs/rk3399_common.h | 2 -- include/configs/rockchip-common.h | 2 ++ include/configs/rv1108_common.h | 3 --- 12 files changed, 3 insertions(+), 20 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2c52ff0..3e9a80d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1167,6 +1167,7 @@ config ARCH_ROCKCHIP select DM_PWM select DM_REGULATOR select ENABLE_ARM_SOC_BOOT0_HOOK + select SYS_NS16550 imply CMD_FASTBOOT imply FASTBOOT imply FAT_WRITE diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 0adaed4..007cb22 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -103,7 +103,6 @@ config ROCKCHIP_RK3368 imply SPL_SERIAL_SUPPORT imply TPL_SERIAL_SUPPORT select DEBUG_UART_BOARD_INIT - select SYS_NS16550 help The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised into a big and little cluster with 4 cores each) Cortex-A53 including diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index f39a272..c5ec864 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -18,9 +18,6 @@ #define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 #define CONFIG_SYS_LOAD_ADDR 0x60800800 #define CONFIG_SPL_STACK 0x10081fff diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index bd8019c..c593f18 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -19,8 +19,6 @@ #define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) -#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 #define CONFIG_SYS_LOAD_ADDR 0x60800800 diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 94f8cda..30c150e 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -22,8 +22,6 @@ #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) #define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_NS16550_MEM32 - #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ #endif diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 7f9c7fb..832f037 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -18,7 +18,6 @@ #define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */ #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 #define CONFIG_SYS_LOAD_ADDR 0x60800800 #define CONFIG_SPL_STACK 0x10088000 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 78595b8..44d5c2a 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -19,8 +19,6 @@ #define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */ #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) -#define CONFIG_SYS_NS16550_MEM32 - #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM /* Bootrom will load u-boot binary to 0x0 once return from SPL */ #endif diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 7018668..ce650c8 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -13,8 +13,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index a7fe4ca..866383d 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -22,8 +22,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00280000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index fe8c675..53691e5 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -17,8 +17,6 @@ #define CONFIG_SPL_SPI_LOAD #endif -#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0xff8effff diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 24651ce..4062480 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -12,6 +12,8 @@ #define CONFIG_SYS_ARCH_TIMER #define CONFIG_SYS_HZ_CLOCK 24000000 +#define CONFIG_SYS_NS16550_MEM32 + #ifndef CONFIG_SPL_BUILD /* First try to boot from SD (index 0), then eMMC (index 1) */ diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 349c53c..cd204e9 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -18,9 +18,6 @@ #define CONFIG_SYS_TIMER_BASE 0x10350020 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) From patchwork Tue Mar 27 09:28:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891459 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="VZsQqQcZ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409QnY5Syfz9s1R for ; Tue, 27 Mar 2018 20:34:09 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 7B7B2C22072; Tue, 27 Mar 2018 09:31:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9782DC21FB1; Tue, 27 Mar 2018 09:30:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 02709C21FB8; Tue, 27 Mar 2018 09:30:04 +0000 (UTC) Received: from mail-pg0-f68.google.com (mail-pg0-f68.google.com [74.125.83.68]) by lists.denx.de (Postfix) with ESMTPS id 5F13CC21F9C for ; Tue, 27 Mar 2018 09:30:00 +0000 (UTC) Received: by mail-pg0-f68.google.com with SMTP id a15so8349176pgn.5 for ; Tue, 27 Mar 2018 02:30:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=2/dlLTOc/f0rATZpZhRwaPT9M+DOnU2A92SrHgzNgXE=; b=VZsQqQcZINbSG/3NN/XauCADveScSBVU6XHBR2DL+cPMcEa38fcN4sh622cZcMa+CM xNHQ8NFp7zmnuQzyXR9lMZRqWP6280HdSayRh0IyQIsGIiAu58kb13ftWRuljUvx5WC1 MM2hcw8sjvSkc0ioiNSXJpI5Gef2XFDIeMBRXsRnAw+83LM7lQh3QzPuQwFT+IiehwAy kXIG2z5VaAIbpcgbuFXkhnf9Wt/e0aA9468NoWkMx3CFgbeSKNJ7sEo2j6Dze14FatK6 +HyVQudUyLlCqSCCLVLWCXVYnuErCfGxUTcmQ/oTenL9SCSw53BL/EylexqL3Tg9Dpq/ gsJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=2/dlLTOc/f0rATZpZhRwaPT9M+DOnU2A92SrHgzNgXE=; b=pPAIoHChAH9i5J5cthaQrcv36Ie3moiRF8ZJXqOKcq5X9UmesdOSgUwWyASrqc/TZ+ RzHXuFRJAcABMvMzl/MFCcGsy0wuD4LJEM0ANCCan+aRf3QOcs4M+AVaGuPYyq4hY1GD fbPdJfeABlww7xxAlBCVvecH6h53l4nxEwlieBdFFB+nh0LJCQUCLLs9gWitV/S9QXuz y4CaSwPLtjkYtESrMlUbL76Mb+G5cJB16nlTy74R4CsKKa7WQ3za824luBBXaC6FyreY eUZ0MsEmHbHEYM8En6sQbzbIQBYcS1EoWv00lDCMk2qO7cAwh5Mxpf72xS31jJlhT6AF MqMg== X-Gm-Message-State: AElRT7EHyQ1kvSKjIETAb0uKlpFHzaHcWdXpnq3+zMVuyrUNThC8K4FG VX6asBFnLVq5CUpLEqbk/xDHOA== X-Google-Smtp-Source: AG47ELsrrCPDHBLaso7NJvXeKaK/5r4YNS5ArIPzbj6eciiM8gEUMcjizpam2lw7JUGFZGC4CCvWOg== X-Received: by 10.101.75.135 with SMTP id t7mr16832792pgq.235.1522142998504; Tue, 27 Mar 2018 02:29:58 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.29.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:29:57 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:28:58 +0800 Message-Id: <1522142971-20739-5-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: Jernej Skrabec , Lin Huang , Klaus Goger Subject: [U-Boot] [PATCH 04/36] rockchip: defconfig: remove CONFIG_SYS_NS16550 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We have enable NS16550 in Kconfig, do not need enable at defconfig Signed-off-by: Kever Yang Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- configs/evb-rk3128_defconfig | 1 - configs/evb-rk3229_defconfig | 1 - configs/evb-rk3288_defconfig | 1 - configs/evb-rk3328_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/fennec-rk3288_defconfig | 1 - configs/firefly-rk3288_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/miqi-rk3288_defconfig | 1 - configs/phycore-rk3288_defconfig | 1 - configs/popmetal-rk3288_defconfig | 1 - configs/puma-rk3399_defconfig | 1 - configs/tinker-rk3288_defconfig | 1 - configs/vyasa-rk3288_defconfig | 1 - 14 files changed, 14 deletions(-) diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index e7414c9..367c654 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -33,7 +33,6 @@ CONFIG_DM_RESET=y CONFIG_DEBUG_UART_BASE=0x20068000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 5ec9788..96afda8 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -45,7 +45,6 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_BASE=0x11030000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_GADGET=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 7ba7178..b8189fd 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -64,7 +64,6 @@ CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 266d699..3fb1cfc 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -43,7 +43,6 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index b5ae073..7e3e97d 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -55,7 +55,6 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig index 11112ca..0b6e8b9 100644 --- a/configs/fennec-rk3288_defconfig +++ b/configs/fennec-rk3288_defconfig @@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index adb6b5d..dc856b0 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -67,7 +67,6 @@ CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 03d0324..ed30652 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -57,7 +57,6 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index a2e58a7..c62158a 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index bd698f5..8e4e04d 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -67,7 +67,6 @@ CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index 0d85349..2beee6e 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index a8b4bac..8ff73be 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -80,7 +80,6 @@ CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_BASE=0xFF180000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYS_NS16550=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index f8ff916..1c28817 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -66,7 +66,6 @@ CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index 4c76041..a15c65f 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -60,7 +60,6 @@ CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y From patchwork Tue Mar 27 09:28:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891462 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="R4XuzQOn"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409Qq22V4Dz9s1S for ; Tue, 27 Mar 2018 20:35:26 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 07B28C22011; Tue, 27 Mar 2018 09:32:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 96D65C21FBB; Tue, 27 Mar 2018 09:30:47 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 22A59C21FBA; Tue, 27 Mar 2018 09:30:05 +0000 (UTC) Received: from mail-pf0-f193.google.com (mail-pf0-f193.google.com [209.85.192.193]) by lists.denx.de (Postfix) with ESMTPS id DBBE7C21EF7 for ; Tue, 27 Mar 2018 09:30:02 +0000 (UTC) Received: by mail-pf0-f193.google.com with SMTP id l27so8634430pfk.12 for ; Tue, 27 Mar 2018 02:30:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=8GPU6ex2MwOyLFIwShr19ManRaeUteTX2CA6DGKdgTo=; b=R4XuzQOne5G5JwwOdsUWSwkLmEIycgjhbDOiQsvBiESiPOqDhZRO+WN7ER2f2cjWr3 LeAyIozbsVORbsv/rHdNwwBn00CAe0OHjffNfJ+ntFlnVh6VL1gV0OL5jJ0fQRmK+0GR YUOgyhU5M74PLCUiTn/7bF6dZSGiObgdMKLXo/dDJsZfHPAvD+NKDy4J47vXAkjBlJxv SKtMdbVOxfMmkC0CXIVMgdoaHI2zhYJe2LZy3XLd1Zds0nudAUrfBIfT2OZYUOXr3CcH UFZnswgDyr/S25DLo6/woGwxijLPWelCQS0sR+irYpHcgiFBM6yGRIEqDjzgm5oRHE54 vrfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=8GPU6ex2MwOyLFIwShr19ManRaeUteTX2CA6DGKdgTo=; b=jGRi0/Y9iO6yf5oAU5TFJM01elCe+NodopUqqNB0g4s6eVJ8xGv7lYE2YejCpAa2us SpCogl9x4q558NmFG6MDgjB1fJD9vOeOHXjyu6N5kg9QrGJQqq3Mne4D0JfsKw9YzZH5 EbxPyfae8hZETTVQRvooxB4fs5RiKcuHQwiaCgq5WFU2aT3Mt4srPp8gVDdAWeP37Vsx YHkDZJfVheohUnBUDDKJqTfj9QL2z0U/zLi5X+S/ZX1Ug6YKXp0TW2PMYmTAyyBMeKlW 2CrcpBUZm3Ylx1sdYjviKyrnRfj/W4Jj2xPVMVGCRvAubPbC0dTaoxkXIw9SxUFn9haC +2ng== X-Gm-Message-State: AElRT7EdFKuR5H3U4KOQKsYycbzNMDBNTlbCqe62g8Kb07WjHJePe26B sz4Hoz+P9SsWN4tC5SdRdto+5w== X-Google-Smtp-Source: AG47ELsU5802JZx0+4F9TMzejXRtXhlQSaJM6zHhtlKvSz93Ty0ThOpPrBKxxKGOD0/+5iaUulB/5Q== X-Received: by 10.99.169.1 with SMTP id u1mr18847451pge.251.1522143001194; Tue, 27 Mar 2018 02:30:01 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.29.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:00 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:28:59 +0800 Message-Id: <1522142971-20739-6-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 05/36] rockchip: add STIMER_BASE for all SoCs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" STIMER is can only access in secure mode if the SoCs supports trust, and it locate in alive power domain, as the source of ARM arch/generic timer, we add a base addr for all SoCs so that we can init with a common function. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/Kconfig | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 007cb22..5dfe452 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -190,6 +190,25 @@ config ROCKCHIP_BOOT_MODE_REG The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h) according to the value from this register. +config ROCKCHIP_STIMER_BASE + hex "Rockchip Secure timer base address" + default 0xff220020 if ROCKCHIP_PX30 + default 0x200440a0 if ROCKCHIP_RK3036 + default 0x2000e000 if ROCKCHIP_RK3066 + default 0x20018020 if ROCKCHIP_RK3126 + default 0x200440a0 if ROCKCHIP_RK3128 + default 0x2000e000 if ROCKCHIP_RK3188 + default 0x110d0020 if ROCKCHIP_RK322X + default 0xff810020 if ROCKCHIP_RK3288 + default 0xff1d0020 if ROCKCHIP_RK3328 + default 0xff830020 if ROCKCHIP_RK3368 + default 0xff8680a0 if ROCKCHIP_RK3399 + default 0x10350020 if ROCKCHIP_RV1108 + default 0 + help + The secure timer inited in SPL/TPL in secure word, ARM generic timer + works after this timer work. + config ROCKCHIP_SPL_RESERVE_IRAM hex "Size of IRAM reserved in SPL" default 0 From patchwork Tue Mar 27 09:29:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891463 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="paRg83gS"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409Qqk0gt1z9s1S for ; Tue, 27 Mar 2018 20:36:01 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C3812C21FDE; Tue, 27 Mar 2018 09:35:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9CBA9C21FD3; Tue, 27 Mar 2018 09:30:59 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4A63DC21FC3; Tue, 27 Mar 2018 09:30:06 +0000 (UTC) Received: from mail-pf0-f193.google.com (mail-pf0-f193.google.com [209.85.192.193]) by lists.denx.de (Postfix) with ESMTPS id 9CD32C21FAB for ; Tue, 27 Mar 2018 09:30:05 +0000 (UTC) Received: by mail-pf0-f193.google.com with SMTP id t16so4413499pfh.4 for ; Tue, 27 Mar 2018 02:30:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=F66ofSKXgN9raZJMnGJriirvs51SEpKT5lvO6UkKCDU=; b=paRg83gSb6mZBVzzVzW4Z6xgnz9yM3A3YMiYjcFX6vjVgo2dQ7mpvjrb0Z4TXcnwbT 85MW630elSavvO2fRsP+T+iby7ubUJdMk7H4RQj4YSomO2hV4n2/zAdJMNuWOfX9aPqk ttE7gdHS2LkVaSvaSShiJO3NC7jV8LlDNGlQ3MswQsJxIY0zWlAmYSBGp2FoXDC3qSYn Pzr+Rw0fsyctlvIeoDso3FZKjYVpeM5Q5sqamw1vQNyCB7WbCRU9sCU/B/bFCLjvXxeJ d10tFWoNEifMWONvEJXt5uig2vw+8qgYR3AuSY5yUEU0oiF6y4BSgy+CDbHZdILbJdh5 GdyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=F66ofSKXgN9raZJMnGJriirvs51SEpKT5lvO6UkKCDU=; b=GFqS53BtJENmtJgCfDnLZa/2JlDEf+MqC4GS8CSB3JGa+1E3o9f3hMff5+nmdYPzZ9 TzEORYEsxHcGNkyGx6JrTmB3Sh5iONnbWI6b3qaA3Zmy7bbg6rofHCU6A77eqwTFzP+3 fAWSgQt8GXqc9zjimV8QQ8pW1iBn3sB9C4+ewflPV2B0fWSUYwZeYtqKBk9bT3NVmLV6 2qQmapbIaP0fxteQ7S8/5/y++PF1k8L+64UpnbVtyGQr5goS6B8drNX2bFXTjUvgC7CS RSdisXyhP18RdulwEEZ+i+Db6hef9kUaxZ87saXwAg3aFRc09NUWqzj016w5SDtsGcfX u9Rw== X-Gm-Message-State: AElRT7EqUwbxyRs5UuiZ2slckjKhBm+sZysPDOEWm//8HHTTVgKLdhvo xmpvA25uUH4wjzycn5iWvWzvgw== X-Google-Smtp-Source: AIpwx4+Xn4pyEhzfz4QQe6ftL3ThtYMNvdvBNWd0Lx6hdXyugy33VoBZLmAlIzAbI8/9Yg1vAsepbw== X-Received: by 10.101.92.74 with SMTP id v10mr4353672pgr.289.1522143003922; Tue, 27 Mar 2018 02:30:03 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:03 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:00 +0800 Message-Id: <1522142971-20739-7-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 06/36] rockchip: add IRAM_START_ADDR for all SoCs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We add this for get the location for boot device of bootrom. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/Kconfig | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 5dfe452..98bf935 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -209,6 +209,23 @@ config ROCKCHIP_STIMER_BASE The secure timer inited in SPL/TPL in secure word, ARM generic timer works after this timer work. +config ROCKCHIP_IRAM_START_ADDR + hex "Rockchip Secure timer base address" + default 0xff0e0000 if ROCKCHIP_PX30 + default 0x10080000 if ROCKCHIP_RK3036 + default 0x10080000 if ROCKCHIP_RK3128 + default 0x10080000 if ROCKCHIP_RK3188 + default 0x10080000 if ROCKCHIP_RK322X + default 0xff700000 if ROCKCHIP_RK3288 + default 0xff091000 if ROCKCHIP_RK3328 + default 0xff8c0000 if ROCKCHIP_RK3368 + default 0xff8c0000 if ROCKCHIP_RK3399 + default 0x10080000 if ROCKCHIP_RV1108 + default 0 + help + The IRAM start addr is to locate variant of the boot device from + bootrom. + config ROCKCHIP_SPL_RESERVE_IRAM hex "Size of IRAM reserved in SPL" default 0 From patchwork Tue Mar 27 09:29:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891461 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Av2WZJRT"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409Qpf2xzqz9s1S for ; Tue, 27 Mar 2018 20:35:06 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 12F13C22080; Tue, 27 Mar 2018 09:32:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8C160C21FB3; Tue, 27 Mar 2018 09:30:52 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 19E0DC21FC9; Tue, 27 Mar 2018 09:30:09 +0000 (UTC) Received: from mail-pg0-f67.google.com (mail-pg0-f67.google.com [74.125.83.67]) by lists.denx.de (Postfix) with ESMTPS id 6E1A9C21FA1 for ; Tue, 27 Mar 2018 09:30:08 +0000 (UTC) Received: by mail-pg0-f67.google.com with SMTP id y63so5210509pgy.12 for ; Tue, 27 Mar 2018 02:30:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=HRq7qtjTwZkfiMZuQpZRjPm8oVnEzDzBq++XreUEgrc=; b=Av2WZJRTl0DpZgJ223NfbVbOedTaquxWns/hnniTvzOLxRDz1PpfbGAl8YfoLCvS3W /36HnFFpJad6xzuT11Y40QGjcG/KB8D1FcuDfWGsWeQZIX/SPx3TyJglzXdpJ2u7cvS0 UPpLV0fGggoqt4vd/NxICuaBQeptZjephsHEctg7cj3W9FvOhMgWlZ24Tj3rG+hv7X7Y rHvQHpN46LqM3Nu1qn+Y0VPoE/zaNQbsWmV+qr0mmKkqVE4ycm+3LoyTQF2KXorJzlZh DscYEP4R/l4C30TBnchWAa1dT7jW5cf7Ueq9QRsUe1zHDXPsuOaVeKwmIt/UJ3kPI/Om H1kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=HRq7qtjTwZkfiMZuQpZRjPm8oVnEzDzBq++XreUEgrc=; b=L7dMUN3yZYzKxu7C3YPGqYamd/OBvSH3I70MFTk0N4o6jkl8wCojF9qfyasSIzsMPC IZlFeVF2BFiJS4ZjJJ5ZErvmdtxfzHU85jRwVeC5l9cLT8BmKl/Db4KpCGVAuO0DKxfM Tk7ZTs5dIHDo5DvCOsRVHmICs0/u3iF3AR+iPwDa21beykyNEAPGCuVoeFiiGWkarqj5 1N0c1FkG580yq/jVP5kTdVIQR6aJErzcLGo3dggc1XY6Xzqb5FdlMit7F/u3ozoTpLEA 2ACD/32RF1GcNhl8rZAAjShyN+6OBI1fyChJil40e4mz+Ah4PdaM+NwA65ujYF/RKfMC HOrQ== X-Gm-Message-State: AElRT7HqKun0yxQ91oYM1OYfFOp/Qx0JVHyJy7kxTrToEICaer7luRSx iFI4Tp5JVyDlAqJkaE50v8B4zA== X-Google-Smtp-Source: AG47ELvFvIANK63bl7j9B3wDZgXGMkVOSD1jxBvb791GFUw9HRaV5+ulOhjLkJZKgrbCLuqMlrjyBA== X-Received: by 10.98.103.69 with SMTP id b66mr35757682pfc.151.1522143006650; Tue, 27 Mar 2018 02:30:06 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:05 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:01 +0800 Message-Id: <1522142971-20739-8-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 07/36] rockchip: rk3328: add BOOT_MODE_REG for rk3328 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 98bf935..892d51e 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -182,6 +182,7 @@ config ROCKCHIP_BOOT_MODE_REG default 0x20004040 if ROCKCHIP_RK3188 default 0x110005c8 if ROCKCHIP_RK322X default 0xff730094 if ROCKCHIP_RK3288 + default 0xff1005c8 if ROCKCHIP_RK3328 default 0xff738200 if ROCKCHIP_RK3368 default 0xff320300 if ROCKCHIP_RK3399 default 0x10300580 if ROCKCHIP_RV1108 From patchwork Tue Mar 27 09:29:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891441 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="H4bqitd9"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409Qk53y9hz9s1S for ; Tue, 27 Mar 2018 20:31:09 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 39D2DC21FDD; Tue, 27 Mar 2018 09:30:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1AE08C21F8A; Tue, 27 Mar 2018 09:30:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3C126C21F94; Tue, 27 Mar 2018 09:30:16 +0000 (UTC) Received: from mail-pg0-f67.google.com (mail-pg0-f67.google.com [74.125.83.67]) by lists.denx.de (Postfix) with ESMTPS id A4F71C21FAD for ; Tue, 27 Mar 2018 09:30:11 +0000 (UTC) Received: by mail-pg0-f67.google.com with SMTP id t10so2215007pgv.8 for ; Tue, 27 Mar 2018 02:30:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=YxttIJoqGufZVgTVRApesLFVaYxcxMngFSC1doNnXKk=; b=H4bqitd943aQMQG4J5a9aO8PZkxs5pf1uLE89hAe4qtPemLl3VYIwyLus9Itt3IFuQ 3VesX9hxCjiVDiEYiqaT2nma+KMackj6WWuKqP/DWlYL+MHO7leSiik6yf6u8i81Kl9X Fe0Hr/JhTgTZPIG0rYlCOi7V4MZNMWRDgi1vaYwlIABzJBQI7iCp16E0eoXqBZPaS8/q 3Xfkws6yrZT0Y/XhjF+I90tklAUbU9Szd6+qkQbS+XxX05JWBpimcEWridiAXJmYSd6k nJY20WgcDkED8XQb+TZx3tcN1KKmk7FO0tC/OAOI8N2DgmzqdVW7Pttoy9pgTCDdDNCD QlOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=YxttIJoqGufZVgTVRApesLFVaYxcxMngFSC1doNnXKk=; b=VYWb+WcY5TRi0veuSwsz77hpB5O+ff5fOvc+BGe2ZBHFGXBgMQrw6XOIoIE5DeSDvI pEFfoUqEGwGVL8/Ogan7ibjeXDQ8zr+Qjmb9ER94BEORI5DubIsD3yYzJ0eMHhCT7BtT /7tbSpgVqm0js6tswPQcDyG/ZOyWRcCqE5Uur05TMvBB7eRcxbyXSjpY3dIPJuvLzdF5 wA9PdA1nQU3Y9AC61bieTroSygHoNJHMh5aRtN1lvWgX2VwpGimqs6VJ+ZdGBSckoOfE eP4+stpn1SIIlSV/dO1HDljzrzqHH6iCMNkeiHijlYwZKw0IVZrEwcTNUZPHEGLU7ImV IXhA== X-Gm-Message-State: AElRT7F0Ru2wspKTFoGVsrv53ciJMwi7mXC/dIlL+VnLdFD5y/x8Cq2E f9eW8EzPPS1om4K5O1ffxfhG0g== X-Google-Smtp-Source: AG47ELuqWdJc4G917Eabm1qIE3Krjj0JDstGAZXM+gqfaDkpkr0Xlkjy0/r5YsZdTTuawXLSahyeMA== X-Received: by 10.98.137.15 with SMTP id v15mr12533413pfd.95.1522143009862; Tue, 27 Mar 2018 02:30:09 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:08 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:02 +0800 Message-Id: <1522142971-20739-9-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: Thomas Petazzoni , Chris Packham Subject: [U-Boot] [PATCH 08/36] rockchip: rk322x: remove use rockchip timer as sys timer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We can use arch timer instead of rockchip timer. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- include/configs/rk322x_common.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 832f037..29e222a 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -14,9 +14,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ -#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -#define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */ -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 #define CONFIG_SYS_LOAD_ADDR 0x60800800 From patchwork Tue Mar 27 09:29:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891460 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LxxGvcSU"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409QpK2Jq3z9s1S for ; Tue, 27 Mar 2018 20:34:48 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B00ECC22095; Tue, 27 Mar 2018 09:32:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 68F69C21FBA; Tue, 27 Mar 2018 09:30:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 77A09C21F1B; Tue, 27 Mar 2018 09:30:18 +0000 (UTC) Received: from mail-pg0-f65.google.com (mail-pg0-f65.google.com [74.125.83.65]) by lists.denx.de (Postfix) with ESMTPS id 565D9C21FAB for ; Tue, 27 Mar 2018 09:30:14 +0000 (UTC) Received: by mail-pg0-f65.google.com with SMTP id n11so8344045pgp.4 for ; Tue, 27 Mar 2018 02:30:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=SxAqimND9N4ot3K/DD4JjObXhofYlXxZfFWSCBh3fmw=; b=LxxGvcSUX0klrnDgRpcUkHAOfAggBaDibZhw8OybTqRLk3ekUAvOcCsa0zd+yqVN90 HiEARt0VPA7iZ/Z2BFFQhGX+kCmNoSYeas08chIfi5f1gbsUHgLYahzfSTc2bvW03Ru9 zOU3rMjoN6vCizozislKzQlf5wuNd8Dy9yVEha/fASL27ZoDkajA9rfLL8H2M91t4183 HF7ooZ8of22PX7tPuV4OUvwiyLs+07l9/AAZ2WtSbP3Rk6XHfWbzNy3JatscszYK1v5c tt6vJ7W5LJfZqGJsBEFE8voHWYSSc6/X2T5dGZUUhgIf1oCItBEu7i5lriTkqa3Nw94f EQvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=SxAqimND9N4ot3K/DD4JjObXhofYlXxZfFWSCBh3fmw=; b=KWklVaJi26ukWX1CRHbeXpEylpUTnrMMxdbH6KY7cBGNwCeK9BNq28/zwMKEBGxw4H lGpIRjWn6vur+F+fhZsqGO+muvbIgr/OBMZWtt89NpqSi+lWLbBaZtYYRj9xB5ZqayQE gOrnXlpVEZaYBENb7IDLNhn2PGc1LSFiUsBoYmxh4EdSMj4UuJ/yUMfitb0v62AJQOej Z2brOni43MEQhoa7Szq+0GS5XvZVHRsmotMidhbzS0d3c503eiQEsWWgBg6vC5n8PFsC qTiSSYhwlvx4cUVZuiQaQsQST2UriXufmF9S67k39L+fN1fiuZQGaPCyukh97qpCZNAI 5ikQ== X-Gm-Message-State: AElRT7FEu1jGgwRgN+j323v6F9eBoU5cOVtterXZnLyyZcxNmG3YQeUH Qz2zh0TnrgwzIxEK/mSEBlPXKQ== X-Google-Smtp-Source: AG47ELsEktVgXWTq2h++rtwUsFBUVWsDCgyQLQtcVHT6N6Zn8bul/vdkdktBI25tqHCe6y9+aFFsWw== X-Received: by 10.99.96.19 with SMTP id u19mr30098983pgb.261.1522143012457; Tue, 27 Mar 2018 02:30:12 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:11 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:03 +0800 Message-Id: <1522142971-20739-10-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 09/36] rockchip: rk322x: sdram: use common udelay instead of rockchip_udelay X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Do not need to use rockchip_udelay after we can use systimer. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- drivers/ram/rockchip/sdram_rk322x.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index cc3138b..c4da000 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -97,26 +96,26 @@ void phy_pctrl_reset(struct rk322x_cru *cru, 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); clrbits_le32(&ddr_phy->ddrphy_reg[0], SOFT_RESET_MASK << SOFT_RESET_SHIFT); - rockchip_udelay(10); + udelay(10); setbits_le32(&ddr_phy->ddrphy_reg[0], SOFT_DERESET_ANALOG); - rockchip_udelay(5); + udelay(5); setbits_le32(&ddr_phy->ddrphy_reg[0], SOFT_DERESET_DIGITAL); - rockchip_udelay(1); + udelay(1); } void phy_dll_bypass_set(struct rk322x_ddr_phy *ddr_phy, u32 freq) @@ -155,7 +154,7 @@ static void send_command(struct rk322x_ddr_pctl *pctl, u32 rank, u32 cmd, u32 arg) { writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); - rockchip_udelay(1); + udelay(1); while (readl(&pctl->mcmd) & START_CMD) ; } @@ -168,7 +167,7 @@ static void memory_init(struct chan_info *chan, if (dramtype == DDR3) { send_command(pctl, 3, DESELECT_CMD, 0); - rockchip_udelay(1); + udelay(1); send_command(pctl, 3, PREA_CMD, 0); send_command(pctl, 3, MRS_CMD, (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | @@ -197,17 +196,17 @@ static void memory_init(struct chan_info *chan, (0x63 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | (0 & LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); - rockchip_udelay(10); + udelay(10); send_command(pctl, 3, MRS_CMD, (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | (0xff & LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); - rockchip_udelay(1); + udelay(1); send_command(pctl, 3, MRS_CMD, (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | (0xff & LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); - rockchip_udelay(1); + udelay(1); send_command(pctl, 3, MRS_CMD, (1 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | (sdram_params->phy_timing.mr[1] & @@ -244,7 +243,7 @@ static u32 data_training(struct chan_info *chan) DQS_SQU_CAL_SEL_CS0); setbits_le32(&ddr_phy->ddrphy_reg[2], DQS_SQU_CAL_START); - rockchip_udelay(30); + udelay(30); ret = readl(&ddr_phy->ddrphy_reg[0xff]); clrbits_le32(&ddr_phy->ddrphy_reg[2], @@ -368,9 +367,9 @@ static void phy_softreset(struct dram_info *dram) writel(GRF_DDRPHY_BUFFEREN_CORE_EN, &grf->soc_con[0]); clrbits_le32(&ddr_phy->ddrphy_reg[0], 0x3 << 2); - rockchip_udelay(1); + udelay(1); setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 2); - rockchip_udelay(5); + udelay(5); setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 3); writel(GRF_DDRPHY_BUFFEREN_CORE_DIS, &grf->soc_con[0]); } From patchwork Tue Mar 27 09:29:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891483 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Nis5LCL3"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R6W4kXwz9s1S for ; Tue, 27 Mar 2018 20:48:51 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 4CB89C21FDE; Tue, 27 Mar 2018 09:38:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9FAC3C21FB8; Tue, 27 Mar 2018 09:32:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AF695C21F88; Tue, 27 Mar 2018 09:30:22 +0000 (UTC) Received: from mail-pg0-f68.google.com (mail-pg0-f68.google.com [74.125.83.68]) by lists.denx.de (Postfix) with ESMTPS id 41F47C21FB7 for ; Tue, 27 Mar 2018 09:30:17 +0000 (UTC) Received: by mail-pg0-f68.google.com with SMTP id a15so8349429pgn.5 for ; Tue, 27 Mar 2018 02:30:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=aSEIgRJEbCZvFG30qlhI2TTP58wYTK3AN0fii6uCN4M=; b=Nis5LCL362w4vSrAhEXvA78WLr70cgDWGBYviazNXZsFU51Q3MvhK/nR67q++GEmTs k8dQEskrnEbIGi4nP9mRP6w/6tp3mKsAtIznIcXOxXkj1IjwrDpVI8dYdxYOATX/eYyJ HzYkJWsFOeg8ChYco5XC32q5l889PXm5l98drhI/YgIv6jdVTNAY2yd/qKD0fFINPmic OYrgP84vXDdjZg4jUZ064jAh5jjQRvJVpPpIWNSrZCACPqZqt5vA9fcYnw9CuIm5KkfA pZ1mzYgkr/o94CRe4e6O2Sc+56sGYNIJbUu72HzIBTUeOaf6Xwaf0UXCdafQc8PDN+Dn yr5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=aSEIgRJEbCZvFG30qlhI2TTP58wYTK3AN0fii6uCN4M=; b=eAvhcQiq9Z4bxzJwEnWeMdLm4je5pzTiYQQiPYlU2ufuxKkPxm7MwOfdYqEnfeSAOp F9M/pQ6cVfKHsFG+9OzKPV9KvMttYDbfLw4mbhBKt4XSgXMNX0LsE6g5Wn9FV8Z5uPgX LwlXPoLkfM4rmzSPzSSwhxD2e5TcG308PsodNwk3cIwHLV1J2wFW7x+WHN2y/D6PATsD zs+R5juRIomysSO4/v/vDRqGIc0+fhb9P0FVHCJAm74TyoA6QyZFBGsVVCxYoUNNafDz fshOjzf63gVxNRauimCMLSsmy0U5zP8n3Akxk84ftyGpTnOOf+eq7mH7O8rYZyVhyACw 6dSA== X-Gm-Message-State: AElRT7FII3FcvlpeTq12yjpiZcXQeLUc+L6xjbTbStsSY02L5KeXtwdT UskpDAEGAchf9KkGMD40Fc+pIQ== X-Google-Smtp-Source: AG47ELtNvm40RF7fMlWQeX+YhQ82PDeM4JrfzF1l5a2wHBbKdUMM5WXtQirlqcTRZxfhvgTlSq3hjg== X-Received: by 10.101.83.194 with SMTP id z2mr14108494pgr.133.1522143015330; Tue, 27 Mar 2018 02:30:15 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:14 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:04 +0800 Message-Id: <1522142971-20739-11-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: David Wu Subject: [U-Boot] [PATCH 10/36] rockchip: rk322x: prepare to use common board file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Move soc spec setting into rk322x.c and remove rk322x-board/board-spl.c Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/rk322x-board.c | 155 --------------------- arch/arm/mach-rockchip/rk322x/Makefile | 2 +- .../{rk322x-board-spl.c => rk322x/rk322x.c} | 86 ++++-------- 3 files changed, 29 insertions(+), 214 deletions(-) delete mode 100644 arch/arm/mach-rockchip/rk322x-board.c rename arch/arm/mach-rockchip/{rk322x-board-spl.c => rk322x/rk322x.c} (51%) diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c deleted file mode 100644 index 8642a90..0000000 --- a/arch/arm/mach-rockchip/rk322x-board.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -__weak int rk_board_late_init(void) -{ - return 0; -} - -int board_late_init(void) -{ - setup_boot_mode(); - - return rk_board_late_init(); -} - -int board_init(void) -{ -#include - /* Enable early UART2 channel 1 on the RK322x */ -#define GRF_BASE 0x11000000 - struct rk322x_grf * const grf = (void *)GRF_BASE; - enum { - GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, - GPIO1B2_GPIO = 0, - GPIO1B2_UART21_SIN, - - GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, - GPIO1B1_GPIO = 0, - GPIO1B1_UART1_SOUT, - GPIO1B1_UART21_SOUT, - }; - enum { - CON_IOMUX_UART2SEL_SHIFT= 8, - CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT, - CON_IOMUX_UART2SEL_2 = 0, - CON_IOMUX_UART2SEL_21, - }; - - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B1_MASK | GPIO1B2_MASK, - GPIO1B2_UART21_SIN << GPIO1B2_SHIFT | - GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT); - /* Set channel C as UART2 input */ - rk_clrsetreg(&grf->con_iomux, - CON_IOMUX_UART2SEL_MASK, - CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); - - /* - * The integrated macphy is enabled by default, disable it - * for saving power consuming. - */ - rk_clrsetreg(&grf->macphy_con[0], - MACPHY_CFG_ENABLE_MASK, - 0 << MACPHY_CFG_ENABLE_SHIFT); - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x8400000; - /* Reserve 0x200000 for OPTEE */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE - + gd->bd->bi_dram[0].size + 0x200000; - gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start - + gd->ram_size - gd->bd->bi_dram[1].start; - - return 0; -} - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif - -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) -#include -#include - -static struct dwc2_plat_otg_data rk322x_otg_data = { - .rx_fifo_sz = 512, - .np_tx_fifo_sz = 16, - .tx_fifo_sz = 128, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node; - const char *mode; - bool matched = false; - const void *blob = gd->fdt_blob; - - /* find the usb_otg node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3288-usb"); - - while (node > 0) { - mode = fdt_getprop(blob, node, "dr_mode", NULL); - if (mode && strcmp(mode, "otg") == 0) { - matched = true; - break; - } - - node = fdt_node_offset_by_compatible(blob, node, - "rockchip,rk3288-usb"); - } - if (!matched) { - debug("Not found usb_otg device\n"); - return -ENODEV; - } - rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - - return dwc2_udc_probe(&rk322x_otg_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} -#endif - -#if defined(CONFIG_USB_FUNCTION_FASTBOOT) -int fb_set_reboot_flag(void) -{ - struct rk322x_grf *grf; - - printf("Setting reboot to fastboot flag ...\n"); - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - /* Set boot mode to fastboot */ - writel(BOOT_FASTBOOT, &grf->os_reg[0]); - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk322x/Makefile b/arch/arm/mach-rockchip/rk322x/Makefile index ecb3e8d..89b0fed 100644 --- a/arch/arm/mach-rockchip/rk322x/Makefile +++ b/arch/arm/mach-rockchip/rk322x/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # - obj-y += clk_rk322x.o +obj-y += rk322x.o obj-y += syscon_rk322x.o diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x/rk322x.c similarity index 51% rename from arch/arm/mach-rockchip/rk322x-board-spl.c rename to arch/arm/mach-rockchip/rk322x/rk322x.c index 206abfa..98b6ec3 100644 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ b/arch/arm/mach-rockchip/rk322x/rk322x.c @@ -1,32 +1,41 @@ /* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * Copyright (c) 2017 Rockchip Electronics Co., Ltd * * SPDX-License-Identifier: GPL-2.0+ */ - -#include -#include -#include -#include -#include #include #include -#include -#include #include -#include -#include +#include -u32 spl_boot_device(void) +#define GRF_BASE 0x11000000 +#define CRU_MISC_CON 0x110e0134 +#define SGRF_DDR_CON0 0x10150000 + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000", + [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000", +}; + +#ifdef CONFIG_SPL_BUILD +int arch_cpu_init(void) { - return BOOT_DEVICE_MMC1; -} -DECLARE_GLOBAL_DATA_PTR; + static struct rk322x_grf * const grf = (void *)GRF_BASE; + /* We do some SoC one time setting here. */ -#define GRF_BASE 0x11000000 -#define SGRF_BASE 0x10140000 + /* Disable the ddr secure region setting to make it non-secure */ + rk_clrreg(SGRF_DDR_CON0, 0x4000); + + /* + * The integrated macphy is enabled by default, disable it + * for saving power consuming. + */ + rk_clrsetreg(&grf->macphy_con[0], MACPHY_CFG_ENABLE_MASK, + 0 << MACPHY_CFG_ENABLE_SHIFT); -#define DEBUG_UART_BASE 0x11030000 + return 0; +} +#endif void board_debug_uart_init(void) { @@ -34,8 +43,7 @@ void board_debug_uart_init(void) enum { GPIO1B2_SHIFT = 4, GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, - GPIO1B2_GPIO = 0, - GPIO1B2_UART1_SIN, + GPIO1B2_GPIO = 0, GPIO1B2_UART21_SIN, GPIO1B1_SHIFT = 2, @@ -61,41 +69,3 @@ void board_debug_uart_init(void) CON_IOMUX_UART2SEL_MASK, CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); } - -#define SGRF_DDR_CON0 0x10150000 -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - printascii("SPL Init"); - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - rockchip_timer_init(); - printf("timer init done\n"); - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - printf("DRAM init failed: %d\n", ret); - return; - } - - /* Disable the ddr secure region setting to make it non-secure */ - rk_clrreg(SGRF_DDR_CON0, 0x4000); -#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif -} From patchwork Tue Mar 27 09:29:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891466 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="GlA3tWWl"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409Qvc1K0nz9s1S for ; Tue, 27 Mar 2018 20:39:24 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BE314C21FB1; Tue, 27 Mar 2018 09:36:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 56AA4C21F05; Tue, 27 Mar 2018 09:31:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 680ADC21FE1; Tue, 27 Mar 2018 09:30:24 +0000 (UTC) Received: from mail-pg0-f66.google.com (mail-pg0-f66.google.com [74.125.83.66]) by lists.denx.de (Postfix) with ESMTPS id B3BCCC21FBA for ; Tue, 27 Mar 2018 09:30:19 +0000 (UTC) Received: by mail-pg0-f66.google.com with SMTP id t12so6569086pgp.13 for ; Tue, 27 Mar 2018 02:30:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=H9ClGNpREbalac2KhCEB2S51kM35xZuk8WaceRzS+z8=; b=GlA3tWWl7qkqQLB4+7KXc72l1Lyk3zmg8EUT6xtcPMtXYUOKUEbLHVPpwe9BWrtItL hwIJq4Vqq7nJxIXbn2UEdQ4yquU780o+MhrJeoJRV4qYgZAimbuxqLAj9OwuFlC1YxTX 0Gs8gjG1YAMEo3Zj+mit+9/DJdW0a6DV7u7/QhiuSIcgRoOCMbq1vBSHr0Oyr6sTnL3Z J7a3ehztnnKsW0ZhXVgILao+DpNfgN4Lr0g8WIACtLQ8Q24SMzqUK3YIMIF4ICqP8N3k U3BB5SB6WrtRLh6ihFWrz8iHRrFKD7x4VX+l3d6EytT8h37TmcuTmnMamJAkyimLTt5s yKAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=H9ClGNpREbalac2KhCEB2S51kM35xZuk8WaceRzS+z8=; b=KBGnek4GJ4QKjCGDTQ5CEKYufAx05xkL7pA7hZjNZMl63IvG6ya4mCAYVfm8SbSQCi BcThGY+25BrzusEvqZ7bHaz7DTRKrMhT45mjJ/vtSJWAdeukC0cEbBnrkhpuFrIM7gsJ e16D4PvtciBF0dzUphH92lu2gJ8V1gCVRJTUBz4/Q6OUOdtDl/I4lr6416CwBt2XBCyV rXKPI4c7PeeTMNE3azevyYMP3seyGJJgfpGt9CcTUT7eY8P9f0OXGVeCRQoAm1PH/ftv 1+lU5K82yhkmRM7IxDKIWLcOsHYqMgbBTeA1UFxrxEcZGF0UGF0Lvs/LY4Ve3ZE9p20G iYdg== X-Gm-Message-State: AElRT7GUT/HaKYHR+kwRfaA+maghfItYIZyyOqCFz0VrqThc9IbidyOu HHk0mQek0j77GOXlDbcmyBzGdg== X-Google-Smtp-Source: AG47ELtbx+EYV3qGb/W1gO5LWqQykzyn5RVAMSnN7TzC4dFtOjjcCSjmlU9mjPF481dI8C+SXAjAPA== X-Received: by 10.98.225.9 with SMTP id q9mr24266249pfh.23.1522143017911; Tue, 27 Mar 2018 02:30:17 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:16 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:05 +0800 Message-Id: <1522142971-20739-12-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 11/36] rockchip: defconfig enable sysreset for rk3229 spl X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We need CONFIG_SPL_DRIVERS_MISC_SUPPORT to enable sysreset driver, which will fix missing do_reset() error in SPL build. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- configs/evb-rk3229_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 96afda8..4f1007a 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_ROCKCHIP_RK322X=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_EVB_RK3229=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb" CONFIG_DEBUG_UART=y From patchwork Tue Mar 27 09:29:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891465 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QyOFMsLk"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409Qsj3xd4z9s1c for ; Tue, 27 Mar 2018 20:37:45 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2AAD4C21FC9; Tue, 27 Mar 2018 09:36:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6606FC21FF4; Tue, 27 Mar 2018 09:31:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1CCDEC21FFD; Tue, 27 Mar 2018 09:30:27 +0000 (UTC) Received: from mail-pg0-f66.google.com (mail-pg0-f66.google.com [74.125.83.66]) by lists.denx.de (Postfix) with ESMTPS id 8BA98C21F9B for ; Tue, 27 Mar 2018 09:30:22 +0000 (UTC) Received: by mail-pg0-f66.google.com with SMTP id y63so5210713pgy.12 for ; Tue, 27 Mar 2018 02:30:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=00nVhRlzm2oky9s3bdgptEMAshGkT57Ua/qSga6Voos=; b=QyOFMsLkyhcjf/r+h1j3oWM4HVpRDSQ+7XF8pyPI0MMskHubx3t/sikqX1sfcZ7JsK mT3hnbVVKBThqzbc4LZaQMLrzN/6jb7KJaSmmiWdrKJ7L4fsgoeI+cQNBue/Bdnggcfq 2/2UO2a3Gc1CxGksmHn34dGXzMWZofqml84+X7Zzdt5Ec6pkydM9QKrJGEIkXYaha939 6s4dHGVX1CC6NLk+BlIFKI2UJ+0vOg/bmAKDdTG+SFdQ5x3MRL14GbAZaM+46iyTSUGE icZ0i3BcmZx27UczVYtgtigQuUZMf03Ucm3xOrmJPN3E/8l0ISVA5RACdQAWCkqsOZEl vvuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=00nVhRlzm2oky9s3bdgptEMAshGkT57Ua/qSga6Voos=; b=dQFd6XijYmtruRncqVLp64/mjrPhFQKsLVsarszSHbTVl+iU9Hofy7yZSayLEoYqI7 pZ/naxp29ioXHg4WxdYik0Z1vg4j6zJAmRZR7AjDSInZZn/d9iHhRoJ5KJTx6L4Vxe0z bCH1sGl7Ql5Q1WwTP4f83kqL7NfuKDbEYQRjc9sTydg9pUaAJKSu6pQLWfXfe9nq5Kv7 O3fxrHzMOyR+VQtq51vcbJOOsDOyCYWtu+CiKhiG1x4+VA82Kaio2NUiofHe28Td6/YZ PT0DgvZ/0crPo3QA8XIBP7El9g2sVWhGg0MC4bIYLOmQShwqS+5O3V6mYOkfxffsCzhj tdNQ== X-Gm-Message-State: AElRT7EZtorxlwsJqbpOYwtgTUOMCpVBq7Xprvg9G+W6pmCcGhp1zHZf OccANQomDVrkIl5gdnYGRzDnmg== X-Google-Smtp-Source: AG47ELtZ2knp0A5fPujtD2vMFaeZ/hkAN/HltsLyFbtYfVheCgVqwAldfZ2jwc5Jy6jYSinBxssffQ== X-Received: by 10.98.171.7 with SMTP id p7mr22360317pff.215.1522143020680; Tue, 27 Mar 2018 02:30:20 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:19 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:06 +0800 Message-Id: <1522142971-20739-13-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 12/36] rockchip: rk3036: sdram: use udelay instead of rockchip_udelay X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We are going to remove rockchip_udelay after enable arch timer. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index e5393ec..ce3f09a 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -10,7 +10,6 @@ #include #include #include -#include #include /* @@ -346,7 +345,7 @@ static void rkdclk_init(struct rk3036_sdram_priv *priv) /* waiting for pll lock */ while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) - rockchip_udelay(1); + udelay(1); /* PLL enter normal-mode */ rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, @@ -374,25 +373,25 @@ void phy_pctrl_reset(struct rk3036_sdram_priv *priv) 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); clrsetbits_le32(&ddr_phy->ddrphy_reg1, SOFT_RESET_MASK << SOFT_RESET_SHIFT, 0 << SOFT_RESET_SHIFT); - rockchip_udelay(10); + udelay(10); clrsetbits_le32(&ddr_phy->ddrphy_reg1, SOFT_RESET_MASK << SOFT_RESET_SHIFT, 3 << SOFT_RESET_SHIFT); - rockchip_udelay(1); + udelay(1); } void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq) @@ -445,7 +444,7 @@ static void send_command(struct rk3036_ddr_pctl *pctl, u32 rank, u32 cmd, u32 arg) { writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); - rockchip_udelay(1); + udelay(1); while (readl(&pctl->mcmd) & START_CMD) ; } @@ -455,7 +454,7 @@ static void memory_init(struct rk3036_sdram_priv *priv) struct rk3036_ddr_pctl *pctl = priv->pctl; send_command(pctl, 3, DESELECT_CMD, 0); - rockchip_udelay(1); + udelay(1); send_command(pctl, 3, PREA_CMD, 0); send_command(pctl, 3, MRS_CMD, (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | @@ -493,7 +492,7 @@ static void data_training(struct rk3036_sdram_priv *priv) clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03, DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START); - rockchip_udelay(1); + udelay(1); while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) != (HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) { ; From patchwork Tue Mar 27 09:29:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891464 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="JwqP2Fh8"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409Qrw5RZKz9s1S for ; Tue, 27 Mar 2018 20:37:04 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 55045C21FD9; Tue, 27 Mar 2018 09:35:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id F1D7EC21FDB; Tue, 27 Mar 2018 09:31:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0E1B6C21E26; Tue, 27 Mar 2018 09:30:30 +0000 (UTC) Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by lists.denx.de (Postfix) with ESMTPS id 974ADC21FA5 for ; Tue, 27 Mar 2018 09:30:25 +0000 (UTC) Received: by mail-pf0-f196.google.com with SMTP id q9so1911598pff.1 for ; Tue, 27 Mar 2018 02:30:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=eEwhJ9QpU7BQtER3uc5mGjmNXtNHwbbmOvYunUCx8gs=; b=JwqP2Fh8lwrD62D/RKCapc3zJDE1yKH7x3N97KMJQDdV9fRxRh2TeimeXN27aJ2Qat tc4QfBjDNR8UOSFTNoBohaqoABSzFsdP3GhzHDJywaUm9f9b7CYKOE6DGBcWKuJxmMNH vKRDYDRPhwDyiGKslEZyu2unSqOYiH6B+bHK10Ikim0rkqXcGYaFNaGvk6tFG5tFsXCW vyeUo8vRz3tkyr7ENZj4E1iZeAOiiD0XRoeOg3z2f244pVEIar7c/7BQpNRrXH2nDsUz T8wJGE4SgR+/r5sNur20P95WeKQJQsI8XOHhEY8jUqd2d3y0MENz/4JQYtFkKGAHm/uZ tZ1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=eEwhJ9QpU7BQtER3uc5mGjmNXtNHwbbmOvYunUCx8gs=; b=WWo2jriiVG5H7W7B3pNJ44xwyJ6KhB4LQt41qmKxYfAIBYsht0gYyOhhGkiv3N9QVz sqbtyWAtcYY18q5UdYOOEpwimAW7lHl76tP1dJnPWcEkmC1ar3pa+QhUsyFj1kAvRjKB +O/N7y7gfZhNFqKr0/7Ni5uQnZa3gf0RFYkgup+Gd25HgNBmhnmhItAyxesKEw2CaMrC wet1yBgSEiIC8EeNRn6f7AptLyfmvZsVL+jFyE6yF4P/iJVJrBNLsmFIOrTzBfqmhjpL mENES00hwH09gER73Jm+dUoyt0YYT2ZJHDatCtJ38zwhKvd0SV1buY3C86n/Q5jDMESq JRUQ== X-Gm-Message-State: AElRT7GBme1iqo7mRoBBy04P5iC4JRR0Rk1wjpTg4a2kMDTrflr1z4KR zAqtpAo/5foYJ5wU2xwGSoI+6g== X-Google-Smtp-Source: AIpwx48pAAvp1/Ku+sSp2Adfgkt02PmMeXAyBZdrXHyduoWVeLpv9Pc+sV6uXlf9D/OlhuoqrwkemA== X-Received: by 10.98.149.78 with SMTP id p75mr3161623pfd.188.1522143023899; Tue, 27 Mar 2018 02:30:23 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:22 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:07 +0800 Message-Id: <1522142971-20739-14-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: Chris Packham Subject: [U-Boot] [PATCH 13/36] rockchip: rk3036: remove sys timer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use ARM arch timer instead. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- include/configs/rk3036_common.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index c5ec864..8230373 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -14,10 +14,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) - #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 #define CONFIG_SYS_LOAD_ADDR 0x60800800 #define CONFIG_SPL_STACK 0x10081fff From patchwork Tue Mar 27 09:29:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891467 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="p/XTho7D"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409QwL6Lm7z9s1S for ; Tue, 27 Mar 2018 20:40:02 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5E63CC21FA4; Tue, 27 Mar 2018 09:38:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7EE6EC2200D; Tue, 27 Mar 2018 09:31:47 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 64825C2200F; Tue, 27 Mar 2018 09:30:33 +0000 (UTC) Received: from mail-pg0-f67.google.com (mail-pg0-f67.google.com [74.125.83.67]) by lists.denx.de (Postfix) with ESMTPS id E8C3AC21F99 for ; Tue, 27 Mar 2018 09:30:28 +0000 (UTC) Received: by mail-pg0-f67.google.com with SMTP id b9so1201675pgf.6 for ; Tue, 27 Mar 2018 02:30:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=zkHtdzsanG8YC+4+7svQyVLmWP8qt2ntNYrSNagd7E4=; b=p/XTho7DFnMc2dai0Ija9Pzd2NEsbLAeUsTKX9WE82hdrYSSg566jJaBzJW3rBsX8S anipwPC0mVCw/eDldjcYhJfRgCtf2od2FFwIm3xaQP8a9BkfT0tte1j6i/cHNdzyDI5+ Tko0aJZGfJzEJ+457rWiMO0dCMCmk3zF4KlhehDyCRJdsCccegFwO+cM6JrRM4+KB77a FhGnxkvUiAQ8jMXeb6UElGRhCHHaSiZKN0isxLmN0cKmtGzkJqvs/NbHMIrhexF6mHsr XRgqmdtd8s+pNOSBmrwSsw92Af5wr7K+6DVp1zR0Ojh81qZ1SmeLK2PHbeqzSILaUuMY hPTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=zkHtdzsanG8YC+4+7svQyVLmWP8qt2ntNYrSNagd7E4=; b=SSBj8u75nl7+9S/R0TXd05FyuCW9DovzzXZsPn8ZdY0Ir2w670Hiwzg42f2LnLoSM5 sDg4rmcCUYMt1zi5Mou1UEUu+gTdV2vD3iQi9/+tC8SLeDaXguW4H2AQdiNKIk6FFBKT mozKa4Z3EjmUoGVcIAT3fkuBoeQYS5+YnN0avwsq6sMFFm2cHZD38DE6tv6T4DbcAJl2 2Y1b0+4COUGT3GU/PEocIrKm9qMqDbdy4zd63Hiqct4SyILhbDf1xY0DHJ9Fj1cQfw7k Je5EZyZmFu1ZZTfhLWVc8cd8DAz29Z+GY1n6mlqIqD5MasE91awzh4eITYdQiV0UfVhv TRJQ== X-Gm-Message-State: AElRT7Fj8FR5uqnG/ksIAijjxJIjxieyEfeSlSPtXOpdeFWxdzuJcHSn uydGJmC/Q6XrURZ3Dmd1RzCivQ== X-Google-Smtp-Source: AG47ELsuKPWC2gjkBhjvPrs/MSxkWWq+GZSPTn9ZYwpBgSf9Jb+iNVooui765M8k+ePfd/EBCO8C4w== X-Received: by 10.101.66.70 with SMTP id d6mr17186719pgq.234.1522143026783; Tue, 27 Mar 2018 02:30:26 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:25 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:08 +0800 Message-Id: <1522142971-20739-15-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: Andy Yan Subject: [U-Boot] [PATCH 14/36] rockchip: rk3036: prepare to use commong board file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Move some soc spec setting into rk3036.c Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/rk3036-board.c | 104 --------------------- arch/arm/mach-rockchip/rk3036/Makefile | 2 +- .../{rk3036-board-spl.c => rk3036/rk3036.c} | 41 ++------ arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 14 +++ 4 files changed, 24 insertions(+), 137 deletions(-) delete mode 100644 arch/arm/mach-rockchip/rk3036-board.c rename arch/arm/mach-rockchip/{rk3036-board-spl.c => rk3036/rk3036.c} (50%) diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c deleted file mode 100644 index a5d2571..0000000 --- a/arch/arm/mach-rockchip/rk3036-board.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -__weak int rk_board_late_init(void) -{ - return 0; -} - -int board_late_init(void) -{ - setup_boot_mode(); - - return rk_board_late_init(); -} - -int board_init(void) -{ - return 0; -} - -#if !CONFIG_IS_ENABLED(RAM) -/* - * When CONFIG_RAM is enabled, the dram_init() function is implemented - * in sdram_common.c. - */ -int dram_init(void) -{ - gd->ram_size = sdram_size(); - - return 0; -} -#endif - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif - -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) -#include -#include - -static struct dwc2_plat_otg_data rk3036_otg_data = { - .rx_fifo_sz = 512, - .np_tx_fifo_sz = 16, - .tx_fifo_sz = 128, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node; - const char *mode; - bool matched = false; - const void *blob = gd->fdt_blob; - - /* find the usb_otg node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3288-usb"); - - while (node > 0) { - mode = fdt_getprop(blob, node, "dr_mode", NULL); - if (mode && strcmp(mode, "otg") == 0) { - matched = true; - break; - } - - node = fdt_node_offset_by_compatible(blob, node, - "rockchip,rk3288-usb"); - } - if (!matched) { - debug("Not found usb_otg device\n"); - return -ENODEV; - } - rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - - return dwc2_udc_probe(&rk3036_otg_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile index 20d28f7..8a144d1 100644 --- a/arch/arm/mach-rockchip/rk3036/Makefile +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += clk_rk3036.o +obj-y += rk3036.o clk_rk3036.o ifndef CONFIG_SPL_BUILD obj-y += syscon_rk3036.o diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036/rk3036.c similarity index 50% rename from arch/arm/mach-rockchip/rk3036-board-spl.c rename to arch/arm/mach-rockchip/rk3036/rk3036.c index 550e3a1..39cc43b 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036/rk3036.c @@ -1,28 +1,22 @@ /* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * Copyright (c) 2017 Rockchip Electronics Co., Ltd * * SPDX-License-Identifier: GPL-2.0+ */ - -#include -#include #include #include -#include #include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - +#include #define GRF_BASE 0x20008000 -#define DEBUG_UART_BASE 0x20068000 - -void board_init_f(ulong dummy) +#ifdef CONFIG_SPL_BUILD +int arch_cpu_init(void) +{ + return 0; +} +#endif +void board_debug_uart_init(void) { -#ifdef EARLY_DEBUG struct rk3036_grf * const grf = (void *)GRF_BASE; /* * NOTE: sd card and debug uart use same iomux in rk3036, @@ -34,22 +28,5 @@ void board_init_f(ulong dummy) GPIO1C2_MASK << GPIO1C2_SHIFT, GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); - debug_uart_init(); -#endif - rockchip_timer_init(); - sdram_init(); - - /* return to maskrom */ - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -} -/* Place Holders */ -void board_init_r(gd_t *id, ulong dest_addr) -{ - /* - * Function attribute is no-return - * This Function never executes - */ - while (1) - ; } diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index ce3f09a..a4fb3ae 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -11,6 +11,7 @@ #include #include #include +DECLARE_GLOBAL_DATA_PTR; /* * we can not fit the code to access the device tree in SPL @@ -764,3 +765,16 @@ void sdram_init(void) move_to_access_state(&sdram_priv); dram_cfg_rbc(&sdram_priv); } + +#if !CONFIG_IS_ENABLED(RAM) +/* + * When CONFIG_RAM is enabled, the dram_init() function is implemented + * in sdram_common.c. + */ +int dram_init(void) +{ + gd->ram_size = sdram_size(); + + return 0; +} +#endif From patchwork Tue Mar 27 09:29:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891487 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="R6fhwaWV"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R9T1rGbz9s1S for ; Tue, 27 Mar 2018 20:51:25 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id F1ECEC21FEC; Tue, 27 Mar 2018 09:37:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 54998C21F94; Tue, 27 Mar 2018 09:31:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 55735C21F88; Tue, 27 Mar 2018 09:30:34 +0000 (UTC) Received: from mail-pl0-f66.google.com (mail-pl0-f66.google.com [209.85.160.66]) by lists.denx.de (Postfix) with ESMTPS id 1ED72C21FAB for ; Tue, 27 Mar 2018 09:30:31 +0000 (UTC) Received: by mail-pl0-f66.google.com with SMTP id s24-v6so3364509plq.6 for ; Tue, 27 Mar 2018 02:30:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=st5RfuZjatf4QzkTagEaAcie9OsUK3AGdf70nhFv5LI=; b=R6fhwaWVq29GvDOSbhN9PA8XM9PlXA14oBSYpZ2Dni/lYzwdQd0Cf2ALEFl/eRkx4f d5rt8MrCq7H1jU2BmjBr72Ovml4E2QOmHfuSDAHJZZfpZMDykMf8SbGA+4Jai++JWd4M 2PojnmGUlm8X2poKFrvEmbTcH61WwXmB3FZMFsrR+HGs6r9KpZMJNyz7QHHWz/3tbSSY UPhbm3tHmqTlDzoEPHaHz5Qf/11GIGblf0ad5t3K1va09SDXzcXYs0Zkuh/0mhovcQZm mspsMCmJWdKIzfEx349VpXNAtKkmgB3/FRquiQA27MaWo428jzSwRAD0B1RLD6mdA4MY 76cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=st5RfuZjatf4QzkTagEaAcie9OsUK3AGdf70nhFv5LI=; b=ijKxiQGsQn4fq7zHZmNvmE2xj+YutEb/pSE5q44br8hfwYSymQkXuYt+zgB2Ou623Y EUy8OgvzRARsVX4VuI2JPMuAg4tnUfEESdpDHAM+cPaVsccyvKd2ngM3sZ5IkjoaGbeb cbyCM9iOXIm/2ajKNpOxoWssvKfrcx1c1EIPM469qqW1/1Yrqma/LO7MbEcZE0wYq0RR QT9n5d4dH+gefqD08fYBKI8pg+Yra22qsEneZ2F/SQG8tmtLZkwkJkGJfAs/WwlA8Pmk erAsQKxc0PRyI/txD1eGHjkGqiBLwCI4VhWfeOICB/UzcHvVM4dKXmZfE7LMfDyfJdwK T5+w== X-Gm-Message-State: AElRT7HKJ2aNMd3gornxCyVZlbdW/jXXeo9NGmF9FUqLYjYMmgmJk8n4 Ok1KsMJtBxwpGfOVD7jIt7Wf5g== X-Google-Smtp-Source: AG47ELtGHFz9sDwbvTE+wJkIvt4R244UfWVsZnVmtSj3dRO8sv+OAilZkkjFxSAkmnlbgkddv1eD8g== X-Received: by 2002:a17:902:8d87:: with SMTP id v7-v6mr44035262plo.146.1522143029461; Tue, 27 Mar 2018 02:30:29 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:28 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:09 +0800 Message-Id: <1522142971-20739-16-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 15/36] rockchip: declare sdram_init() in common header X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We need a dedicate sdram_init() function for those SoCS not using SPL_FRAMEWORK. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/sys_proto.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h index 3617ac2..7b7e336 100644 --- a/arch/arm/include/asm/arch-rockchip/sys_proto.h +++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h @@ -7,5 +7,8 @@ #ifndef _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H +#ifndef CONFIG_SPL_FRAMEWORK +void sdram_init(void); +#endif #endif /* _ASM_ARCH_SYS_PROTO_H */ From patchwork Tue Mar 27 09:29:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891469 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="YHS2MK0V"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409Qy62Y5lz9s1c for ; Tue, 27 Mar 2018 20:41:34 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id DF059C21F05; Tue, 27 Mar 2018 09:39:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B25EEC21FF3; Tue, 27 Mar 2018 09:32:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 46FF9C21FC4; Tue, 27 Mar 2018 09:30:37 +0000 (UTC) Received: from mail-pl0-f66.google.com (mail-pl0-f66.google.com [209.85.160.66]) by lists.denx.de (Postfix) with ESMTPS id DD682C21FA4 for ; Tue, 27 Mar 2018 09:30:33 +0000 (UTC) Received: by mail-pl0-f66.google.com with SMTP id b7-v6so13749128plr.8 for ; Tue, 27 Mar 2018 02:30:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=ptZ9lGYIT7Rv719jW9+W5s4FfVJk+JUsg9r34nst900=; b=YHS2MK0VX4kDdMvH26+2CVgJgfbhX1YwKYBYKtm8/vYzrt+JydHaIXVma0rRan12lA 2+zMSprJ9ivGg+b/j5ufO3kwNwDx3Tdc40WZbxQ6yE32OOMYXpTC4M9rdXcKxjXyyeEq +LfXrnmat6s2RjrA4PorDqjse4XEKM4/6zozNgk1mdrSHvZYGfCS7nBrQ1Gp0ym+dmBZ dn26q0THRckUiHfGDf5i82LdpCFmW9SBbU/WjXW04YHkK+lSC/dJuZT4il4REklcSpd0 S3jpjIU8fCW3aH7InA+YCaiKb6qOPteC30o+3ab/lrfZwGQwTgUUV6kMm7Di12B6PQrt BoeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=ptZ9lGYIT7Rv719jW9+W5s4FfVJk+JUsg9r34nst900=; b=VsmUshRiJIJ4BfqNiB22ceMCkKeTmnRseROf9ICssGzyEREIi2fcNPx6CzqLQmn3kM g8bAF9p9R3whZJJFa7nN7q966w/aqkzdJ+EFkfM2IDlx/wfK5lYbgLY2SJxxqQK4l8ZL oN10S2x2AeCMoa/DkkRqkztDP8IEa8yzoZJ6R1+GC10WSGwd57rlhf4DeEc1+Lf11kPH 5RjA9hvve107RtHVv+t4PCeBQDRc+C7Oibfm3xA3qj9BhUSsdT9nqWgCyrctRL3sV9n+ 4YNIxhPl3pi42mQ8C+WRymeEWoAIZGftcLPVkcd6PEswbaE0r+zl52TTsIHooFxpVY07 ExUg== X-Gm-Message-State: AElRT7F8YyBf9ktEP7NNRdcX0B1wiJLYyp2nds0S4JH8vRRMgsat+GYa 5veuSvlrV3MAmQYrBD+RzTne1g== X-Google-Smtp-Source: AG47ELuxasguEo1m7P190BuPdS0hZMVd4I5BuzPtjHQ10AdpZcE5UJeXbQh7abvCLrlWaxxA5KBrXw== X-Received: by 2002:a17:902:149:: with SMTP id 67-v6mr44952578plb.296.1522143032188; Tue, 27 Mar 2018 02:30:32 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:31 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:10 +0800 Message-Id: <1522142971-20739-17-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 16/36] rockchip: sdram-common: add api to pass dram info to trust os X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Trust OS decode this info like this: https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/rockchip/common/drivers/parameter/ddr_parameter.c#L19 We have to set a available value, or else we get error info from Trust OS like this: "ERROR: over or zero region, nr=3145987, max=10" Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/sdram_common.h | 4 ++++ arch/arm/mach-rockchip/sdram_common.c | 21 +++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index fec8586..55c6b81 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -55,4 +55,8 @@ size_t rockchip_sdram_size(phys_addr_t reg); /* Called by U-Boot board_init_r for Rockchip SoCs */ int dram_init(void); + +/* Write ddr param to a known place for trustos */ +int rockchip_setup_ddr_param(struct ram_info *info); + #endif diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c index 76dbdc8..3a71f09 100644 --- a/arch/arm/mach-rockchip/sdram_common.c +++ b/arch/arm/mach-rockchip/sdram_common.c @@ -12,6 +12,15 @@ #include DECLARE_GLOBAL_DATA_PTR; +struct ddr_param { + u32 count; + u32 reserved; + u64 bank_addr; + u64 bank_size; +}; + +#define PARAM_DRAM_INFO_OFFSET 0x2000000 + size_t rockchip_sdram_size(phys_addr_t reg) { u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; @@ -81,3 +90,15 @@ ulong board_get_usable_ram_top(ulong total_size) return (gd->ram_top > top) ? top : gd->ram_top; } + +int rockchip_setup_ddr_param(struct ram_info *info) +{ + struct ddr_param *dinfo = (struct ddr_param *)CONFIG_SYS_SDRAM_BASE + + PARAM_DRAM_INFO_OFFSET; + + dinfo->count = 1; + dinfo->bank_addr = info->base; + dinfo->bank_size = info->size; + + return 0; +} From patchwork Tue Mar 27 09:29:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891480 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="sRvKVpRW"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R3q2S5hz9s1l for ; Tue, 27 Mar 2018 20:46:31 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 015D4C21FE2; Tue, 27 Mar 2018 09:37:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 966AAC21F9B; Tue, 27 Mar 2018 09:31:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 75DD2C21F92; Tue, 27 Mar 2018 09:30:41 +0000 (UTC) Received: from mail-pl0-f67.google.com (mail-pl0-f67.google.com [209.85.160.67]) by lists.denx.de (Postfix) with ESMTPS id 8A655C21EF7 for ; Tue, 27 Mar 2018 09:30:36 +0000 (UTC) Received: by mail-pl0-f67.google.com with SMTP id v7-v6so14555plo.4 for ; Tue, 27 Mar 2018 02:30:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=9NxU/zUZ6zOGDd6s1nvzLEsojQQ6fSUx8WZRktT19jg=; b=sRvKVpRWzSNLY11acWCrInwDHHQzUeObuYlqBspSlUZtLIYzz75A3izNnkIMEX0l8E 2xO1jgpVLzVapTs9FYK0W7zpSR99TExo1Lvr5q2Rhis46S90PtoWpZCsgLnkEB6xFpg7 SHgmKL1MYs70XEH8Wv0iA+LoWOTnEvYkid21w+p/VIk7OJpHj/pVFOFIF+pazCbNoEhG pC3BnCSmm0VczUerVdRLKP8AA6udvLWvqE4KSwAe+bw/TByHJGHXmF21qkuyZANQJbAj I3PlDpAot9li/Z2yOym5xpfm2xcnZrTQ388m5uzcdte00dorulO20zbzhRYhMSM3pw4o ohGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=9NxU/zUZ6zOGDd6s1nvzLEsojQQ6fSUx8WZRktT19jg=; b=TxMlDLbfdhgW1QCH8E9SZTiga2kCMUwq3aQVT7kyNYPPaYptRLXWMSYUeKU2CoQBl+ dNtGjHn2yWsHH9jo0CuX1sXduay1BlckpyA7ou95Yx8ICRDMqzu0rQyhyDRFr6CioLwF 6Wxv85XGMJzG8Iud3V0ZLCXnTGBlfxYVFACPOkrICS79xUIUXyfJNXFZxEGIJKi+ygu8 TpyA0uyMUK6N8SclzGVFE5HkpDWhSO2vyIA4Y8hnarFuXGXvZBQZRW+vl/2hkwkdqKV+ vFt748gmvdRc9Y+W3pWdqMll1bFnouAvwSLiQ8qxtpnmVllnpNdFXbQyDwSHOG5mhQIu 4UpQ== X-Gm-Message-State: AElRT7GtB0Zy9OQl8wfiCg2CJzCHFk03UvR1QnleU/QGvK5jj4kymueI ubrF3ZOJHumKARfgEjXUKJWofQ== X-Google-Smtp-Source: AG47ELtDdY217eaQwpJADNetj4vymmMid9+4qyHUbpyDi7IeuWrwlqF61I7v1ujNhwRx9F+HHVRjZw== X-Received: by 2002:a17:902:3225:: with SMTP id y34-v6mr28023543plb.180.1522143034840; Tue, 27 Mar 2018 02:30:34 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:33 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:11 +0800 Message-Id: <1522142971-20739-18-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 17/36] rockchip: sdram_common: add common dram_init_banksize X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" dram_init_banksize() can be common used by all SoCs, move it into sdram_common.c Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/sdram_common.c | 63 ++++++++++++++++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c index 3a71f09..ff86096 100644 --- a/arch/arm/mach-rockchip/sdram_common.c +++ b/arch/arm/mach-rockchip/sdram_common.c @@ -21,13 +21,74 @@ struct ddr_param { #define PARAM_DRAM_INFO_OFFSET 0x2000000 +#define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024) + +struct tos_parameter_t { + u32 version; + u32 checksum; + struct { + char name[8]; + s64 phy_addr; + u32 size; + u32 flags; + } tee_mem; + struct { + char name[8]; + s64 phy_addr; + u32 size; + u32 flags; + } drm_mem; + s64 reserve[8]; +}; + +int dram_init_banksize(void) +{ + size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE), + gd->ram_top); + +#ifdef CONFIG_ARM64 + /* Reserve 0x200000 for ATF bl31 */ + gd->bd->bi_dram[0].start = 0x200000; + gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; +#else +#ifdef CONFIG_SPL_OPTEE + struct tos_parameter_t *tos_parameter; + + tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE + + TRUST_PARAMETER_OFFSET); + + if (tos_parameter->tee_mem.flags == 1) { + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr + - CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr + + tos_parameter->tee_mem.size; + gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start + + top - gd->bd->bi_dram[1].start; + } else { + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x8400000; + /* Reserve 32M for OPTEE with TA */ + gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + + gd->bd->bi_dram[0].size + 0x2000000; + gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start + + top - gd->bd->bi_dram[1].start; + } +#else + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; +#endif +#endif + + return 0; +} + size_t rockchip_sdram_size(phys_addr_t reg) { u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; size_t chipsize_mb = 0; size_t size_mb = 0; u32 ch; - u32 sys_reg = readl(reg); u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK); From patchwork Tue Mar 27 09:29:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891482 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="DiJsGtod"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R4B4g3Fz9s1l for ; Tue, 27 Mar 2018 20:46:50 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 57828C21FC9; Tue, 27 Mar 2018 09:37:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 365A8C21FB0; Tue, 27 Mar 2018 09:31:33 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 825CFC21FC3; Tue, 27 Mar 2018 09:30:44 +0000 (UTC) Received: from mail-pl0-f65.google.com (mail-pl0-f65.google.com [209.85.160.65]) by lists.denx.de (Postfix) with ESMTPS id 841A0C21F79 for ; Tue, 27 Mar 2018 09:30:39 +0000 (UTC) Received: by mail-pl0-f65.google.com with SMTP id x4-v6so13735792pln.7 for ; Tue, 27 Mar 2018 02:30:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=GHORDFb1FFZz1pilu9zTNA449vt5Y7CRU5j1VqBC5Ts=; b=DiJsGtodlnmPowaxV2i1PQ/tNbR0GJZ57+6/Dssd6A+p6g35mJDM68LO3XWu7ysO93 tHFGFhPA9eiPMynj6CR1U3vw0s5+kWQQTp+dtAKYSRAF5fz6iF//o6rXo67TStEIfBb9 pkubOeW9xKHky+eoilzHKSLe4QxxYP2ogIKUlQoXCksrjVGSQDA8Oj/EE9zJjOsWblhh CRoxvAhCTdbM/xwaUCTy8dS4jJ/mh4jT8qbyUUErJiMxfYSXxeRtCNwZyjBPr7YR3yi0 zHe+7K+ll9bFQv8Uidpb4sjDC+mw9LoX901Aob+do0AsXMfDPYaDe8Pb+dZUp7d+qtHB HD6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=GHORDFb1FFZz1pilu9zTNA449vt5Y7CRU5j1VqBC5Ts=; b=gA/+mhbG2HawbcX458Ue9VRAE1s7bw/I/D6f5rq0ikidEWT0DqV8EzrF2wOWnmgFz4 lkwmOm9J416G4MwPuCaA8UqiM39RvpNeOWfYX/cziGU+MITSkbHZK47B68M/raNAUnJG qOeLeLaP9DgiFQMVjohdRdL2KFxfAz9ZdYxXSnWoGKOowUZgDTe2zugNkvQwtyW0XDF5 NqulkSDGUGfz8mqyelMpkI+bCZhW1oeeI4qDeApWLWEc6IEkRk9t/Yn3cge6ogjJmzxD ktN96SFiwTaTHHQjmqggIZ/voHhF7k0JMFebsdH49FhN7Qvpv2Go/eyf2AqVTQDLR1tt UG9g== X-Gm-Message-State: AElRT7E7wHY5mnPoi3hXaUcK8mKqwUk526dqHyuXRDAY9te5LcGBQvKI YPJVNSPerikN1p6Bzy4yWacYIQ== X-Google-Smtp-Source: AG47ELvwO186vUyLYPmoGz7vq5YSwR5vnqJ3+GP1zqcHJ5kE03WnopHKu1oycXVj/d/pyh6ev8aoiw== X-Received: by 2002:a17:902:2d01:: with SMTP id o1-v6mr26417522plb.309.1522143037843; Tue, 27 Mar 2018 02:30:37 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:36 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:12 +0800 Message-Id: <1522142971-20739-19-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: Chris Packham Subject: [U-Boot] [PATCH 18/36] rockchip: rk3188: remove rockchip timer as sys timer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We use ARM arch timer instead. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- include/configs/rk3188_common.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 30c150e..7dddf11 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -17,9 +17,6 @@ #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -#define CONFIG_SYS_TIMER_BASE 0x2000e000 /* TIMER3 */ -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) #define CONFIG_SYS_TIMER_COUNTS_DOWN #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM From patchwork Tue Mar 27 09:29:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891473 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="h0/Cuxw2"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R1v1MgLz9s1c for ; Tue, 27 Mar 2018 20:44:51 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D2362C21F92; Tue, 27 Mar 2018 09:36:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D841DC21FEA; Tue, 27 Mar 2018 09:31:20 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 781F4C21F82; Tue, 27 Mar 2018 09:30:46 +0000 (UTC) Received: from mail-pl0-f66.google.com (mail-pl0-f66.google.com [209.85.160.66]) by lists.denx.de (Postfix) with ESMTPS id 75567C21FB5 for ; Tue, 27 Mar 2018 09:30:42 +0000 (UTC) Received: by mail-pl0-f66.google.com with SMTP id m22-v6so13752297pls.5 for ; Tue, 27 Mar 2018 02:30:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=KrRLslXtTyoKUCYlcO0kNM/QGKwNoOgiQoWOH6VwbIM=; b=h0/Cuxw20llM1eByFUP8CF53bkCnBqKDMw1RIwfqPI87kWPAyxImQvGNKYJZGT78vp 9YmjzX8cXjg7smITNxnYZZQptaUl6oGm9vnKAxFIDfQ2UH/oP8CQIIWJ75qKIKD8VINR QC+rVMPN3dQIk7w/1ttAafzyMzWwTqSWYlLXE+QE5lwzvugrbTaGVGbJlFwSmVZ/aIhZ R3lCwmCFS9ou7dcKnmYxiJgXOd/6fkm1ZaExyYpNuWAUvWPA8x8f1W0glF4of6SGsSVO hidIRj3R2YpnlizykRLC5V4MAUYEk1DxmPV25l3GUpKYPs8VeRMXi8eLfKoW59MuUjip nIpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=KrRLslXtTyoKUCYlcO0kNM/QGKwNoOgiQoWOH6VwbIM=; b=mSV8+yN67YucBTw6OWeBXwMhI7ULEgYZXRQ1qiifGnuIgXw3YhmS++UHhll+lWgqDY zCTE0ZY7PNnf00sGO4nqeb40NrhHe8RvxvLf+mRcbJm2mjPmMsqWVDzL36TC8SbUAGHF Rasnuqu0yskD2E98Vnef1jzi3hBcwVFKVpP3uYneCU8sZArHTy7R33xGKw97XUB+iNGR WWgQm7UoQOXEZaAR3s+CFZeeo3wtMwyQ5UH+PZX6fFAF0raaOPcuCOpmXUkfK1HN4o1S 54Zv/+Otvn79ejRwI8fAMQ8fSdfywytWx3a1LEKcLc1QO+hEbqk3MmCYKvO3iOcfV+e5 Et7w== X-Gm-Message-State: AElRT7G4aqvujTjExKZtYIlKjOn0GSdA0j6Qug+fG88Jv+QI3V2SnE+Q EsoBcShrYCkgYd8vfGwJWyhwCA== X-Google-Smtp-Source: AG47ELuS9JUS7HIX4GBpFpWF1WEscyY/mnTNULayzJ4cQjyu5yUDYTkTL2Bq1UjOdnl5WvggBFrBHg== X-Received: by 2002:a17:902:3124:: with SMTP id w33-v6mr45570438plb.119.1522143040567; Tue, 27 Mar 2018 02:30:40 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:39 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:13 +0800 Message-Id: <1522142971-20739-20-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 19/36] rockchip: rk3188: prepare to use common board file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Move SoC spec setting into rk3188.c Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/rk3188-board-spl.c | 226 ------------------------------ arch/arm/mach-rockchip/rk3188-board.c | 82 ----------- arch/arm/mach-rockchip/rk3188/Makefile | 1 + arch/arm/mach-rockchip/rk3188/rk3188.c | 23 +++ 4 files changed, 24 insertions(+), 308 deletions(-) delete mode 100644 arch/arm/mach-rockchip/rk3188-board-spl.c delete mode 100644 arch/arm/mach-rockchip/rk3188-board.c create mode 100644 arch/arm/mach-rockchip/rk3188/rk3188.c diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c deleted file mode 100644 index 74771d3..0000000 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * (C) Copyright 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -u32 spl_boot_device(void) -{ -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - const void *blob = gd->fdt_blob; - struct udevice *dev; - const char *bootdev; - int node; - int ret; - - bootdev = fdtdec_get_config_string(blob, "u-boot,boot0"); - debug("Boot device %s\n", bootdev); - if (!bootdev) - goto fallback; - - node = fdt_path_offset(blob, bootdev); - if (node < 0) { - debug("node=%d\n", node); - goto fallback; - } - ret = device_get_global_by_of_offset(node, &dev); - if (ret) { - debug("device at node %s/%d not found: %d\n", bootdev, node, - ret); - goto fallback; - } - debug("Found device %s\n", dev->name); - switch (device_get_uclass_id(dev)) { - case UCLASS_SPI_FLASH: - return BOOT_DEVICE_SPI; - case UCLASS_MMC: - return BOOT_DEVICE_MMC1; - default: - debug("Booting from device uclass '%s' not supported\n", - dev_get_uclass_name(dev)); - } - -fallback: -#endif - return BOOT_DEVICE_MMC1; -} - -static int setup_arm_clock(void) -{ - struct udevice *dev; - struct clk clk; - int ret; - - ret = rockchip_get_clk(&dev); - if (ret) - return ret; - - clk.id = CLK_ARM; - ret = clk_request(dev, &clk); - if (ret < 0) - return ret; - - ret = clk_set_rate(&clk, 600000000); - - clk_free(&clk); - return ret; -} - -void board_init_f(ulong dummy) -{ - struct udevice *pinctrl, *dev; - int ret; - - /* Example code showing how to enable the debug UART on RK3188 */ -#ifdef EARLY_UART -#include - /* Enable early UART on the RK3188 */ -#define GRF_BASE 0x20008000 - struct rk3188_grf * const grf = (void *)GRF_BASE; - - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B1_MASK << GPIO1B1_SHIFT | - GPIO1B0_MASK << GPIO1B0_SHIFT, - GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | - GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - printch('s'); - printch('p'); - printch('l'); - printch('\n'); -#endif - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - rockchip_timer_init(); - - ret = rockchip_get_clk(&dev); - if (ret) { - debug("CLK init failed: %d\n", ret); - return; - } - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("Pinctrl init failed: %d\n", ret); - return; - } - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } - - setup_arm_clock(); -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif -} - -static int setup_led(void) -{ -#ifdef CONFIG_SPL_LED - struct udevice *dev; - char *led_name; - int ret; - - led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); - if (!led_name) - return 0; - ret = led_get_by_label(led_name, &dev); - if (ret) { - debug("%s: get=%d\n", __func__, ret); - return ret; - } - ret = led_set_on(dev, 1); - if (ret) - return ret; -#endif - - return 0; -} - -void spl_board_init(void) -{ - struct udevice *pinctrl; - int ret; - - ret = setup_led(); - if (ret) { - debug("LED ret=%d\n", ret); - hang(); - } - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - -#ifdef CONFIG_SPL_MMC_SUPPORT - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); - if (ret) { - debug("%s: Failed to set up SD card\n", __func__); - goto err; - } -#endif - - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - goto err; - } - - preloader_console_init(); -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif - return; - -err: - printf("spl_board_init: Error %d\n", ret); - - /* No way to report error here */ - hang(); -} diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c deleted file mode 100644 index 916d18f..0000000 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_late_init(void) -{ - struct rk3188_grf *grf; - - setup_boot_mode(); - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - if (IS_ERR(grf)) { - pr_err("grf syscon returned %ld\n", PTR_ERR(grf)); - } else { - /* enable noc remap to mimic legacy loaders */ - rk_clrsetreg(&grf->soc_con0, - NOC_REMAP_MASK << NOC_REMAP_SHIFT, - NOC_REMAP_MASK << NOC_REMAP_SHIFT); - } - - return 0; -} - -int board_init(void) -{ -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - struct udevice *pinctrl; - int ret; - - /* - * We need to implement sdcard iomux here for the further - * initialization, otherwise, it'll hit sdcard command sending - * timeout exception. - */ - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); - if (ret) { - debug("%s: Failed to set up SD card\n", __func__); - goto err; - } - - return 0; -err: - printf("board_init: Error %d\n", ret); - - /* No way to report error here */ - hang(); - - return -1; -#else - return 0; -#endif -} - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif diff --git a/arch/arm/mach-rockchip/rk3188/Makefile b/arch/arm/mach-rockchip/rk3188/Makefile index 7fa0104..b3b2315 100644 --- a/arch/arm/mach-rockchip/rk3188/Makefile +++ b/arch/arm/mach-rockchip/rk3188/Makefile @@ -5,6 +5,7 @@ # ifndef CONFIG_TPL_BUILD +obj-y += rk3188.o obj-y += clk_rk3188.o obj-y += syscon_rk3188.o endif diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c new file mode 100644 index 0000000..57d2abf --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define GRF_BASE 0x20008000 +void board_debug_uart_init(void) +{ + struct rk3188_grf * const grf = (void *)GRF_BASE; + + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK << GPIO1B1_SHIFT | + GPIO1B0_MASK << GPIO1B0_SHIFT, + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); +} From patchwork Tue Mar 27 09:29:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891474 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="mTKhvwac"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R2440h6z9s1c for ; Tue, 27 Mar 2018 20:45:00 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id CAF8CC21F90; Tue, 27 Mar 2018 09:35:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2E10AC21FD5; Tue, 27 Mar 2018 09:31:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AAD88C21FC9; Tue, 27 Mar 2018 09:30:49 +0000 (UTC) Received: from mail-pl0-f66.google.com (mail-pl0-f66.google.com [209.85.160.66]) by lists.denx.de (Postfix) with ESMTPS id 49B64C21FAE for ; Tue, 27 Mar 2018 09:30:45 +0000 (UTC) Received: by mail-pl0-f66.google.com with SMTP id m22-v6so13752357pls.5 for ; Tue, 27 Mar 2018 02:30:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=YlacZgGmRDOQ00qdPSEbRPwR7UZ1xVAHhy6nD1FiwZs=; b=mTKhvwachpyLT657ZUiqD53Epb7yj2475OCQFS6gyM80tCeoo+7p2n0QWhKM2Uv1g5 3spuXICQD1XBagc/+SB42hKR150YUohvp3l/v/i8197JisOn+D5c1FCp1TtLYYPaBetu MqANJEqfTRO7yQiNvZ8cGI8FQvCA82IH64PBzGhIvfCsy9KX7fiS6vhETo8V1ETssKG9 5HT6nPY/3LHmHrbc/Mm8T8bs/VnodgENIx2hfyYBCF0ms4DhM5gvCdoh0bw3k2mf+dWo xKU2laFWzDeB0t3Bp4VaKrn3hl66tqhMMnJ+y4LjoGOO4G201mlM5b0mF1f1hoqbwd04 KLLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=YlacZgGmRDOQ00qdPSEbRPwR7UZ1xVAHhy6nD1FiwZs=; b=PwcUWB3MfPssF3XUYiF6Snei1qMWT4YV1PPIIuLNQxOAOoV2mMynoACNhM+53yOb07 qidss51Z+URy6F9JVVGGchNpc0E2LR68rx4e51+o2ZouK54A4tIoogTDSphnO4h7Og6w /UEFEM1G95uZEFmnPvBf1nCz2uTVGETRE7csXqmorWTfZs+1xqRydxeruuTKagziaoJi B0WhtIC89fYywC624pxxPzf5AO6Dy4DW/nhBxx+Ytd8NHodM6XSuEWuhXyQqlm4C907t uvMNAUMfDvzvfMeJGcjotHEI9ANJEsZyDW0w5ol3PpXhhmwqdFjVpN4IbK+6nOLYbsbA S06Q== X-Gm-Message-State: AElRT7FE6z514kFtrx01DDuadUIvKkJGWsksqEt/J385HocPiHCpuSos yN2IJ9y5ZdpTUuGe/67o1vEszw== X-Google-Smtp-Source: AG47ELszehIwdfbRSmjhJv/7DypBNHACPqUItEga8RBXtkR6RFhAp0eVVVkpToQcr+dq6pXx31AK9w== X-Received: by 2002:a17:902:d81:: with SMTP id 1-v6mr43237230plv.324.1522143043585; Tue, 27 Mar 2018 02:30:43 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:42 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:14 +0800 Message-Id: <1522142971-20739-21-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: Chris Packham Subject: [U-Boot] [PATCH 20/36] rockchip: rk3128: remove rockchip timer as systimer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We use ARM arch timer instead. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- include/configs/rk3128_common.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index c593f18..313a1e2 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -15,10 +15,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) - #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 #define CONFIG_SYS_LOAD_ADDR 0x60800800 From patchwork Tue Mar 27 09:29:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891471 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Y+kSBNzx"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R1L0bynz9s1c for ; Tue, 27 Mar 2018 20:44:22 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 66BF9C21FA0; Tue, 27 Mar 2018 09:39:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3A10FC21FE3; Tue, 27 Mar 2018 09:32:21 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2736AC21F92; Tue, 27 Mar 2018 09:30:52 +0000 (UTC) Received: from mail-pl0-f68.google.com (mail-pl0-f68.google.com [209.85.160.68]) by lists.denx.de (Postfix) with ESMTPS id 15E36C21FBC for ; Tue, 27 Mar 2018 09:30:48 +0000 (UTC) Received: by mail-pl0-f68.google.com with SMTP id s24-v6so3364849plq.6 for ; Tue, 27 Mar 2018 02:30:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=Vupm+PV/xR/LVaAL8WcN01vySBNvH5VltZKWdWlBUO8=; b=Y+kSBNzxf8JxZCfdkHkdsmcs1FgWBsDf5UJoQvC+LNScXWXG4c5axP5M1bRsdCADub QUJSzfB8uKntnlLSD+ZxOqSk0OqWrL29aLnG/UHKHOVn6sj5oiUW8tvYdWIIWK8CZ1od +coI84zcJMGeStRdd5YdoXSbgooiJ7q/xaIY6bLHNUWUM+mLXf0qZtbJHqMh+boYLXVA RdMaogUy5HoPcearQV+JzF4N84nujFEXzrliScwzK0WdIYtwDhioUjN9MxUNdies1Ino e1oaqebNk8ib2N/EEKfrJ8odzmtckdamyT2JtT0lycFKD3dF9C2Lvdxf3Moie/eCc8v0 pEtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=Vupm+PV/xR/LVaAL8WcN01vySBNvH5VltZKWdWlBUO8=; b=VyNLU0EljXthFFJDf8FsyJ2KxZ9bmKi1IHIjvZOrBZ4RKAVZYM0nFMAw1iZGML2/sn ODoKykky7gUjSD0hzFXd1qS2Du/Fkjh7ncMIXd/7lERxaC0gMbWahVyhJr/BYkAKvO+p EH51KwjCEJiRiUkm/xK7v2rd0BdiR1enZAXQwru+U8jTMqjrD9jk+pKn7g98HSug0RB+ BhHwAvSpnZNWro3nlnbOLZFKSK6OakNdkYr3LkrkGQvJJHAsCrUsmhMWVZFImI62Qry7 Di5B0HPJPSBobzoapdF1UVqDx0C7FRrzB+ldrPTP1jP/AxH62HzIMCAwdl6HrZ5rFo6B COWg== X-Gm-Message-State: AElRT7G74DWFJCrcssSj73IzUD9nG/cqQCWMLIWR2w41K7PQbZvvPQ3Y EaTPPVTbqao1aOlU+k9KWtj9Bw== X-Google-Smtp-Source: AIpwx48nFlw6Jv8pFFBv8rlfSuv8lT7bB+rdSlpbuXXn4UwPehlv4ZC/nqxA72+/KeuURFjP0UAeVQ== X-Received: by 2002:a17:902:6e8c:: with SMTP id v12-v6mr4559493plk.24.1522143046284; Tue, 27 Mar 2018 02:30:46 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:45 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:15 +0800 Message-Id: <1522142971-20739-22-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 21/36] rockchip: rk3128: prepare use common board file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" remoe rk3128 board file and move SoC spec setting into rk3128.c Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/rk3128-board.c | 127 ---------------------------------- 1 file changed, 127 deletions(-) delete mode 100644 arch/arm/mach-rockchip/rk3128-board.c diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c deleted file mode 100644 index 2e8393d..0000000 --- a/arch/arm/mach-rockchip/rk3128-board.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -__weak int rk_board_late_init(void) -{ - return 0; -} - -int board_late_init(void) -{ - setup_boot_mode(); - - return rk_board_late_init(); -} - -int board_init(void) -{ - int ret = 0; - - rockchip_timer_init(); - - ret = regulators_enable_boot_on(false); - if (ret) { - debug("%s: Cannot enable boot on regulator\n", __func__); - return ret; - } - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x8400000; - /* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE - + gd->bd->bi_dram[0].size + 0xe00000; - gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start - + gd->ram_size - gd->bd->bi_dram[1].start; - - return 0; -} - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif - -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) -#include -#include - -static struct dwc2_plat_otg_data rk3128_otg_data = { - .rx_fifo_sz = 512, - .np_tx_fifo_sz = 16, - .tx_fifo_sz = 128, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node; - const char *mode; - bool matched = false; - const void *blob = gd->fdt_blob; - - /* find the usb_otg node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3128-usb"); - - while (node > 0) { - mode = fdt_getprop(blob, node, "dr_mode", NULL); - if (mode && strcmp(mode, "otg") == 0) { - matched = true; - break; - } - - node = fdt_node_offset_by_compatible(blob, node, - "rockchip,rk3128-usb"); - } - if (!matched) { - debug("Not found usb_otg device\n"); - return -ENODEV; - } - rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - - return dwc2_udc_probe(&rk3128_otg_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} -#endif - -#if defined(CONFIG_USB_FUNCTION_FASTBOOT) -int fb_set_reboot_flag(void) -{ - struct rk3128_grf *grf; - - printf("Setting reboot to fastboot flag ...\n"); - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - /* Set boot mode to fastboot */ - writel(BOOT_FASTBOOT, &grf->os_reg[0]); - - return 0; -} -#endif From patchwork Tue Mar 27 09:29:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891470 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="f4VHuuVg"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409QyY1FWLz9s1c for ; Tue, 27 Mar 2018 20:41:57 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C2CCFC21F84; Tue, 27 Mar 2018 09:38:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2E568C21FBC; Tue, 27 Mar 2018 09:32:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EADC1C21C4A; Tue, 27 Mar 2018 09:30:54 +0000 (UTC) Received: from mail-pl0-f67.google.com (mail-pl0-f67.google.com [209.85.160.67]) by lists.denx.de (Postfix) with ESMTPS id CAA5AC21FAE for ; Tue, 27 Mar 2018 09:30:50 +0000 (UTC) Received: by mail-pl0-f67.google.com with SMTP id x4-v6so13736018pln.7 for ; Tue, 27 Mar 2018 02:30:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=kgHNzJc+PlS8jqMOMgOOdZqA6Iock/jJm58jNsd5KkI=; b=f4VHuuVg9QyYx95Yr3+Lv9rZtt299CLRIeSjD5wuMkMpK2MOG0t7sGfK9ntCCSUDVM GPo03PXDmJ2ShCLu2rI0WGUIIpYB9BIIQIsb+AF8XsmVDM0YDld8VJMsCwlA25Teb/nQ dSc+AksHdPc81cbLaaVUrAMWOrb4xVJeb6hyVdhga3u8nYJYDq9cWlCvai55+DrL356g 5Dc1MY7ukQLjnHJG5WQiI+KdOtH18GzpcnrGWuL9L2rTJ3D+UrcOTy6QsD7pWMtTwLqK j8efAqOSVeeX/OE/l1eQibeNM0nQLzTL0+N1F3UqLOgHdJBdYIOqH8d1FjP6dU5euRHw TK2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=kgHNzJc+PlS8jqMOMgOOdZqA6Iock/jJm58jNsd5KkI=; b=JfQT138m2QFLIileXllWjxPHm45bt22BQnVjhrjlQamKUhXcgb0UpSN2xHTZ4UzG16 +YBZwnRmurfMjMMeWbtufeobdWxbjWa41CekxEFUvRnWLLSDOTN4j/0OBKfjDbbuefJC o+lqta9xRoq367zxmSzNdsvIekWG6LduucGORAE6W+E8N792OUweHhxiOxRawmum6tVo VCnD88PfRj8HcNio93dQsXdimn1qS+m+l6xx+1jnlvY6HIoUjvlyHUAcF44CCM1UxMOa H4+abjhExEEApDkycP5xf0aCWQJNZxNR9p7mj6IT5cdC9o7fRic/SqMqNgGrWZdLpmsP AaHg== X-Gm-Message-State: AElRT7GVywcP5+bY4pvF+WJbOkYAZGWo+2fngG1IrY2aHJ+Y8gMiIjS+ Rlq9SpWwufsTAvu9qXnnV5xTqw== X-Google-Smtp-Source: AG47ELtU71gGX2b6QnNZSbH1Wcik3tPGcH8wWhMnNk1xTM/FAdD2vIGTqYzIonlBY6UIhe/vzmw+kg== X-Received: by 2002:a17:902:8d87:: with SMTP id v7-v6mr44036549plo.146.1522143049143; Tue, 27 Mar 2018 02:30:49 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:48 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:16 +0800 Message-Id: <1522142971-20739-23-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 22/36] rockchip: dts: rk3288: update spl-boot-order X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use "uboot,spl-boot-orde" instead of "uboot,boot0". Signed-off-by: Kever Yang Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- arch/arm/dts/rk3288-phycore-rdk.dts | 6 +----- arch/arm/dts/rk3288-veyron.dtsi | 6 +----- 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts b/arch/arm/dts/rk3288-phycore-rdk.dts index f2bb7b5..3bf8efb 100644 --- a/arch/arm/dts/rk3288-phycore-rdk.dts +++ b/arch/arm/dts/rk3288-phycore-rdk.dts @@ -53,11 +53,7 @@ chosen { stdout-path = &uart2; - }; - - config { - u-boot,dm-pre-reloc; - u-boot,boot0 = &emmc; + u-boot,spl-boot-order = &emmc; }; user_buttons: user-buttons { diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi index a314058..77b9bf8 100644 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ b/arch/arm/dts/rk3288-veyron.dtsi @@ -17,11 +17,7 @@ chosen { stdout-path = &uart2; - }; - - config { - u-boot,dm-pre-reloc; - u-boot,boot0 = &spi_flash; + u-boot,spl-boot-order = &spi_flash; }; firmware { From patchwork Tue Mar 27 09:29:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891488 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="U+cUZ2JD"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R9V3bPtz9s1b for ; Tue, 27 Mar 2018 20:51:26 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 3F424C21FED; Tue, 27 Mar 2018 09:39:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6039FC21FC3; Tue, 27 Mar 2018 09:32:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B39B6C21FFD; Tue, 27 Mar 2018 09:30:57 +0000 (UTC) Received: from mail-pg0-f65.google.com (mail-pg0-f65.google.com [74.125.83.65]) by lists.denx.de (Postfix) with ESMTPS id E12EEC21F90 for ; Tue, 27 Mar 2018 09:30:53 +0000 (UTC) Received: by mail-pg0-f65.google.com with SMTP id f10so8182496pgs.9 for ; Tue, 27 Mar 2018 02:30:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=4F8YL9qQn/7eFSzLEiFZPW42NJ4y9Qjtczt5nuE4jh4=; b=U+cUZ2JDd3ALvcHo76AerxBNvW5rSx96kAxdxjIGAcUjBKU/dmfJSuzJU86GPHVVxe VDEgdb0lnlOu6u39p7ONvb1qP+ic0n3u6u6INNZuZ3Vop33MJ1um9tgs3tK9Ms9bU+kp /UPGtEdcKnOdu07Y5xBCTskF7ZPdYnwIR5NAio0zvGEKspfmHjyunmd8rsafvx2/RtmF 4zBEb0QnKAnKPiZvqiikoJuXPL9Iz1s837bPkNkd4cVSQduz1geeIq2ZoRmbnzOP1zTY D6q8TdR5TQAGhsx9z6MS03HmlSF+KBh7CTK0565N9vuz6WPxz9NGDHuthLTD1jJ/RSRB LwGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=4F8YL9qQn/7eFSzLEiFZPW42NJ4y9Qjtczt5nuE4jh4=; b=BEr/och/q5mjjwXDaBG4gHgtTqZJCJKaTZ8C3r5eZLeVmavGKtuhGmpEJzeLtj9LY4 zoaIGF4bBtUrJBBTK6HDjaIA2dSWq+/DXBtKy24X4c0UTouFi0BDuv/n5vsiM6BevHoO xyyAOhWDun1NWCYSQS7wcF71Yq6Vbr4+SBUcFG2xD/DGHJS1UE2Fka/JZQZsfFcnBsnt BHehVp3kmVpQCv+Bt103Kn+eb3Lk3ZlcGfWgfxZzqB9fPTztf8x1xkbdUwsXbv7evSg8 3aPinexFOwux9HL+tGEk4ny2sieRwUHgw4AIjlnMSztdPi5i/+CVRfqB7gsNF2k83caH 1b3Q== X-Gm-Message-State: AElRT7G2kY/ARN4y2atsiWmsNoh+cIXB4gflbGwDLhP3SYiaoWQNJhuQ xSR4Mx6J3z2GVMOHd5K6Tc4GlA== X-Google-Smtp-Source: AG47ELsURagLg05gE/n7ayIL2YLbWhkS9AVFw9Q3fP2veN0pXfZ/YaPJK93l6udBe6tD1kTojIM/fQ== X-Received: by 10.99.127.75 with SMTP id p11mr30155553pgn.392.1522143052166; Tue, 27 Mar 2018 02:30:52 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:51 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:17 +0800 Message-Id: <1522142971-20739-24-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: Chris Packham Subject: [U-Boot] [PATCH 23/36] rockchip: rk3288: remove rockchip timer for sys timer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use ARM arch timer instead Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- include/configs/rk3288_common.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 44d5c2a..8d0a0f9 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -15,10 +15,6 @@ #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */ -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) - #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM /* Bootrom will load u-boot binary to 0x0 once return from SPL */ #endif From patchwork Tue Mar 27 09:29:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891499 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Y8+EWzh/"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409RCy1Nndz9s1S for ; Tue, 27 Mar 2018 20:53:34 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C9F6CC21FE2; Tue, 27 Mar 2018 09:40:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2D3D1C22047; Tue, 27 Mar 2018 09:33:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id ACFAAC21F79; Tue, 27 Mar 2018 09:30:59 +0000 (UTC) Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by lists.denx.de (Postfix) with ESMTPS id 5EE57C21FB5 for ; Tue, 27 Mar 2018 09:30:56 +0000 (UTC) Received: by mail-pf0-f196.google.com with SMTP id g14so2117393pfh.3 for ; Tue, 27 Mar 2018 02:30:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=8XTa5VINQPSIiriHHieEHpxHgwaygQH/a006349lCI4=; b=Y8+EWzh/ZyLrGsZwAeUVEPMNqHXKbnBAXkGsvgqz4b5lT3+bsSTktt4Q5Wc0hAmslA Q7l52My3K3GF+FmxxVKmYyAL3C0x0OSJ5lIywJf3IuZAsPVNqEaY0RcDVTYMf+UWZlt8 Ucmj5eTdRUodOUqdDQvjQCVEUeHvN2xK7fFwET13VFbRnFL2lRqcAm3E3/FX4gpw6FwJ xh0GPemk/yICWvHBmxFoTrohZ+CpNlRsG+MUAVYGTQ0WqbdHMrFT679rDSW5dZQ81DqA w80y3O9hrnbrEeI+CTxrpA/Zyj0MZyc8yGXAe7E06uXhYA3OsuwAALNPMJYRrhQYzY6j 1+Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=8XTa5VINQPSIiriHHieEHpxHgwaygQH/a006349lCI4=; b=CIbbs77Djl5Ebl1NvESQZQbXfLHWBrNyZf6QooYETLAVs9BpDlXCQETYYJEdv0FD4x 4sXjnGOzU2RyVeQ1MgujVMwh4x/WNJ63r8uoa5zKMRSLBBdOjHJspV7WY0rZGuehepxz HpAQZftQLuSn+ErbkfcQjNNQNUDAeOzZ3HkOhE42EtQ96Qhsv41SuRRc2ub+K654iHp0 2NCiUvTFe6ZTDui+K0AcQDzfIlaJH6s3SzN9Z2efC2g7jRMYZJ/HHdg0JIJPXd6gs7Ou y0pi8InlvtSNP7zdeHa7NnWfWqDQ5p5IXHqZi3qiXsAR2O0nkwDJ7xkYETSXbtwZkE0s +PVw== X-Gm-Message-State: AElRT7E8JIjo5MWOXBIF7oS4XxWcE4IHiwCFi4bLcAThByTh/7+OaUit 9bm2OTHitEg8Jfv6L5TkbUkGlQ== X-Google-Smtp-Source: AG47ELvDjXVadYbxPLSZ0oP/sWtBq8GufHquRdNzNvtdwGCA/KEHDqKFoGzAM0Q8fsIqf+HuqsHSEQ== X-Received: by 10.99.104.9 with SMTP id d9mr19202901pgc.304.1522143054662; Tue, 27 Mar 2018 02:30:54 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:53 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:18 +0800 Message-Id: <1522142971-20739-25-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 24/36] armv8: add timer_get_boot_us() for generic timer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We need timer_get_boot_us() for boot stage if we use generic timer only. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/cpu/armv8/generic_timer.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c index a2dda33..d96217e 100644 --- a/arch/arm/cpu/armv8/generic_timer.c +++ b/arch/arm/cpu/armv8/generic_timer.c @@ -7,6 +7,7 @@ #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -52,6 +53,11 @@ uint64_t get_ticks(void) return ticks; } +ulong timer_get_boot_us(void) +{ + return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000)); +} + unsigned long usec2ticks(unsigned long usec) { ulong ticks; From patchwork Tue Mar 27 09:29:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891477 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QZ8w6XgH"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R2k714Gz9s1p for ; Tue, 27 Mar 2018 20:45:34 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A3813C21F05; Tue, 27 Mar 2018 09:42:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0E01FC22027; Tue, 27 Mar 2018 09:34:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C1412C2206C; Tue, 27 Mar 2018 09:31:21 +0000 (UTC) Received: from mail-pl0-f65.google.com (mail-pl0-f65.google.com [209.85.160.65]) by lists.denx.de (Postfix) with ESMTPS id 4F261C21FC2 for ; Tue, 27 Mar 2018 09:31:00 +0000 (UTC) Received: by mail-pl0-f65.google.com with SMTP id g20-v6so2467698plo.9 for ; Tue, 27 Mar 2018 02:31:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=wdaIdhgLdxKh+6uYwGOLM2KITatdMb9KLfVygkipp3A=; b=QZ8w6XgHFr8KwCDB1aOkRyjgvNQAWrwQ/D8rNT+Z+L6TfVYYoUflJW8t9VXVCE/UC2 BV0Yza5qS2IEm8fqpiKfCGaNdO1WhPHKaU9PApHrggM+h+978ARQ9lIOPh/cMIRO4YGW K3S10rFXFshsuooM2/516c3KYy8rw7fMM3pBd2pakMbhJ0Brkxg5QfvDgFcjgwJBMNaI kxJvUowRe1jCN27o3X644e3uwoAYuK86SlFVKZqMGvvPSYMvsgcOaQb856Lj+6NCAyTK SayJMHVbLXn+L6qG7/OiV4cviBWf7ohglJgj2aYX+oLHCDbzvVlCVzOkf+yVOF3U50H7 W37g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=wdaIdhgLdxKh+6uYwGOLM2KITatdMb9KLfVygkipp3A=; b=jBEbYApGvdFoffeq8JWKKxk6IfMhTAudNm5aeBA9FT6VDT0tAYwefLAL6od+AyNYnP dA5r/cAvhVMU07B5V5FeMbcqI2YeoicEWkxqpT1XGTBTEW/aRT0DcKNc6SOD8XZdLfme OgtLi11xuXi9L1UjbKvj/CBbCac3BUOBOl6mAJlq6tAkR79JDFL0yxsaw62aozFYZYWF 2mhIP+FkNmAvLiSZNJJ3A/wd5ZAr7QNN0CqmtNRBt9GcnXREk8vcipy9Qfnde7CNHFMs l7/ZYicFYzCyrll3iJAR4UeqKkZbVa+MU1c9mNpeFLXnr2660rz6dCTw+4wzCqgaDCFT jPaA== X-Gm-Message-State: AElRT7G/7vuLr+DkVAzbZkx6Jov2Zjdjnxb4ju++U0OQbyINpt7ht2b3 vwWlWjTHe4ukZWODweegGXPAQQ== X-Google-Smtp-Source: AIpwx4+E/VtyAp90M9j/0JEHEmuC0clqG6qf6MFwmK/BRvfpQFU9WUWObrpBLe9lZmE5gRJj6qrz8g== X-Received: by 2002:a17:902:b7cc:: with SMTP id v12-v6mr4813660plz.237.1522143058032; Tue, 27 Mar 2018 02:30:58 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:57 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:19 +0800 Message-Id: <1522142971-20739-26-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: Jernej Skrabec , Lin Huang Subject: [U-Boot] [PATCH 25/36] rockchip: rk3288: prepare to use common board file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use common board file and move SoC spec setting into rk3288.c Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/rk3288-board-spl.c | 304 ------------------ arch/arm/mach-rockchip/rk3288-board-tpl.c | 84 ----- arch/arm/mach-rockchip/rk3288-board.c | 338 --------------------- arch/arm/mach-rockchip/rk3288/rk3288.c | 304 +++++++++++++++++- board/chipspark/popmetal_rk3288/popmetal-rk3288.c | 9 +- board/mqmaker/miqi_rk3288/miqi-rk3288.c | 7 - board/phytec/phycore_rk3288/phycore-rk3288.c | 45 ++- board/rockchip/evb_rk3288/evb-rk3288.c | 7 - .../rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c | 8 + board/rockchip/fennec_rk3288/fennec-rk3288.c | 7 - board/rockchip/tinker_rk3288/tinker-rk3288.c | 2 +- 11 files changed, 357 insertions(+), 758 deletions(-) delete mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c delete mode 100644 arch/arm/mach-rockchip/rk3288-board-tpl.c delete mode 100644 arch/arm/mach-rockchip/rk3288-board.c create mode 100644 board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c deleted file mode 100644 index f3ea624..0000000 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - * (C) Copyright 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -u32 spl_boot_device(void) -{ -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - const void *blob = gd->fdt_blob; - struct udevice *dev; - const char *bootdev; - int node; - int ret; - - bootdev = fdtdec_get_config_string(blob, "u-boot,boot0"); - debug("Boot device %s\n", bootdev); - if (!bootdev) - goto fallback; - - node = fdt_path_offset(blob, bootdev); - if (node < 0) { - debug("node=%d\n", node); - goto fallback; - } - ret = device_get_global_by_of_offset(node, &dev); - if (ret) { - debug("device at node %s/%d not found: %d\n", bootdev, node, - ret); - goto fallback; - } - debug("Found device %s\n", dev->name); - switch (device_get_uclass_id(dev)) { - case UCLASS_SPI_FLASH: - return BOOT_DEVICE_SPI; - case UCLASS_MMC: - return BOOT_DEVICE_MMC1; - default: - debug("Booting from device uclass '%s' not supported\n", - dev_get_uclass_name(dev)); - } - -fallback: -#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ - defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ - defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) - return BOOT_DEVICE_SPI; -#endif - return BOOT_DEVICE_MMC1; -} - -#ifdef CONFIG_SPL_MMC_SUPPORT -static int configure_emmc(struct udevice *pinctrl) -{ -#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) - - struct gpio_desc desc; - int ret; - - pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC); - - /* - * TODO(sjg@chromium.org): Pick this up from device tree or perhaps - * use the EMMC_PWREN setting. - */ - ret = dm_gpio_lookup_name("D9", &desc); - if (ret) { - debug("gpio ret=%d\n", ret); - return ret; - } - ret = dm_gpio_request(&desc, "emmc_pwren"); - if (ret) { - debug("gpio_request ret=%d\n", ret); - return ret; - } - ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); - if (ret) { - debug("gpio dir ret=%d\n", ret); - return ret; - } - ret = dm_gpio_set_value(&desc, 1); - if (ret) { - debug("gpio value ret=%d\n", ret); - return ret; - } -#endif - return 0; -} -#endif - -#if !defined(CONFIG_SPL_OF_PLATDATA) -static int phycore_init(void) -{ - struct udevice *pmic; - int ret; - - ret = uclass_first_device_err(UCLASS_PMIC, &pmic); - if (ret) - return ret; - -#if defined(CONFIG_SPL_POWER_SUPPORT) - /* Increase USB input current to 2A */ - ret = rk818_spl_configure_usb_input_current(pmic, 2000); - if (ret) - return ret; - - /* Close charger when USB lower then 3.26V */ - ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000); - if (ret) - return ret; -#endif - - return 0; -} -#endif - -void board_init_f(ulong dummy) -{ - struct udevice *pinctrl; - struct udevice *dev; - int ret; - - /* Example code showing how to enable the debug UART on RK3288 */ -#include - /* Enable early UART on the RK3288 */ -#define GRF_BASE 0xff770000 - struct rk3288_grf * const grf = (void *)GRF_BASE; - - rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | - GPIO7C6_MASK << GPIO7C6_SHIFT, - GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | - GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - debug("\nspl:debug uart enabled in %s\n", __func__); - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - rockchip_timer_init(); - configure_l2ctlr(); - - ret = rockchip_get_clk(&dev); - if (ret) { - debug("CLK init failed: %d\n", ret); - return; - } - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("Pinctrl init failed: %d\n", ret); - return; - } - -#if !defined(CONFIG_SPL_OF_PLATDATA) - if (of_machine_is_compatible("phytec,rk3288-phycore-som")) { - ret = phycore_init(); - if (ret) { - debug("Failed to set up phycore power settings: %d\n", - ret); - return; - } - } -#endif - -#if !defined(CONFIG_SUPPORT_TPL) - debug("\nspl:init dram\n"); - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } -#endif - -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif -} - -static int setup_led(void) -{ -#ifdef CONFIG_SPL_LED - struct udevice *dev; - char *led_name; - int ret; - - led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); - if (!led_name) - return 0; - ret = led_get_by_label(led_name, &dev); - if (ret) { - debug("%s: get=%d\n", __func__, ret); - return ret; - } - ret = led_set_on(dev, 1); - if (ret) - return ret; -#endif - - return 0; -} - -void spl_board_init(void) -{ - struct udevice *pinctrl; - int ret; - - ret = setup_led(); - - if (ret) { - debug("LED ret=%d\n", ret); - hang(); - } - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - -#ifdef CONFIG_SPL_MMC_SUPPORT - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); - if (ret) { - debug("%s: Failed to set up SD card\n", __func__); - goto err; - } - ret = configure_emmc(pinctrl); - if (ret) { - debug("%s: Failed to set up eMMC\n", __func__); - goto err; - } -#endif - - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - goto err; - } - - preloader_console_init(); -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif - return; -err: - printf("spl_board_init: Error %d\n", ret); - - /* No way to report error here */ - hang(); -} - -#ifdef CONFIG_SPL_OS_BOOT - -#define PMU_BASE 0xff730000 -int dram_init_banksize(void) -{ - struct rk3288_pmu *const pmu = (void *)PMU_BASE; - size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]); - - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = size; - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk3288-board-tpl.c b/arch/arm/mach-rockchip/rk3288-board-tpl.c deleted file mode 100644 index 150beea..0000000 --- a/arch/arm/mach-rockchip/rk3288-board-tpl.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (C) 2017 Amarula Solutions - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define GRF_BASE 0xff770000 -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - - /* Example code showing how to enable the debug UART on RK3288 */ - /* Enable early UART on the RK3288 */ - struct rk3288_grf * const grf = (void *)GRF_BASE; - - rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | - GPIO7C6_MASK << GPIO7C6_SHIFT, - GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | - GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - rockchip_timer_init(); - configure_l2ctlr(); - - ret = rockchip_get_clk(&dev); - if (ret) { - debug("CLK init failed: %d\n", ret); - return; - } - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } -} - -void board_return_to_bootrom(void) -{ - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_BOOTROM; -} - -void spl_board_init(void) -{ - puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \ - U_BOOT_TIME ")\n"); -} diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c deleted file mode 100644 index 1c53cca..0000000 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ /dev/null @@ -1,338 +0,0 @@ -/* - * (C) Copyright 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -__weak int rk_board_late_init(void) -{ - return 0; -} - -int rk3288_qos_init(void) -{ - int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT; - /* set vop qos to higher priority */ - writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS); - writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS); - - if (!fdt_node_check_compatible(gd->fdt_blob, 0, - "rockchip,rk3288-tinker")) - { - /* set isp qos to higher priority */ - writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS); - writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS); - writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS); - } - return 0; -} - -static void rk3288_detect_reset_reason(void) -{ - struct rk3288_cru *cru = rockchip_get_cru(); - const char *reason; - - if (IS_ERR(cru)) - return; - - switch (cru->cru_glb_rst_st) { - case GLB_POR_RST: - reason = "POR"; - break; - case FST_GLB_RST_ST: - case SND_GLB_RST_ST: - reason = "RST"; - break; - case FST_GLB_TSADC_RST_ST: - case SND_GLB_TSADC_RST_ST: - reason = "THERMAL"; - break; - case FST_GLB_WDT_RST_ST: - case SND_GLB_WDT_RST_ST: - reason = "WDOG"; - break; - default: - reason = "unknown reset"; - } - - env_set("reset_reason", reason); - - /* - * Clear cru_glb_rst_st, so we can determine the last reset cause - * for following resets. - */ - rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); -} - -int board_late_init(void) -{ - setup_boot_mode(); - rk3288_qos_init(); - rk3288_detect_reset_reason(); - - return rk_board_late_init(); -} - -#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) -static int veyron_init(void) -{ - struct udevice *dev; - struct clk clk; - int ret; - - ret = regulator_get_by_platname("vdd_arm", &dev); - if (ret) { - debug("Cannot set regulator name\n"); - return ret; - } - - /* Slowly raise to max CPU voltage to prevent overshoot */ - ret = regulator_set_value(dev, 1200000); - if (ret) - return ret; - udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ - ret = regulator_set_value(dev, 1400000); - if (ret) - return ret; - udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ - - ret = rockchip_get_clk(&clk.dev); - if (ret) - return ret; - clk.id = PLL_APLL; - ret = clk_set_rate(&clk, 1800000000); - if (IS_ERR_VALUE(ret)) - return ret; - - return 0; -} -#endif - -int board_init(void) -{ -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - struct udevice *pinctrl; - int ret; - - /* - * We need to implement sdcard iomux here for the further - * initlization, otherwise, it'll hit sdcard command sending - * timeout exception. - */ - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); - if (ret) { - debug("%s: Failed to set up SD card\n", __func__); - goto err; - } - - return 0; -err: - printf("board_init: Error %d\n", ret); - - /* No way to report error here */ - hang(); - - return -1; -#else - int ret; - - /* We do some SoC one time setting here */ - if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { - ret = veyron_init(); - if (ret) - return ret; - } - - return 0; -#endif -} - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif - -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) -#include -#include - -static struct dwc2_plat_otg_data rk3288_otg_data = { - .rx_fifo_sz = 512, - .np_tx_fifo_sz = 16, - .tx_fifo_sz = 128, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node, phy_node; - const char *mode; - bool matched = false; - const void *blob = gd->fdt_blob; - u32 grf_phy_offset; - - /* find the usb_otg node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3288-usb"); - - while (node > 0) { - mode = fdt_getprop(blob, node, "dr_mode", NULL); - if (mode && strcmp(mode, "otg") == 0) { - matched = true; - break; - } - - node = fdt_node_offset_by_compatible(blob, node, - "rockchip,rk3288-usb"); - } - if (!matched) { - debug("Not found usb_otg device\n"); - return -ENODEV; - } - rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - - node = fdtdec_lookup_phandle(blob, node, "phys"); - if (node <= 0) { - debug("Not found usb phy device\n"); - return -ENODEV; - } - - phy_node = fdt_parent_offset(blob, node); - if (phy_node <= 0) { - debug("Not found usb phy device\n"); - return -ENODEV; - } - - rk3288_otg_data.phy_of_node = phy_node; - grf_phy_offset = fdtdec_get_addr(blob, node, "reg"); - - /* find the grf node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3288-grf"); - if (node <= 0) { - debug("Not found grf device\n"); - return -ENODEV; - } - rk3288_otg_data.regs_phy = grf_phy_offset + - fdtdec_get_addr(blob, node, "reg"); - - return dwc2_udc_probe(&rk3288_otg_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} -#endif - -static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - static const struct { - char *name; - int id; - } clks[] = { - { "osc", CLK_OSC }, - { "apll", CLK_ARM }, - { "dpll", CLK_DDR }, - { "cpll", CLK_CODEC }, - { "gpll", CLK_GENERAL }, -#ifdef CONFIG_ROCKCHIP_RK3036 - { "mpll", CLK_NEW }, -#else - { "npll", CLK_NEW }, -#endif - }; - int ret, i; - struct udevice *dev; - - ret = rockchip_get_clk(&dev); - if (ret) { - printf("clk-uclass not found\n"); - return 0; - } - - for (i = 0; i < ARRAY_SIZE(clks); i++) { - struct clk clk; - ulong rate; - - clk.id = clks[i].id; - ret = clk_request(dev, &clk); - if (ret < 0) - continue; - - rate = clk_get_rate(&clk); - printf("%s: %lu\n", clks[i].name, rate); - - clk_free(&clk); - } - - return 0; -} - -U_BOOT_CMD( - clock, 2, 1, do_clock, - "display information about clocks", - "" -); - -#define GRF_SOC_CON2 0xff77024c - -int board_early_init_f(void) -{ - struct udevice *pinctrl; - struct udevice *dev; - int ret; - - /* - * This init is done in SPL, but when chain-loading U-Boot SPL will - * have been skipped. Allow the clock driver to check if it needs - * setting up. - */ - ret = rockchip_get_clk(&dev); - if (ret) { - debug("CLK init failed: %d\n", ret); - return ret; - } - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - return ret; - } - - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - return ret; - } - rk_setreg(GRF_SOC_CON2, 1 << 0); - - return 0; -} diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 1e1c6be..0212015 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -3,11 +3,30 @@ * * SPDX-License-Identifier: GPL-2.0+ */ +#include +#include +#include #include #include +#include +#include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include -#define GRF_SOC_CON2 0xff77024c +#define GRF_BASE 0xff770000 +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000", + [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000", +}; #ifdef CONFIG_SPL_BUILD static void configure_l2ctlr(void) @@ -36,7 +55,290 @@ int arch_cpu_init(void) #ifdef CONFIG_SPL_BUILD configure_l2ctlr(); #else + struct rk3288_grf * const grf = (void *)GRF_BASE; + /* Use rkpwm by default */ + rk_setreg(&grf->soc_con2, 1 << 0); +#endif + return 0; +} + +void board_debug_uart_init(void) +{ + struct rk3288_grf * const grf = (void *)GRF_BASE; + + rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | + GPIO7C6_MASK << GPIO7C6_SHIFT, + GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | + GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); +} + +#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) +#ifdef CONFIG_SPL_MMC_SUPPORT +static int configure_emmc(void) +{ +#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) + + struct gpio_desc desc; + int ret; + struct udevice *pinctrl; + + pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC); + + /* + * TODO(sjg@chromium.org): Pick this up from device tree or perhaps + * use the EMMC_PWREN setting. + */ + ret = dm_gpio_lookup_name("D9", &desc); + if (ret) { + debug("gpio ret=%d\n", ret); + return ret; + } + ret = dm_gpio_request(&desc, "emmc_pwren"); + if (ret) { + debug("gpio_request ret=%d\n", ret); + return ret; + } + ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + if (ret) { + debug("gpio dir ret=%d\n", ret); + return ret; + } + ret = dm_gpio_set_value(&desc, 1); + if (ret) { + debug("gpio value ret=%d\n", ret); + return ret; + } +#endif + return 0; +} + +int rk_spl_board_init(void) +{ + struct udevice *pinctrl; + int ret = 0; + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + goto err; + } + /* TODO: we may need to check boot device first */ +#ifdef CONFIG_SPL_MMC_SUPPORT + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); + if (ret) { + debug("%s: Failed to set up SD card\n", __func__); + goto err; + } +#endif + + ret = configure_emmc(); + if (ret) + debug("%s: Failed to set up eMMC\n", __func__); + +err: + return ret; +} +#endif +#endif + +int rk3288_qos_init(void) +{ + int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT; + /* set vop qos to higher priority */ + writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS); + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS); + + if (!fdt_node_check_compatible(gd->fdt_blob, 0, + "rockchip,rk3288-tinker")) { + /* set isp qos to higher priority */ + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS); + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS); + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS); + } + return 0; +} + +static void rk3288_detect_reset_reason(void) +{ + struct rk3288_cru *cru = rockchip_get_cru(); + const char *reason; + + if (IS_ERR(cru)) + return; + + switch (cru->cru_glb_rst_st) { + case GLB_POR_RST: + reason = "POR"; + break; + case FST_GLB_RST_ST: + case SND_GLB_RST_ST: + reason = "RST"; + break; + case FST_GLB_TSADC_RST_ST: + case SND_GLB_TSADC_RST_ST: + reason = "THERMAL"; + break; + case FST_GLB_WDT_RST_ST: + case SND_GLB_WDT_RST_ST: + reason = "WDOG"; + break; + default: + reason = "unknown reset"; + } + + env_set("reset_reason", reason); + + /* + * Clear cru_glb_rst_st, so we can determine the last reset cause + * for following resets. + */ + rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); +} + +__weak int rk3288_board_late_init(void) +{ + return 0; +} + +int rk_board_late_init(void) +{ + rk3288_qos_init(); + rk3288_detect_reset_reason(); + + return rk3288_board_late_init(); +} + +#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) +static int veyron_init(void) +{ + struct udevice *dev; + struct clk clk; + int ret; + + ret = regulator_get_by_platname("vdd_arm", &dev); + if (ret) { + debug("Cannot set regulator name\n"); + return ret; + } + + /* Slowly raise to max CPU voltage to prevent overshoot */ + ret = regulator_set_value(dev, 1200000); + if (ret) + return ret; + udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ + ret = regulator_set_value(dev, 1400000); + if (ret) + return ret; + udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ + + ret = rockchip_get_clk(&clk.dev); + if (ret) + return ret; + clk.id = PLL_APLL; + ret = clk_set_rate(&clk, 1800000000); + if (IS_ERR_VALUE(ret)) + return ret; + + return 0; +} + +int rk_board_init(void) +{ + int ret; + + /* We do some SoC one time setting here */ + if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { + ret = veyron_init(); + if (ret) + return ret; + } + + return 0; +} +#endif + +static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + static const struct { + char *name; + int id; + } clks[] = { + { "osc", CLK_OSC }, + { "apll", CLK_ARM }, + { "dpll", CLK_DDR }, + { "cpll", CLK_CODEC }, + { "gpll", CLK_GENERAL }, +#ifdef CONFIG_ROCKCHIP_RK3036 + { "mpll", CLK_NEW }, +#else + { "npll", CLK_NEW }, +#endif + }; + int ret, i; + struct udevice *dev; + + ret = rockchip_get_clk(&dev); + if (ret) { + printf("clk-uclass not found\n"); + return 0; + } + + for (i = 0; i < ARRAY_SIZE(clks); i++) { + struct clk clk; + ulong rate; + + clk.id = clks[i].id; + ret = clk_request(dev, &clk); + if (ret < 0) + continue; + + rate = clk_get_rate(&clk); + printf("%s: %lu\n", clks[i].name, rate); + + clk_free(&clk); + } + + return 0; +} + +U_BOOT_CMD( + clock, 2, 1, do_clock, + "display information about clocks", + "" +); + +#define GRF_SOC_CON2 0xff77024c + +int board_early_init_f(void) +{ + struct udevice *pinctrl; + struct udevice *dev; + int ret; + + /* + * This init is done in SPL, but when chain-loading U-Boot SPL will + * have been skipped. Allow the clock driver to check if it needs + * setting up. + */ + ret = rockchip_get_clk(&dev); + if (ret) { + debug("CLK init failed: %d\n", ret); + return ret; + } + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + return ret; + } + + /* Enable debug UART */ + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); + if (ret) { + debug("%s: Failed to set up console UART\n", __func__); + return ret; + } rk_setreg(GRF_SOC_CON2, 1 << 0); return 0; diff --git a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c index ed82b2b..9945f97 100644 --- a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c +++ b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c @@ -8,16 +8,9 @@ #include #include -void board_boot_order(u32 *spl_boot_list) -{ - /* eMMC prior to sdcard */ - spl_boot_list[0] = BOOT_DEVICE_MMC2; - spl_boot_list[1] = BOOT_DEVICE_MMC1; -} - #define GPIO7A3_HUB_RST 227 -int rk_board_late_init(void) +int rk3288_board_late_init(void) { int ret; diff --git a/board/mqmaker/miqi_rk3288/miqi-rk3288.c b/board/mqmaker/miqi_rk3288/miqi-rk3288.c index a82f0ae..846dedd 100644 --- a/board/mqmaker/miqi_rk3288/miqi-rk3288.c +++ b/board/mqmaker/miqi_rk3288/miqi-rk3288.c @@ -6,10 +6,3 @@ #include #include - -void board_boot_order(u32 *spl_boot_list) -{ - /* eMMC prior to sdcard. */ - spl_boot_list[0] = BOOT_DEVICE_MMC2; - spl_boot_list[1] = BOOT_DEVICE_MMC1; -} diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c index 47b069e..175c017 100644 --- a/board/phytec/phycore_rk3288/phycore-rk3288.c +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c @@ -12,6 +12,7 @@ #include #include #include "som.h" +#include static int valid_rk3288_som(struct rk3288_som *som) { @@ -27,7 +28,49 @@ static int valid_rk3288_som(struct rk3288_som *som) return hw == som->bs; } -int rk_board_late_init(void) +#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_PLATDATA) +static int phycore_init(void) +{ + struct udevice *pmic; + int ret; + + ret = uclass_first_device_err(UCLASS_PMIC, &pmic); + if (ret) + return ret; + +#if defined(CONFIG_SPL_POWER_SUPPORT) + /* Increase USB input current to 2A */ + ret = rk818_spl_configure_usb_input_current(pmic, 2000); + if (ret) + return ret; + + /* Close charger when USB lower then 3.26V */ + ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000); + if (ret) + return ret; +#endif + + return 0; +} + +int rk_board_init_f(void) +{ + int ret = 0; + + if (of_machine_is_compatible("phytec,rk3288-phycore-som")) { + ret = phycore_init(); + if (ret) { + debug("Failed to set up phycore power settings: %d\n", + ret); + return ret; + } + } + + return 0; +} +#endif + +int rk3288_board_late_init(void) { int ret; struct udevice *dev; diff --git a/board/rockchip/evb_rk3288/evb-rk3288.c b/board/rockchip/evb_rk3288/evb-rk3288.c index a82f0ae..846dedd 100644 --- a/board/rockchip/evb_rk3288/evb-rk3288.c +++ b/board/rockchip/evb_rk3288/evb-rk3288.c @@ -6,10 +6,3 @@ #include #include - -void board_boot_order(u32 *spl_boot_list) -{ - /* eMMC prior to sdcard. */ - spl_boot_list[0] = BOOT_DEVICE_MMC2; - spl_boot_list[1] = BOOT_DEVICE_MMC1; -} diff --git a/board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c b/board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c new file mode 100644 index 0000000..88b6327 --- /dev/null +++ b/board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c @@ -0,0 +1,8 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include diff --git a/board/rockchip/fennec_rk3288/fennec-rk3288.c b/board/rockchip/fennec_rk3288/fennec-rk3288.c index aad74ef..846dedd 100644 --- a/board/rockchip/fennec_rk3288/fennec-rk3288.c +++ b/board/rockchip/fennec_rk3288/fennec-rk3288.c @@ -6,10 +6,3 @@ #include #include - -void board_boot_order(u32 *spl_boot_list) -{ - /* eMMC prior to sdcard */ - spl_boot_list[0] = BOOT_DEVICE_MMC2; - spl_boot_list[1] = BOOT_DEVICE_MMC1; -} diff --git a/board/rockchip/tinker_rk3288/tinker-rk3288.c b/board/rockchip/tinker_rk3288/tinker-rk3288.c index 790a921..5681ef1 100644 --- a/board/rockchip/tinker_rk3288/tinker-rk3288.c +++ b/board/rockchip/tinker_rk3288/tinker-rk3288.c @@ -21,7 +21,7 @@ static int get_ethaddr_from_eeprom(u8 *addr) return i2c_eeprom_read(dev, 0, addr, 6); } -int rk_board_late_init(void) +int rk3288_board_late_init(void) { u8 ethaddr[6]; From patchwork Tue Mar 27 09:29:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891476 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OtpjoJPF"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R2F26t6z9s1j for ; Tue, 27 Mar 2018 20:45:09 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id EB130C21F94; Tue, 27 Mar 2018 09:41:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E8D97C21FB3; Tue, 27 Mar 2018 09:33:59 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0ACF6C22037; Tue, 27 Mar 2018 09:31:21 +0000 (UTC) Received: from mail-pg0-f68.google.com (mail-pg0-f68.google.com [74.125.83.68]) by lists.denx.de (Postfix) with ESMTPS id BFD01C21FD2 for ; Tue, 27 Mar 2018 09:31:02 +0000 (UTC) Received: by mail-pg0-f68.google.com with SMTP id y63so5211220pgy.12 for ; Tue, 27 Mar 2018 02:31:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=x+hYFvXo0Azip3Fyc+FJ7W54xPwAD4B+QAMtqUJAa48=; b=OtpjoJPFcTOAbRLj0+vn2Q37iMvQnRMATjokrC/k0kGAwlxHMCAwrMAz0dnF057qLj vZMHBWN93n0vvej7W18DODB2hpL0uGi/ahjsfIfdgNLYtcXfjIpVJYrTdbe3lu9jSLOP tGfI3SwVVt+qVsiPYjOYKQjsvPpkY8pDpXeLiw76tLgg9N9VFkUCNp3mnfI2yFpPTfkS tIoKdYc9nyq6McTaqjmSRYVlSIIIXY23O2OEQS1fJ2fCoj1pNO41c+zkEKE1DqoarZO1 DdYI5iMaJvvvtS5Qy63dhO8cgbNFHPy3KnDvTpoW2dSfqYLnUfeeh7wn4/0zqH1/KhsC g0LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=x+hYFvXo0Azip3Fyc+FJ7W54xPwAD4B+QAMtqUJAa48=; b=TrgrlUQYRq/JDeqWDhRmPmb4f2OgsCVYzNO5SxsU8N/yD0C8KGv9nPEGqBMJYESBkM QLDBPb+V+4AuiIKHWQBJl9va9fxjfeAahv5ok3u+P7CHCK6bM03Azeu5EK5yDAzO/5fx 8kNRtfI0b1jzc/6ukne3AYWTN/zqMRk/u0631iUmtcFDGr+PMAteAOHfwwRgsHO1+7gC 72OO/x7BjlSNBJTOUIkZJpmgdpaHElvJmlaBtWEZr9gA8M9ieQgGj7PVoGNoGaRtshBN vFT19FA00XG/FoZhksXJTXsJoEbXZq95kNkLOqBfFUWs+DrT8CTUnHt1uPBdmzM0tOhQ /MIg== X-Gm-Message-State: AElRT7HQ743qS2TrwZajn6tByM9kg0S71ZW9WSz288Sv/wv0AWDdvbDx D3QCQAo8UAa9mMBrlDfi/6B3lA== X-Google-Smtp-Source: AG47ELttgWI/k6aStRb8KHHAvnPMKa124v1yrC7cEvOfjJvkd/musvLlSKMWVgtPFwNBCqqLqcloug== X-Received: by 10.99.5.137 with SMTP id 131mr29984463pgf.99.1522143061057; Tue, 27 Mar 2018 02:31:01 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:31:00 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:20 +0800 Message-Id: <1522142971-20739-27-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: Thomas Petazzoni , Andy Yan Subject: [U-Boot] [PATCH 26/36] rockchip: rk1108: remove rockchip timer for sys timer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We use ARM arch timer instead. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- include/configs/rv1108_common.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index cd204e9..7a9ec7b 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -13,11 +13,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -/* TIMER1,initialized by ddr initialize code */ -#define CONFIG_SYS_TIMER_BASE 0x10350020 -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) - #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) From patchwork Tue Mar 27 09:29:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891478 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nNdsEyzu"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R2p3nfWz9s1l for ; Tue, 27 Mar 2018 20:45:38 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E5173C21FC1; Tue, 27 Mar 2018 09:42:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 10102C22051; Tue, 27 Mar 2018 09:34:05 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CC854C2206B; Tue, 27 Mar 2018 09:31:21 +0000 (UTC) Received: from mail-pf0-f195.google.com (mail-pf0-f195.google.com [209.85.192.195]) by lists.denx.de (Postfix) with ESMTPS id A6D16C21FC8 for ; Tue, 27 Mar 2018 09:31:05 +0000 (UTC) Received: by mail-pf0-f195.google.com with SMTP id m68so8635137pfm.11 for ; Tue, 27 Mar 2018 02:31:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=HfKGEK2rSy5hLPqOSYp/xxn0BBdNPaAXWnqWA2CBaVU=; b=nNdsEyzuqCnvSiT1VdOGhHO2T/IpsP96g6vd45/WLwEF3jvOKYAd8HikadvUPZaGQn F2Cb73+Kzwy10dg5bL9FFLt3OVHLcxdmw6JU9PPNd9nSDMXHqs4EWk/t0E9XtuEcJJMn OIRsUHYY94s3YXgglBHIDWiThbyXYNETGAE5Brxy67Lc2e4Zkf61c2BXRM7H6NYz7f9y HuQKgyrbOj40Pa/owGL0nwBUa7Euo40lM7PN+M3YJvdsA+PNmAabSM2bUdcgG1gGmk9M SyvUkX+EaGhC7QW1KkuCNRgbN3jjpvX6lV4TJVdsYdRs+XEXwuM2qUfIWKwO7vWec9Ch M1Fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=HfKGEK2rSy5hLPqOSYp/xxn0BBdNPaAXWnqWA2CBaVU=; b=rStnbsER5z9poB58YsyQBdrkzF3OdmufSLixoU1YcKZ0p/FoZ4kuei3aTIV/HePTW/ SGqfVaXDBK2Z0VRUikVijKbya7poW0cd7DSHvOGiU/JDzqP1Tge/mk64Ngp6AmCBsxvt 0SmiIKczA2pJOIxgn6e9Y+UBdeNH3SZAiOn8yKms8tGRI3s3WWKq2YA4GL41ARLiPfRX EMhVNIorjF2s4yLTPzAewrshtT7Z0xbCLqdgDIkFnmvst7XJYwFFPcSz6b3RY57/boHZ clVSSb9G4thBHU6VlJD3NHoMy5ckctadPLjeG5S+PBInAfoCMT/khYU02PCM8kep79pb 5aWg== X-Gm-Message-State: AElRT7EZcNDMzUBR0rBKJ4qipFIqwgIjKDkFnqRFauWQ+6VNehZoiDEP ZB8KmcWMAYAwj1iDFID7mknX9A== X-Google-Smtp-Source: AG47ELseMQWAOQRNyQxwmaMj4e56Xkoz91Sfw46xWEZ1a/u7t3qo2M6/I/wmiA+IXYB7gz6cSTmeiA== X-Received: by 10.99.60.79 with SMTP id i15mr30370621pgn.399.1522143063927; Tue, 27 Mar 2018 02:31:03 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.31.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:31:03 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:21 +0800 Message-Id: <1522142971-20739-28-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: Andy Yan Subject: [U-Boot] [PATCH 27/36] rockchip: rv1108: prepare to use common board file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Remove functions will present at common board file. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/rv1108/rv1108.c | 8 -------- board/rockchip/evb_rv1108/evb_rv1108.c | 6 ------ 2 files changed, 14 deletions(-) diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c b/arch/arm/mach-rockchip/rv1108/rv1108.c index 868cdd5..3b6b21d 100644 --- a/arch/arm/mach-rockchip/rv1108/rv1108.c +++ b/arch/arm/mach-rockchip/rv1108/rv1108.c @@ -5,11 +5,3 @@ */ #include - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c index 54bd08b..0160f42 100644 --- a/board/rockchip/evb_rv1108/evb_rv1108.c +++ b/board/rockchip/evb_rv1108/evb_rv1108.c @@ -47,12 +47,6 @@ int mach_cpu_init(void) return 0; } - -int board_init(void) -{ - return 0; -} - int dram_init(void) { gd->ram_size = 0x8000000; From patchwork Tue Mar 27 09:29:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891475 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="RixPWWae"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R263WVqz9s1j for ; Tue, 27 Mar 2018 20:45:02 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 077BEC21FA4; Tue, 27 Mar 2018 09:41:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D64CDC2202A; Tue, 27 Mar 2018 09:33:57 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5285AC2204A; Tue, 27 Mar 2018 09:31:24 +0000 (UTC) Received: from mail-pg0-f68.google.com (mail-pg0-f68.google.com [74.125.83.68]) by lists.denx.de (Postfix) with ESMTPS id 84FD6C21F88 for ; Tue, 27 Mar 2018 09:31:08 +0000 (UTC) Received: by mail-pg0-f68.google.com with SMTP id y63so5211299pgy.12 for ; Tue, 27 Mar 2018 02:31:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=9LT38wGBfVnesi2dXjywineIkL6hxcDCxBYMeLsRO5E=; b=RixPWWae1KQHrR8pL4POUI8RDfTdRqAsYjvGB7eX8egKc0Cxgl/8QzopfBNfPZ3aAz 6K0mxsizWQ9hwkfIYdhWQvZVbCOUR66pExcnLuBvOR3Ua57ZlDzOeAX/evQsjZQG1QVR zy79HaiHIq9Sgz6wMG01lMU6Pp4U2Cz8+JslbSh7rhzBi/wAwb91x+uv7Qw0J0OUv1lY qfbM2z3dZG3h27vKTLyiIEbHLmM0tK96qZ8QIha+ct2NBtl+JY3d0nL2xl/Jm7vXcyAA 9HtTdMDW4dvg5qhgLSXk1FhZ7q+17EBOHW4KS6+0e/cBs2SJmIHtfGZ7OFCdVekNSVMF yPPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=9LT38wGBfVnesi2dXjywineIkL6hxcDCxBYMeLsRO5E=; b=spcQ47jBuMEvAFh30HoSGxR2eDX+p/FfQcXNSiFEcXnDzmh+wpNXOClttKFjoFVyaU JyU4vkdPHduvuau9F72cIb4Rrhee93eb67JXBgLS5kVFoNvDaeFQjb1rn8MzpM/guglu uymMexmqA3Tdf1ADo73P/R443rj190t0jOFuv89dCByYp4pLc+SL8s6BaRFp2O7hbrFQ aVM75EgI3BMq9vncfEdJvR9myJCgjFz56Mue4idQOxMzCpxDh5N1BsIRuPj/9GK7MoJ8 1atrmxtREOrKyqjOBuugKGvV8H7jSH8wUnZU15WFNFGb9gZ5SQlORxTe+L0rZHCX15Bh bFGw== X-Gm-Message-State: AElRT7EVVYs4+o6JcfxjT99P0Ewi//YnRSeqdIz61l6TpHexTYQFVIRg w1x9xOY9tyIjKOMydgCvwnoFUA== X-Google-Smtp-Source: AG47ELtJeYG+fbUGHLgwyJjgJhOBRe4s4UzhTpCmXYCPdvjTU/zkne/JdAi9yMU30kRRSDvi0BFAvg== X-Received: by 10.99.96.19 with SMTP id u19mr30101343pgb.261.1522143066668; Tue, 27 Mar 2018 02:31:06 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.31.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:31:05 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:22 +0800 Message-Id: <1522142971-20739-29-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 28/36] rockchip: rk3328: prepare to use common board file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use common board file and move SoC spec setting into rk3328.c Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/rk3328/rk3328.c | 59 +++++++++++++++++++++++++----- board/rockchip/evb_rk3328/evb-rk3328.c | 66 ---------------------------------- 2 files changed, 51 insertions(+), 74 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index 6764494..ddf53d5 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -5,12 +5,22 @@ */ #include +#include #include +#include +#include #include #include DECLARE_GLOBAL_DATA_PTR; +#define CRU_BASE 0xFF440000 +#define GRF_BASE 0xFF100000 +#define UART2_BASE 0xFF130000 + +#define CRU_MISC_CON 0xff440084 +#define FW_DDR_CON_REG 0xff7c0040 + static struct mm_region rk3328_mem_map[] = { { .virt = 0x0UL, @@ -33,20 +43,53 @@ static struct mm_region rk3328_mem_map[] = { struct mm_region *mem_map = rk3328_mem_map; -int dram_init_banksize(void) +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/rksdmmc@ff520000", + [BROM_BOOTSOURCE_SD] = "/rksdmmc@ff500000", +}; + +int arch_cpu_init(void) { - size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); +#ifdef CONFIG_TPL_BUILD + struct rk3328_grf_regs * const grf = (void *)GRF_BASE; + /* We do some SoC one time setting here. */ + + /* Disable the ddr secure region setting to make it non-secure */ + rk_setreg(FW_DDR_CON_REG, 0x200); - /* Reserve 0x200000 for ATF bl31 */ - gd->bd->bi_dram[0].start = 0x200000; - gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start; + /* HDMI phy clock source select HDMIPHY clock out */ + rk_clrreg(CRU_MISC_CON, 1 << 13); +#endif return 0; } -int arch_cpu_init(void) +void board_debug_uart_init(void) { - /* We do some SoC one time setting here. */ +#ifdef CONFIG_TPL_BUILD + struct rk3328_grf_regs * const grf = (void *)GRF_BASE; + struct rk_uart * const uart = (void *)UART2_BASE; - return 0; + /* uart_sel_clk default select 24MHz */ + writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148); + + /* init uart baud rate 1500000 */ + writel(0x83, &uart->lcr); + writel(0x1, &uart->rbr); + writel(0x3, &uart->lcr); + + /* Enable early UART2 */ + rk_clrsetreg(&grf->com_iomux, + IOMUX_SEL_UART2_MASK, + IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A0_SEL_MASK, + GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A1_SEL_MASK, + GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT); + + /* enable FIFO */ + writel(0x1, &uart->sfe); +#endif } diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c index 99a73da..c8e7a3a 100644 --- a/board/rockchip/evb_rk3328/evb-rk3328.c +++ b/board/rockchip/evb_rk3328/evb-rk3328.c @@ -3,69 +3,3 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - int ret; - - ret = regulators_enable_boot_on(false); - if (ret) - debug("%s: Cannot enable boot on regulator\n", __func__); - - return ret; -} - -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) -#include -#include - -static struct dwc2_plat_otg_data rk3328_otg_data = { - .rx_fifo_sz = 512, - .np_tx_fifo_sz = 16, - .tx_fifo_sz = 128, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node; - const char *mode; - bool matched = false; - const void *blob = gd->fdt_blob; - - /* find the usb_otg node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3328-usb"); - - while (node > 0) { - mode = fdt_getprop(blob, node, "dr_mode", NULL); - if (mode && strcmp(mode, "otg") == 0) { - matched = true; - break; - } - - node = fdt_node_offset_by_compatible(blob, node, - "rockchip,rk3328-usb"); - } - if (!matched) { - debug("Not found usb_otg device\n"); - return -ENODEV; - } - - rk3328_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - - return dwc2_udc_probe(&rk3328_otg_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} -#endif From patchwork Tue Mar 27 09:29:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891472 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="e/Yv1DMe"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R1N6ppZz9s1c for ; Tue, 27 Mar 2018 20:44:24 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 7D6BCC21FC4; Tue, 27 Mar 2018 09:40:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 52757C2200F; Tue, 27 Mar 2018 09:33:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 444F4C21F9C; Tue, 27 Mar 2018 09:31:25 +0000 (UTC) Received: from mail-pf0-f194.google.com (mail-pf0-f194.google.com [209.85.192.194]) by lists.denx.de (Postfix) with ESMTPS id DB2AEC21FF8 for ; Tue, 27 Mar 2018 09:31:11 +0000 (UTC) Received: by mail-pf0-f194.google.com with SMTP id j2so8633084pff.10 for ; Tue, 27 Mar 2018 02:31:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=/7i0ttU/iGvkFmDDHXOM31Oc7oALdvvkCJKFWLaZmfg=; b=e/Yv1DMeH4KSpR5qTkSvWPfgB/1KyLrRn0YxxShlRXxOPMQBE+X6cVOGCIqXJsJbq7 RIQqLQa0PhrkGYW1xaEdeOfp8LeP3ivF5l+zChJ/RO42AyBwuItvgp458ztihHhHe+uT WAHzVPbji4WvOXE5XW5i9+MkcpiMJvPjTRgsu5OqflqfrAadhlvW8JhzWT1NcPTsq0rY LD541A4wdygGLEyK62ShO6uB1Jx8Cr18xoV97bkLcTaMJzJke10w6SOnShFc+aBW7+hh N7bXaGIKTlY26AIsWjo4wcySzK3+2bWsnKY2m5Y0s3idv6UduQDdSjldblVlrDX/02AB SlEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=/7i0ttU/iGvkFmDDHXOM31Oc7oALdvvkCJKFWLaZmfg=; b=Tk82V/xxSZY6Jx1kLUir65wo59ytUSa2jXJD0S+gpLEHAfKZuEA/bkx2PPbYIjtl1a S6PCkrioH+j+/k8YNqs+PD24r7qjpdhWA5BgaCXMe98ocMWnNXWVQC+UAy5Nszc7VZt8 d0YHdoI4j+Nh6MKmJub1RqlYmLn16sThDRjR6GOw2z/PMeZPppFUoxf6Oii8pcsDx6qo 3V/4+5g7hH2+3mdY8kF/QDAS307zTJ1bUWPFidirtf12UaEG1TgKs5Gt7lgjPxIshcvu kql3n1YCI6bKrIbXy9Qm5VZFV19Dk1Tz5tTwctXKQJCN96lAayDEzSk8Mv2d9njco9SM XK5A== X-Gm-Message-State: AElRT7HL7KE14ryYq3PWjfDcouABY3y01dLyh1ahoKp9ANvaNPZlOeud YqsnIgVueFF2URmXH97fn9ydUQ== X-Google-Smtp-Source: AG47ELu//FqHcxhN6uyeY/G/JV1SQIk0rIL8tOzNu18W10nL9t0SzKjljCZvpm3l1Nr2nld6Wt/m4A== X-Received: by 10.101.96.134 with SMTP id t6mr20196127pgu.58.1522143069925; Tue, 27 Mar 2018 02:31:09 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.31.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:31:08 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:23 +0800 Message-Id: <1522142971-20739-30-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: Klaus Goger , Andy Yan , =?utf-8?q?Andreas_F=C3=A4rber?= Subject: [U-Boot] [PATCH 29/36] rockchip: rk3368: prepare to use common board file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use common board file and move SoC spec setting into rk3368.c Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/rk3368-board-spl.c | 73 ---------- arch/arm/mach-rockchip/rk3368-board-tpl.c | 157 ---------------------- arch/arm/mach-rockchip/rk3368/rk3368.c | 116 ++++++++++++++-- board/geekbuying/geekbox/geekbox.c | 5 - board/rockchip/evb_px5/evb-px5.c | 5 - board/rockchip/sheep_rk3368/sheep_rk3368.c | 5 - board/theobroma-systems/lion_rk3368/lion_rk3368.c | 8 -- 7 files changed, 106 insertions(+), 263 deletions(-) delete mode 100644 arch/arm/mach-rockchip/rk3368-board-spl.c delete mode 100644 arch/arm/mach-rockchip/rk3368-board-tpl.c diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c deleted file mode 100644 index 8055ae5..0000000 --- a/arch/arm/mach-rockchip/rk3368-board-spl.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void board_debug_uart_init(void) -{ -} - -void board_init_f(ulong dummy) -{ - struct udevice *pinctrl; - struct udevice *dev; - int ret; - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - /* Set up our preloader console */ - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - pr_err("%s: pinctrl init failed: %d\n", __func__, ret); - hang(); - } - - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0); - if (ret) { - pr_err("%s: failed to set up console UART\n", __func__); - hang(); - } - - preloader_console_init(); - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_MMC1; -} - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c deleted file mode 100644 index 60d5aea..0000000 --- a/arch/arm/mach-rockchip/rk3368-board-tpl.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * The SPL (and also the full U-Boot stage on the RK3368) will run in - * secure mode (i.e. EL3) and an ATF will eventually be booted before - * starting up the operating system... so we can initialize the SGRF - * here and rely on the ATF installing the final (secure) policy - * later. - */ -static inline uintptr_t sgrf_soc_con_addr(unsigned no) -{ - const uintptr_t SGRF_BASE = - (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); - - return SGRF_BASE + sizeof(u32) * no; -} - -static inline uintptr_t sgrf_busdmac_addr(unsigned no) -{ - const uintptr_t SGRF_BASE = - (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); - const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100; - const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET; - - return SGRF_BUSDMAC_BASE + sizeof(u32) * no; -} - -static void sgrf_init(void) -{ - struct rk3368_cru * const cru = - (struct rk3368_cru * const)rockchip_get_cru(); - const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0); - const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2); - const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12); - - /* Set all configurable IP to 'non secure'-mode */ - rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC); - rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC); - rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC); - - /* - * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c - * Original comment: "ddr space set no secure mode" - */ - rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC); - rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC); - rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC); - - /* Set 'secure dma' to 'non secure'-mode */ - rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC); - rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC); - - dsb(); /* barrier */ - - rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ); - rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ); - - dsb(); /* barrier */ - udelay(10); - - rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ); - rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ); -} - -void board_debug_uart_init(void) -{ - /* - * N.B.: This is called before the device-model has been - * initialised. For this reason, we can not access - * the GRF address range using the syscon API. - */ - struct rk3368_grf * const grf = - (struct rk3368_grf * const)0xff770000; - - enum { - GPIO2D1_MASK = GENMASK(3, 2), - GPIO2D1_GPIO = 0, - GPIO2D1_UART0_SOUT = (1 << 2), - - GPIO2D0_MASK = GENMASK(1, 0), - GPIO2D0_GPIO = 0, - GPIO2D0_UART0_SIN = (1 << 0), - }; - -#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) - /* Enable early UART0 on the RK3368 */ - rk_clrsetreg(&grf->gpio2d_iomux, - GPIO2D0_MASK, GPIO2D0_UART0_SIN); - rk_clrsetreg(&grf->gpio2d_iomux, - GPIO2D1_MASK, GPIO2D1_UART0_SOUT); -#endif -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - -#define EARLY_UART -#ifdef EARLY_UART - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - printascii("U-Boot TPL board init\n"); -#endif - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - /* Reset security, so we can use DMA in the MMC drivers */ - sgrf_init(); - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } -} - -void board_return_to_bootrom(void) -{ - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_BOOTROM; -} diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index f62d91d..8c0b370 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -52,16 +53,10 @@ static struct mm_region rk3368_mem_map[] = { struct mm_region *mem_map = rk3368_mem_map; -int dram_init_banksize(void) -{ - size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); - - /* Reserve 0x200000 for ATF bl31 */ - gd->bd->bi_dram[0].start = 0x200000; - gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start; - - return 0; -} +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000", + [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000", +}; #ifdef CONFIG_ARCH_EARLY_INIT_R static int mcu_init(void) @@ -97,3 +92,104 @@ int arch_early_init_r(void) return mcu_init(); } #endif + +#ifdef CONFIG_SPL_BUILD +/* + * The SPL (and also the full U-Boot stage on the RK3368) will run in + * secure mode (i.e. EL3) and an ATF will eventually be booted before + * starting up the operating system... so we can initialize the SGRF + * here and rely on the ATF installing the final (secure) policy + * later. + */ +static inline uintptr_t sgrf_soc_con_addr(u32 no) +{ + const uintptr_t SGRF_BASE = + (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); + + return SGRF_BASE + sizeof(u32) * no; +} + +static inline uintptr_t sgrf_busdmac_addr(u32 no) +{ + const uintptr_t SGRF_BASE = + (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); + const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100; + const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET; + + return SGRF_BUSDMAC_BASE + sizeof(u32) * no; +} + +static void sgrf_init(void) +{ + struct rk3368_cru * const cru = + (struct rk3368_cru * const)rockchip_get_cru(); + const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0); + const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2); + const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12); + + /* Set all configurable IP to 'non secure'-mode */ + rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC); + rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC); + rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC); + + /* + * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c + * Original comment: "ddr space set no secure mode" + */ + rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC); + rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC); + rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC); + + /* Set 'secure dma' to 'non secure'-mode */ + rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC); + rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC); + + dsb(); /* barrier */ + + rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ); + rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ); + + dsb(); /* barrier */ + udelay(10); + + rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ); + rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ); +} + +void board_debug_uart_init(void) +{ + /* + * N.B.: This is called before the device-model has been + * initialised. For this reason, we can not access + * the GRF address range using the syscon API. + */ + struct rk3368_grf * const grf = + (struct rk3368_grf * const)0xff770000; + + enum { + GPIO2D1_MASK = GENMASK(3, 2), + GPIO2D1_GPIO = 0, + GPIO2D1_UART0_SOUT = (1 << 2), + + GPIO2D0_MASK = GENMASK(1, 0), + GPIO2D0_GPIO = 0, + GPIO2D0_UART0_SIN = (1 << 0), + }; + +#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) + /* Enable early UART0 on the RK3368 */ + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D0_MASK, GPIO2D0_UART0_SIN); + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D1_MASK, GPIO2D1_UART0_SOUT); +#endif +} + +int arch_cpu_init(void) +{ + /* Reset security, so we can use DMA in the MMC drivers */ + sgrf_init(); + + return 0; +} +#endif diff --git a/board/geekbuying/geekbox/geekbox.c b/board/geekbuying/geekbox/geekbox.c index 88b67f9..d682349 100644 --- a/board/geekbuying/geekbox/geekbox.c +++ b/board/geekbuying/geekbox/geekbox.c @@ -7,8 +7,3 @@ #include DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - return 0; -} diff --git a/board/rockchip/evb_px5/evb-px5.c b/board/rockchip/evb_px5/evb-px5.c index 6a47642..ec3d27e 100644 --- a/board/rockchip/evb_px5/evb-px5.c +++ b/board/rockchip/evb_px5/evb-px5.c @@ -4,8 +4,3 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include - -int board_init(void) -{ - return 0; -} diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c index 17adb02..ff2d2d2 100644 --- a/board/rockchip/sheep_rk3368/sheep_rk3368.c +++ b/board/rockchip/sheep_rk3368/sheep_rk3368.c @@ -15,8 +15,3 @@ int mach_cpu_init(void) { return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/theobroma-systems/lion_rk3368/lion_rk3368.c b/board/theobroma-systems/lion_rk3368/lion_rk3368.c index 73b1488..025692b 100644 --- a/board/theobroma-systems/lion_rk3368/lion_rk3368.c +++ b/board/theobroma-systems/lion_rk3368/lion_rk3368.c @@ -7,9 +7,6 @@ #include #include #include -#include -#include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -18,8 +15,3 @@ int mach_cpu_init(void) { return 0; } - -int board_init(void) -{ - return 0; -} From patchwork Tue Mar 27 09:29:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891485 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="RK3fh4Ji"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R7V39WJz9s1S for ; Tue, 27 Mar 2018 20:49:42 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2E62DC21FCA; Tue, 27 Mar 2018 09:43:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 436E6C2203B; Tue, 27 Mar 2018 09:34:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DE53CC22063; Tue, 27 Mar 2018 09:31:24 +0000 (UTC) Received: from mail-pg0-f67.google.com (mail-pg0-f67.google.com [74.125.83.67]) by lists.denx.de (Postfix) with ESMTPS id 7508AC21FB5 for ; Tue, 27 Mar 2018 09:31:14 +0000 (UTC) Received: by mail-pg0-f67.google.com with SMTP id a15so8350189pgn.5 for ; Tue, 27 Mar 2018 02:31:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=o4U6RUctOgxnojBNyjajlcXUQcfNOhSZq/WVexogtKE=; b=RK3fh4JiiOrRs0iuw3jYssn9UdOx5FRxGC8pKTVvaQtTGNTk1hESp0SuKHJJLJhvdj r5YgwSH/wIsBnBZwaTLvkKTr5Qoj3nbG+zmU16vsAfbse1a/l8jKyxLK6CSuLCVgmJcS WxAMhLZUAoOWLaHyiozXjBCC6bSy8zTJN/ONTXIZNwr4Wh8uNSW2w14BQJoWgiX5Jabk /b6kmqowHC4OMP2gIP1bjU+kMYv93fvZoCOzBZokgnt7uhyhnVuQRNVdxv3l2CE28fO6 7+fA72FqjMYIscXB8wWDte3gvMTm36Yq8qO6Qw4cN6qZJK3xqHYMPwsBP4sy64qVysMk cQlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=o4U6RUctOgxnojBNyjajlcXUQcfNOhSZq/WVexogtKE=; b=Bnmpxa1DESo5euM6V9R9mbj6UR3mJkBngS9tbBp41MZm6OFpvPj8YEZfcfzeitb6no xHkgKChJlZvmyHekg+KXUd8MJjpWAsz7FmtBlgyTj2vROqubW8gU72zT7r4EEj55zZ2t 1u7Ubi4BiX3X3PhlAiUJtwbArsNcCUwjKp4eM1HnfHyRbQ4lhWcKWiTbglT4JxweOzXI qg3ghW3PrKwwufuvBDLPVeOQEr7Q54xKfk2XuAate2b+H6GLJForWx/wm+fB6VB0CJPF RmZt3/NV+aIZDzN1MZVFrIEoE34lL5LfS68ZSZ+PH2tj69UVZCrXtdqnrCg2d929CkhE i78g== X-Gm-Message-State: AElRT7GYPYIrCSR7+jpTKx4waiW6Pwh6PJLNWFjojkYRGZBHf0w5/M/7 9E7Jx5c2+PT1HVKEYTPWibABRQ== X-Google-Smtp-Source: AG47ELt7ozShJl/4DhB301i+bz17dGSZWs1/BHRw+p9Ci8Zmc4TmS0bIT2IhGd1J0iAGQAJurGoVbQ== X-Received: by 10.98.180.13 with SMTP id h13mr35657765pfn.139.1522143072730; Tue, 27 Mar 2018 02:31:12 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.31.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:31:11 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:24 +0800 Message-Id: <1522142971-20739-31-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: Klaus Goger Subject: [U-Boot] [PATCH 30/36] rockchip: lion-rk3368: remove rockchip timer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We use ARM generic timer. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- configs/lion-rk3368_defconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index 8a95ce3..89c4d76 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -88,10 +88,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y -CONFIG_TIMER=y -CONFIG_SPL_TIMER=y -CONFIG_TPL_TIMER=y -CONFIG_ROCKCHIP_TIMER=y CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_TINY_MEMSET=y CONFIG_LZO=y From patchwork Tue Mar 27 09:29:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891479 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nYsnhHTj"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R390P4Gz9s1l for ; Tue, 27 Mar 2018 20:45:57 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BE2FBC21FBF; Tue, 27 Mar 2018 09:43:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 352B2C2204C; Tue, 27 Mar 2018 09:34:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8231BC2205D; Tue, 27 Mar 2018 09:31:25 +0000 (UTC) Received: from mail-pf0-f195.google.com (mail-pf0-f195.google.com [209.85.192.195]) by lists.denx.de (Postfix) with ESMTPS id A8D64C21FD8 for ; Tue, 27 Mar 2018 09:31:17 +0000 (UTC) Received: by mail-pf0-f195.google.com with SMTP id a16so8637952pfn.9 for ; Tue, 27 Mar 2018 02:31:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=iOAqfn/oYApf9qaZI+r8r4Cp66CcF12W+ljHmNRsj5Q=; b=nYsnhHTj03R3xSl2qOcl68c29cY+T3C2FG8z7qw2HALjZjIezAqikiRkw6siphvfp2 Lh7aR7bM1Jagi1xHwlryTo4N5HAl4VvLZF3bpCub+7jzD43BxWtuRAs23Q2bi+kbcQOz Uu2VQwrB1Jk20i9aGjBJ3sYbC/e7VBCtGPmEYl3F00T8/RxYZ6wvYuUptm8WxNozD/NS 5ZFyoHW2BvV4shjDCs7f8LVOrMxIGMNlL6G5nQaqAWZYhNx10PF86w+N1ne1Jcv6pPIv F06rlqKSByPHaKRqR9ri3L0t9Kyd0jz6PM9MzlSQXyEK63wE05W7jHZ0ew5dZWcG/kFi q39w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=iOAqfn/oYApf9qaZI+r8r4Cp66CcF12W+ljHmNRsj5Q=; b=X7Be996S8/qSkQsj+LAo5I21/npbx0ePC7mlSQs7fB+G6BMDKle1w9oR7a9h5LBPpC 48EWwM+YDMC76OH06/J2pmCBsTsO3TlbC62Ye8vhVBWcEWmeg08aq9eJyWhgUelKWSb7 3og1YGeIJd5go4+kKs/j06/S8cNpUwunche21MVAFjYm3auVusDFh7y2RCt98fHKRiXn dvfac+jGAMaRObtR7dEHhdXY7JUYf6Dw1p+inlkFSlTdG0Kw425pchgP0iOIupo3qTtD GDAnm9K+PA+QaZehdKSDs/3CVDt+Ww+OfFotllaW4qaNjO+Tg2LNztHf5tiKgb97w+X1 Svhw== X-Gm-Message-State: AElRT7GAzAu+bqeoNNd2Utx0ygPoqwjUgjcae0u0BGurClFairmNSajN Givod0ggJk2ZDe5sF2XcMhtwAQ== X-Google-Smtp-Source: AG47ELsJiQaE4c8oTg4dqaxUpghu+yDAmtM8AiMwO2BQL2jLh5VAtoArKJlzAS5Q59GGjJxzCByNHQ== X-Received: by 10.98.224.93 with SMTP id f90mr24606826pfh.21.1522143075649; Tue, 27 Mar 2018 02:31:15 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.31.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:31:14 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:25 +0800 Message-Id: <1522142971-20739-32-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: Klaus Goger Subject: [U-Boot] [PATCH 31/36] rockchip: rk3399: prepare to use common board file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use common board file and move SoC spec setting into rk3399.c Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/rk3399-board-spl.c | 179 ---------------------- arch/arm/mach-rockchip/rk3399-board.c | 14 -- arch/arm/mach-rockchip/rk3399/rk3399.c | 86 +++++++++-- board/rockchip/evb_rk3399/evb-rk3399.c | 56 ++++--- board/theobroma-systems/puma_rk3399/puma-rk3399.c | 17 +- 5 files changed, 103 insertions(+), 249 deletions(-) delete mode 100644 arch/arm/mach-rockchip/rk3399-board-spl.c delete mode 100644 arch/arm/mach-rockchip/rk3399-board.c diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c deleted file mode 100644 index d35990e..0000000 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void board_return_to_bootrom(void) -{ - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -} - -static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000", - [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000", - [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000", -}; - -const char *board_spl_was_booted_from(void) -{ - u32 bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR); - const char *bootdevice_ofpath = NULL; - - if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) - bootdevice_ofpath = boot_devices[bootdevice_brom_id]; - - if (bootdevice_ofpath) - debug("%s: brom_bootdevice_id %x maps to '%s'\n", - __func__, bootdevice_brom_id, bootdevice_ofpath); - else - debug("%s: failed to resolve brom_bootdevice_id %x\n", - __func__, bootdevice_brom_id); - - return bootdevice_ofpath; -} - -u32 spl_boot_device(void) -{ - u32 boot_device = BOOT_DEVICE_MMC1; - - if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) - return BOOT_DEVICE_BOOTROM; - - return boot_device; -} - -#define TIMER_CHN10_BASE 0xff8680a0 -#define TIMER_END_COUNT_L 0x00 -#define TIMER_END_COUNT_H 0x04 -#define TIMER_INIT_COUNT_L 0x10 -#define TIMER_INIT_COUNT_H 0x14 -#define TIMER_CONTROL_REG 0x1c - -#define TIMER_EN 0x1 -#define TIMER_FMODE (0 << 1) -#define TIMER_RMODE (1 << 1) - -void secure_timer_init(void) -{ - writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); - writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); - writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); - writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); - writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); -} - -void board_debug_uart_init(void) -{ -#define GRF_BASE 0xff770000 - struct rk3399_grf_regs * const grf = (void *)GRF_BASE; - -#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) - /* Enable early UART0 on the RK3399 */ - rk_clrsetreg(&grf->gpio2c_iomux, - GRF_GPIO2C0_SEL_MASK, - GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT); - rk_clrsetreg(&grf->gpio2c_iomux, - GRF_GPIO2C1_SEL_MASK, - GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT); -#else - /* Enable early UART2 channel C on the RK3399 */ - rk_clrsetreg(&grf->gpio4c_iomux, - GRF_GPIO4C3_SEL_MASK, - GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); - rk_clrsetreg(&grf->gpio4c_iomux, - GRF_GPIO4C4_SEL_MASK, - GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); - /* Set channel C as UART2 input */ - rk_clrsetreg(&grf->soc_con7, - GRF_UART_DBG_SEL_MASK, - GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT); -#endif -} - -void board_init_f(ulong dummy) -{ - struct udevice *pinctrl; - struct udevice *dev; - struct rk3399_pmusgrf_regs *sgrf; - struct rk3399_grf_regs *grf; - int ret; - -#define EARLY_UART -#ifdef EARLY_UART - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - printascii("U-Boot SPL board init"); -#endif - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - /* - * Disable DDR and SRAM security regions. - * - * As we are entered from the BootROM, the region from - * 0x0 through 0xfffff (i.e. the first MB of memory) will - * be protected. This will cause issues with the DW_MMC - * driver, which tries to DMA from/to the stack (likely) - * located in this range. - */ - sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); - rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0); - rk_clrreg(&sgrf->slv_secure_con4, 0x2000); - - /* eMMC clock generator: disable the clock multipilier */ - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - rk_clrreg(&grf->emmccore_con[11], 0x0ff); - - secure_timer_init(); - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("Pinctrl init failed: %d\n", ret); - return; - } - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } -} - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk3399-board.c b/arch/arm/mach-rockchip/rk3399-board.c deleted file mode 100644 index 9293843..0000000 --- a/arch/arm/mach-rockchip/rk3399-board.c +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2017 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -int board_late_init(void) -{ - setup_boot_mode(); - return 0; -} diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index dbc248f..6c89f25 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -6,8 +6,11 @@ #include #include -#include +#include +#include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -35,23 +38,86 @@ static struct mm_region rk3399_mem_map[] = { struct mm_region *mem_map = rk3399_mem_map; -int dram_init_banksize(void) -{ - size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000", + [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000", +}; - /* Reserve 0x200000 for ATF bl31 */ - gd->bd->bi_dram[0].start = 0x200000; - gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start; +#ifdef CONFIG_SPL_BUILD - return 0; +#define TIMER_CHN10_BASE 0xff8680a0 +#define TIMER_END_COUNT_L 0x00 +#define TIMER_END_COUNT_H 0x04 +#define TIMER_INIT_COUNT_L 0x10 +#define TIMER_INIT_COUNT_H 0x14 +#define TIMER_CONTROL_REG 0x1c + +#define TIMER_EN 0x1 +#define TIMER_FMODE (0 << 1) +#define TIMER_RMODE (1 << 1) + +void rockchip_stimer_init(void) +{ + writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); + writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); + writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); + writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); + writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); + printf("%s\n", __func__); } +#define GRF_BASE 0xff770000 +#define PMUSGRF_BASE 0xff330000 int arch_cpu_init(void) { + struct rk3399_pmusgrf_regs *sgrf = (void *)PMUSGRF_BASE; + struct rk3399_grf_regs * const grf = (void *)GRF_BASE; + /* We do some SoC one time setting here. */ + /* + * Disable DDR and SRAM security regions. + * + * As we are entered from the BootROM, the region from + * 0x0 through 0xfffff (i.e. the first MB of memory) will + * be protected. This will cause issues with the DW_MMC + * driver, which tries to DMA from/to the stack (likely) + * located in this range. + */ + rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0); + rk_clrreg(&sgrf->slv_secure_con4, 0x2000); - /* Emmc clock generator: disable the clock multipilier */ - rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff); + /* eMMC clock generator: disable the clock multipilier */ + rk_clrreg(&grf->emmccore_con[11], 0x0ff); return 0; } +#endif + +void board_debug_uart_init(void) +{ +#define GRF_BASE 0xff770000 + struct rk3399_grf_regs * const grf = (void *)GRF_BASE; + +#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) + /* Enable early UART0 on the RK3399 */ + rk_clrsetreg(&grf->gpio2c_iomux, + GRF_GPIO2C0_SEL_MASK, + GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2c_iomux, + GRF_GPIO2C1_SEL_MASK, + GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT); +#else + /* Enable early UART2 channel C on the RK3399 */ + rk_clrsetreg(&grf->gpio4c_iomux, + GRF_GPIO4C3_SEL_MASK, + GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); + rk_clrsetreg(&grf->gpio4c_iomux, + GRF_GPIO4C4_SEL_MASK, + GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); + /* Set channel C as UART2 input */ + rk_clrsetreg(&grf->soc_con7, + GRF_UART_DBG_SEL_MASK, + GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT); +#endif +} diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index 502dec3..79b7436 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -6,23 +6,29 @@ #include #include +#include #include #include #include #include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; -int board_init(void) +#define RK3399_CPUID_OFF 0x7 +#define RK3399_CPUID_LEN 0x10 + +int rk_board_init(void) { struct udevice *pinctrl, *regulator; int ret; /* - * The PWM do not have decicated interrupt number in dts and can + * The PWM does not have decicated interrupt number in dts and can * not get periph_id by pinctrl framework, so let's init them here. - * The PWM2 and PWM3 are for pwm regulater. + * The PWM2 and PWM3 are for pwm regulators. */ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { @@ -49,10 +55,6 @@ int board_init(void) goto out; } - ret = regulators_enable_boot_on(false); - if (ret) - debug("%s: Cannot enable boot on regulator\n", __func__); - ret = regulator_get_by_platname("vcc5v0_host", ®ulator); if (ret) { debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret); @@ -69,29 +71,23 @@ out: return 0; } -void spl_board_init(void) -{ - struct udevice *pinctrl; - int ret; - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - goto err; - } +#ifdef CONFIG_USB_DWC3 +static struct dwc3_device dwc3_device_data = { + .maximum_speed = USB_SPEED_HIGH, + .base = 0xfe800000, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .dis_u2_susphy_quirk = 1, +}; - preloader_console_init(); - return; -err: - printf("%s: Error %d\n", __func__, ret); +int usb_gadget_handle_interrupts(void) +{ + dwc3_uboot_handle_interrupt(0); + return 0; +} - /* No way to report error here */ - hang(); +int board_usb_init(int index, enum usb_init_type init) +{ + return dwc3_uboot_init(&dwc3_device_data); } +#endif diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index c6690fa..9946311 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -25,21 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - int ret; - - /* - * We need to call into regulators_enable_boot_on() again, as the call - * during SPL may have not included all regulators. - */ - ret = regulators_enable_boot_on(false); - if (ret) - debug("%s: Cannot enable boot on regulator\n", __func__); - - return 0; -} - static void rk3399_force_power_on_reset(void) { ofnode node; @@ -62,7 +47,7 @@ static void rk3399_force_power_on_reset(void) dm_gpio_set_value(&sysreset_gpio, 1); } -void spl_board_init(void) +void rk_spl_board_init(void) { int ret; struct rk3399_cru *cru = rockchip_get_cru(); From patchwork Tue Mar 27 09:29:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891486 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="jxbPcfiM"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R8Z2dYJz9s1S for ; Tue, 27 Mar 2018 20:50:38 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1A2A1C21FAC; Tue, 27 Mar 2018 09:39:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BAD1BC22010; Tue, 27 Mar 2018 09:32:53 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A978EC2200E; Tue, 27 Mar 2018 09:31:26 +0000 (UTC) Received: from mail-pl0-f65.google.com (mail-pl0-f65.google.com [209.85.160.65]) by lists.denx.de (Postfix) with ESMTPS id 0D363C21FE5 for ; Tue, 27 Mar 2018 09:31:20 +0000 (UTC) Received: by mail-pl0-f65.google.com with SMTP id x4-v6so13736695pln.7 for ; Tue, 27 Mar 2018 02:31:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=eQonxqUCnqGqv/YJhu6uvmxK+aLvOoWfACTka+eVdbM=; b=jxbPcfiM6dCViFLwMtkw6GzlykQE4aGnwwlkQcjCgK/pkIos/+a2HygrQB6L6xiKAD lqKAGzMS4BjdwgHi3L8CfBAj7NG9M0x/xp6GvO2VMrTsdMF4dxs7EmXSawyfw9eeuUCU Da1z03+YlH+NXzL7nNXFJSelGSf7hXQaFqaOtSgKzCAaNYVST/DgEZf6FRT02bumFqeM 9kJL268nROiiW/AEiXbqZZU4j2tzcY7RIurdhbiBSHh2CpVQeojdlkxzf6m/jlvkjQmi HnaRuUEZq+4euRxBeTQ0WygeCT8cBEcsgFk2jZH0QscbyEEZwwmGIpNsoxmvxP75I722 s2FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=eQonxqUCnqGqv/YJhu6uvmxK+aLvOoWfACTka+eVdbM=; b=LH+bHhd1QHPv24FAaCLLNP7w98yTa2HWEIHY0COJ18DxmGoOnkwWIrHZGDTfRpR3Sr Y2RHlulZPoyl15BwPUu/cNFxsfMl8Ydn+clEzsP7mypw0JkSGg8V3Ujddnhksl0WL/wK OgztA+z3eBe6tZzjAlcxNdqnS+c7nfDMpxhZwsKMOVNZo3vynSqWd+5fyZodBqMMOQ9c jDgoQ2J0uuzTpIYutzTUGmteADNvyGD2wwr81QwOZnD5MHfdlxvoltRDL+6uEovXV573 ttVJZpxdbOIHFOsge0p/Df9IEfd4g51LAdsSAtHFI5I35WTTpdA/slqWUgMVrFIvjHyO 5LyA== X-Gm-Message-State: AElRT7EwCRzSo+pmXPM7HFdCr9TfaWfAxIrp3HDIG0QKRj4EAjVgJWji ffsgGU94p4YYZp+7JgjTkGBFfg== X-Google-Smtp-Source: AG47ELu+QWx3uhfbxleSa8kx3jL8Hx1QcCB0ayr+K2Z+9rJEpaFwnaZbPYL+lVuKRbdT4pwOajGEGw== X-Received: by 2002:a17:902:24c:: with SMTP id 70-v6mr44171696plc.384.1522143078336; Tue, 27 Mar 2018 02:31:18 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.31.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:31:17 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:26 +0800 Message-Id: <1522142971-20739-33-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 32/36] rockchip: remove rk_timer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We do not use rk_timer.c now, remove it. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- arch/arm/mach-rockchip/rk_timer.c | 48 --------------------------------------- 1 file changed, 48 deletions(-) delete mode 100644 arch/arm/mach-rockchip/rk_timer.c diff --git a/arch/arm/mach-rockchip/rk_timer.c b/arch/arm/mach-rockchip/rk_timer.c deleted file mode 100644 index 853b986..0000000 --- a/arch/arm/mach-rockchip/rk_timer.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE; - -static uint64_t rockchip_get_ticks(void) -{ - uint64_t timebase_h, timebase_l; - - timebase_l = readl(&timer_ptr->timer_curr_value0); - timebase_h = readl(&timer_ptr->timer_curr_value1); - - return timebase_h << 32 | timebase_l; -} - -static uint64_t usec_to_tick(unsigned int usec) -{ - uint64_t tick = usec; - tick *= CONFIG_SYS_TIMER_RATE / (1000 * 1000); - return tick; -} - -void rockchip_udelay(unsigned int usec) -{ - uint64_t tmp; - - /* get timestamp */ - tmp = rockchip_get_ticks() + usec_to_tick(usec); - - /* loop till event */ - while (rockchip_get_ticks() < tmp+1) - ; -} - -void rockchip_timer_init(void) -{ - writel(0xffffffff, &timer_ptr->timer_load_count0); - writel(0xffffffff, &timer_ptr->timer_load_count1); - writel(1, &timer_ptr->timer_ctrl_reg); -} From patchwork Tue Mar 27 09:29:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891490 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="C7L3eUlA"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409RC81X7fz9s1b for ; Tue, 27 Mar 2018 20:52:52 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C59B5C21FB3; Tue, 27 Mar 2018 09:44:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 864FDC22018; Tue, 27 Mar 2018 09:34:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 847BEC22092; Tue, 27 Mar 2018 09:31:26 +0000 (UTC) Received: from mail-pf0-f193.google.com (mail-pf0-f193.google.com [209.85.192.193]) by lists.denx.de (Postfix) with ESMTPS id DECF1C21FC8 for ; Tue, 27 Mar 2018 09:31:22 +0000 (UTC) Received: by mail-pf0-f193.google.com with SMTP id h69so3365211pfe.13 for ; Tue, 27 Mar 2018 02:31:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=hwDKQS2utIMYa6sqqLx8UnMq/fDeT5n4S7SQKkOYL70=; b=C7L3eUlAu/pIkArPQHD+MuJcGqn7nrv8udvw0X0ytfEmVjb1srHzxSoVK0oVGPf6ax nIe7xqAB/5BxgsA3nFYsAknp+8xdUSn4PFRxEUPFhExikZqmBhzxI2vAbGogvZbDkaeo DQW5Tv49CcEtJFcbnuYZRURjhNBaxt2uaKXogfY84FdRWHmsfx8T0zlO8FMNmpGumZp+ 22xkfFwdZDp+YAGJn6qpY45p/6lR299osys1P96/NaM4VaE/D73hrpw24ozSRSFYxYIY qjAtRzDA8yo7QyQR5sC1mURrI9JcFsjcxIqyU0Y6YiAS+KtIAJlR6x4XUl5ANGpyUOHf PJOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=hwDKQS2utIMYa6sqqLx8UnMq/fDeT5n4S7SQKkOYL70=; b=dGddWB0r5jKa50Opd7BC4JL3A8tj1d4hqfQyRG2oGY73SftnqCVMe/ej5kZfoEMSrQ OTWVj/bXx+h0q75RuebzwCjNoQrlw1XyO6IC9esjuiEBtLkA0S/UuT3E5X8bZ3eDlJtM jTgewztJKKZAcgWug+o8mwe7UL2HWjM9zx4l9Mw51I8Cbpl1P9jClvSsrYMJ77XLypJK j7Z0YFaSOCVFbWdfQkKi43OZSFi0pLUPubW4GXalH/wvGxztGt+bkF5gNaqb3kxWOveH P5IXgtfZ7ldD7vxTtBLSS9bKfxLJetCDVei+HTzD0vhEj/+kvhYtgftbqyx1+madWhIT IQZw== X-Gm-Message-State: AElRT7H9dt3NtHwlWAa1TSnuKo5MOzTLWTU0hNtUhSOwA+wxY2jsmEyu DWUlQOSdS68yPRpqkzfTt8RO8Q== X-Google-Smtp-Source: AG47ELuhgFSOiimrTZjkkvIQnfzdVDlvsUbS13z8tzgBLIE++M71OcyYKDwZiMzMZ1sIkSvcMUtuNw== X-Received: by 10.101.83.194 with SMTP id z2mr14111387pgr.133.1522143081206; Tue, 27 Mar 2018 02:31:21 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.31.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:31:20 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:27 +0800 Message-Id: <1522142971-20739-34-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Cc: Klaus Goger Subject: [U-Boot] [PATCH 33/36] rockchip: dts: rk3399-firefly: enable uart2 in spl X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" pre-loader console in SPL needs UART. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/dts/rk3399-firefly.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index f134c00..a007fa1 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -648,6 +648,7 @@ }; &uart2 { + u-boot,dm-pre-reloc; status = "okay"; }; From patchwork Tue Mar 27 09:29:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891484 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kDx1BYvi"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R6n5ywDz9s1b for ; Tue, 27 Mar 2018 20:49:05 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 82AB7C21FE1; Tue, 27 Mar 2018 09:41:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 69732C2203A; Tue, 27 Mar 2018 09:33:55 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0CB7FC21F79; Tue, 27 Mar 2018 09:31:31 +0000 (UTC) Received: from mail-pf0-f195.google.com (mail-pf0-f195.google.com [209.85.192.195]) by lists.denx.de (Postfix) with ESMTPS id B4DD0C21FB0 for ; Tue, 27 Mar 2018 09:31:25 +0000 (UTC) Received: by mail-pf0-f195.google.com with SMTP id a16so8638051pfn.9 for ; Tue, 27 Mar 2018 02:31:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=mQqRDrF/bB1WYZZXmhdCovMuymbn7HVRLvTpNZBI3RA=; b=kDx1BYvi0wXssmi7KXckIaWdI7SbAr8ehYa9q35SfV5Sb63jmY4+YItObDGahFajj+ ZU4aXutS88hJ+sgiVJjT7cO3NEiBbZhVEV0DD68hyls5FNUThfdwsblQUzdCj0QWbpSK +Lv0jR8vWwnCAzAd9aBMX9SCWQ28KxEJNK4yWoaFG/O91v+DIqN+KB6gPO9MRZrKbS+g oODtcERnZt1utjqg+OHcBWn6f9l7D39LwATNue9MZbLnyRLW7kCmdjkJEdRuayUcK2ET NFfd1Wpow2sMFxyWczA27pak+JlIc3nMdicTg6254tRplb42arkODAQgMdT/hLwrJl8D s3RQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=mQqRDrF/bB1WYZZXmhdCovMuymbn7HVRLvTpNZBI3RA=; b=W6T0NqknHtQ3FTd3aYMytAea25sIq253PaN8qkfFQc2sOOVFcpLAoU+u20hJYeNWDX zxS66XviP2fqmntEGJqfzK70I/B8+XZgOd4NuWuxsNVpRLk/y0ZnJzlUbfszF84BEH/v vdNaqqCQ58PxzqfXOrK4nY/sD8IaGGE2QnnLKwiOUzIjyDOlD2lUlEvR7Amd7MF13xi1 rQgivaYlbEC6iTwfsKJEVsPouobz2gt4MoJPpJm+KW1nWqM4u9NNipfvY7syv8q+UUby y72l5iNMtbVj7upUUb3ckl3dPtgTbn6WjIyvvR9H2Igm1n3JHxgDoBfztDz3GJovYNqW gDiA== X-Gm-Message-State: AElRT7EqBLrM8fBaRLJATXHBHpHFhmEcQX0ddWn1BZfp6WzhUeAr+XXi VIIKV2I9V/KEQz9A47RGMkmZ9g== X-Google-Smtp-Source: AG47ELsxmivF+Gr2ZEHY+FVQlrDCID/8D5+SMvttg+kyZ2ajA0XlJ57I/s7n+ma1vgQ0uSRT4o+0pg== X-Received: by 10.99.96.84 with SMTP id u81mr30946221pgb.231.1522143084009; Tue, 27 Mar 2018 02:31:24 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.31.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:31:23 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:28 +0800 Message-Id: <1522142971-20739-35-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 34/36] rockchip: spl-boot-order: do not enable with OF_PLATDATA X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The "fdt_*" functions may not enable even if the OF_CONTROL is enabled. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- arch/arm/mach-rockchip/spl-boot-order.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 843998d..cf4cc77 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -9,7 +9,7 @@ #include #include -#if CONFIG_IS_ENABLED(OF_CONTROL) +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) /** * spl_node_to_boot_device() - maps from a DT-node to a SPL boot device * @node: of_offset of the node From patchwork Tue Mar 27 09:29:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891489 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ENArbKuC"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R9j2Grdz9s1S for ; Tue, 27 Mar 2018 20:51:37 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E6C47C21FDC; Tue, 27 Mar 2018 09:40:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 49F88C22002; Tue, 27 Mar 2018 09:33:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1F2E6C21F98; Tue, 27 Mar 2018 09:31:33 +0000 (UTC) Received: from mail-pl0-f67.google.com (mail-pl0-f67.google.com [209.85.160.67]) by lists.denx.de (Postfix) with ESMTPS id 82DADC21FB1 for ; Tue, 27 Mar 2018 09:31:28 +0000 (UTC) Received: by mail-pl0-f67.google.com with SMTP id c11-v6so13747286plo.0 for ; Tue, 27 Mar 2018 02:31:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=f/hx6Mm+xofaBKnuyMrDfiXghQ+TKrFOf55cEOwLaxE=; b=ENArbKuC00bydwpfDaO0Dcd2+UBpYIspJtvKmfxSwV1nR5SzBoUHyrkVphzYhjiaPk 4I0KNi5uyseujax2ztCp+u4W6PvR94eXG2Ezcp5KzNvspJuq4gNd+c9RK1x0uEXuqh+3 rliGRYI5z8+f1tyHEK7PLuCt7jCHP5+SgQ203zgo3cLYLL76kt8j/MJhCgtf3jW8N5aw koAZijlY/5xyFYAM1G5zCtvKpKsB0i28SFsYxWLnssY7Oin8KyK3V8ZACyQzYUjTRYq7 iCO7yErJr0ZieVEZqpu35pLREjPr5sZTsMwx7cFeiv2Gva/0ZLbBJ8t82ZDWoRL9yDl3 Y9LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=f/hx6Mm+xofaBKnuyMrDfiXghQ+TKrFOf55cEOwLaxE=; b=UP8RAJLyBqzVCL9RCQ5Ip9K4Rp86nbu/X2IWChFTfZvMX8gKU+kgVK5Cq2TdYqp+HY CitI0gdogSHN5jv4Cno/SJWVtwZ8FM++Me9eP3BiCG5ih1oeTMLk7BvezgocymJb5iaL 4AIlUSsGmhHygk/K8HXUCvGIXMRfZmwWbR2k82e7fAld4dkeNOmq89nQddJT/nMFxf/1 dXIlBI7QNmj5AnM9TXmXdN0Os28Xd/f2x+DgYVarhH3Y1ZHFaAdjJh2q/ZNEs4SBDaLl TpYyhu94DVGVWAUdiqaKJYTuedljkMWiRNxhpGx+zCu6KrKG4dng4gpylDyTP0cAdTo1 c0QA== X-Gm-Message-State: AElRT7FMl45gdUCMTvjZkydQyXwUIn8YBDniRYeMlUce0U74Uz6Eb/uK 4gz8GSU/UOD7IMxUrFc7IRifGw== X-Google-Smtp-Source: AIpwx48hF1h2HFWbMK6J53BguXZQ/AKc4K1p/YyEAObhzsmynsJ+Nk6moY+Xyb6jd57n7ll14z/AZQ== X-Received: by 2002:a17:902:9045:: with SMTP id w5-v6mr9211538plz.287.1522143086737; Tue, 27 Mar 2018 02:31:26 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.31.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:31:25 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:29 +0800 Message-Id: <1522142971-20739-36-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 35/36] rockchip: declear boot_devices in bootrom.h X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" boot_devices may defined in soc file, and used in board file, we need to delear it in header file. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/bootrom.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h index 103b799..ac2f370 100644 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -53,6 +53,8 @@ enum { BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB }; +extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1]; + /** * Locations of the boot-device identifier in SRAM */ From patchwork Tue Mar 27 09:29:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891481 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="JPp1VZoF"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409R3y4FHkz9s1p for ; Tue, 27 Mar 2018 20:46:38 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 3AD83C21FD0; Tue, 27 Mar 2018 09:44:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7007EC22078; Tue, 27 Mar 2018 09:34:57 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7DCDCC2205D; Tue, 27 Mar 2018 09:31:41 +0000 (UTC) Received: from mail-pl0-f65.google.com (mail-pl0-f65.google.com [209.85.160.65]) by lists.denx.de (Postfix) with ESMTPS id 6F921C21FC3 for ; Tue, 27 Mar 2018 09:31:31 +0000 (UTC) Received: by mail-pl0-f65.google.com with SMTP id x4-v6so13736931pln.7 for ; Tue, 27 Mar 2018 02:31:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=25M8v49GkucnzfIT4TIrEvCxDtnAIXAKmpCOD20I92M=; b=JPp1VZoFMN+lBwKHtHFHO5OghWD0BpX4+J4XZRomblXezDBfqyNYeiR14LYiRUEm0I W51zGnnI+Ycz0FoAK7AJ3Tgemxr+dWpkupFRZdiXf22+cT6CdOl4u2SHxWtY/Dpz3/u+ GxLQ+XqBqpzMjr0d3FUKxP/HZ+D2hnMuc9Uw8oUKo+A42XLtssMkVgDLLIEXJdHV/WMH tgjIMmEVXAvLMakPakIEqgy/OLN6pd2Qa3dxru8KJhkE/409k12125frRw0DncPhawGW k8onzvYCCXsxT3HxgUjQE4LvhGI0tuGAZHYEr2d35AAmmhlv7ZlK1J1ejFu/iheGbozP 66Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=25M8v49GkucnzfIT4TIrEvCxDtnAIXAKmpCOD20I92M=; b=TRZ/2qO6DAW8m7kxY27vL8b1J/QDOTlsGk/0rDQq/aBNViMe4MHtKENo/EPi7Phkbw 3yfyt/DwJSZuv6K1Ffh+bgHgb4YLYT6enkJmteiEtl/M7oGVQkZ7eH4BEtIyg49yAtvo xj03Z/2z/Nsbw6AHVfJBjC5pawOalZ2LAp7vkYLuPpiWW0rY7ua8ujzodXHbz0Ri5mD8 9Niuk5eE0DUseHtP7Ci2u7BmGV44qr8pGavHP3n2RQ/Dr4kK9dyEK/rE4X/BH6rFcwkR kdkTV/EySiAq1icWzCumKNznFXiDaZyisvPG+acWTbHJwiouU+5IOOd9ROzY/OHUUAFw 5azQ== X-Gm-Message-State: AElRT7EpPBPpUQfCn47N1WY7VaGLhhDO+cFF+JXU8TEXTAyAXF9OUEMC k4IgIkmhy/YYmTugj57GLQNNlA== X-Google-Smtp-Source: AG47ELtiUadfJCtEBiC9Zk9bDU/RAjRDTEAC0blHEYbnH5X5j6/2yyI7R6kJG8dKWfrxggNaZtKaxQ== X-Received: by 2002:a17:902:724b:: with SMTP id c11-v6mr28859916pll.192.1522143089562; Tue, 27 Mar 2018 02:31:29 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.31.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:31:28 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:30 +0800 Message-Id: <1522142971-20739-37-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 36/36] rockchip: add common board file for rockchip platform X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We use common board/spl/tpl file for all rockchip SoCs, - all the SoC spec setting should move into SoC file like rk3288.c; - tpl is option and only purpose to init DRAM, clock, uart(option); - spl do secure relate one time init, boot device select, boot into U-Boot or trust or OS in falcon mode; - board do boot mode detect, enable regulator, usb init and so on. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/Makefile | 23 +---- arch/arm/mach-rockchip/board.c | 136 ++++++++++++++++++++++++++++ arch/arm/mach-rockchip/spl.c | 195 ++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/tpl.c | 111 +++++++++++++++++++++++ 4 files changed, 445 insertions(+), 20 deletions(-) create mode 100644 arch/arm/mach-rockchip/board.c create mode 100644 arch/arm/mach-rockchip/spl.c create mode 100644 arch/arm/mach-rockchip/tpl.c diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index e1b0519..3aba66c 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -11,15 +11,8 @@ obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o -obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o -obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o - -obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o -obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o +obj-tpl-y += tpl.o +obj-spl-y += spl.o spl-boot-order.o ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) @@ -28,21 +21,11 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # we can have the preprocessor correctly recognise both 0x0 and 0 # meaning "turn it off". obj-y += boot_mode.o - -obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o -obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o -obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o -obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o -obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o -obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o +obj-y += board.o endif obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o -ifndef CONFIG_ARM64 -obj-y += rk_timer.o -endif - obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/ ifndef CONFIG_TPL_BUILD diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c new file mode 100644 index 0000000..52c6f66 --- /dev/null +++ b/arch/arm/mach-rockchip/board.c @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_DM_REGULATOR +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_USB_FUNCTION_FASTBOOT) +int fb_set_reboot_flag(void) +{ + printf("Setting reboot to fastboot flag ...\n"); + /* Set boot mode to fastboot */ + writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG); + + return 0; +} + +#define FASTBOOT_KEY_GPIO 43 /* GPIO1_B3 */ +static int fastboot_key_pressed(void) +{ + gpio_request(FASTBOOT_KEY_GPIO, "fastboot_key"); + gpio_direction_input(FASTBOOT_KEY_GPIO); + return !gpio_get_value(FASTBOOT_KEY_GPIO); +} +#endif + +__weak int rk_board_init(void) +{ + return 0; +} + +__weak int rk_board_late_init(void) +{ + return 0; +} + +int board_late_init(void) +{ +#if defined(CONFIG_USB_FUNCTION_FASTBOOT) + if (fastboot_key_pressed()) { + printf("fastboot key pressed!\n"); + fb_set_reboot_flag(); + } +#endif + +#if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) + setup_boot_mode(); +#endif + + return rk_board_late_init(); +} + +int board_init(void) +{ + int ret; + +#if !defined(CONFIG_SUPPORT_SPL) + board_debug_uart_init(); +#endif +#ifdef CONFIG_DM_REGULATOR + ret = regulators_enable_boot_on(false); + if (ret) + debug("%s: Cannot enable boot on regulator\n", __func__); +#endif + + return rk_board_init(); +} + +#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif + +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#include +#include + +static struct dwc2_plat_otg_data otg_data = { + .rx_fifo_sz = 512, + .np_tx_fifo_sz = 16, + .tx_fifo_sz = 128, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + int node; + const char *mode; + bool matched = false; + const void *blob = gd->fdt_blob; + + /* find the usb_otg node */ + node = fdt_node_offset_by_compatible(blob, -1, + "snps,dwc2"); + + while (node > 0) { + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode && strcmp(mode, "otg") == 0) { + matched = true; + break; + } + + node = fdt_node_offset_by_compatible(blob, node, + "snps,dwc2"); + } + if (!matched) { + debug("Not found usb_otg device\n"); + return -ENODEV; + } + otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); + + return dwc2_udc_probe(&otg_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c new file mode 100644 index 0000000..3c10b63 --- /dev/null +++ b/arch/arm/mach-rockchip/spl.c @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define BROM_BOOTSOURCE_ID_ADDR (CONFIG_ROCKCHIP_IRAM_START_ADDR + 0x10) +void board_return_to_bootrom(void) +{ + back_to_bootrom(BROM_BOOT_NEXTSTAGE); +} + +__weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { +}; + +const char *board_spl_was_booted_from(void) +{ + u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); + const char *bootdevice_ofpath = NULL; + + if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) + bootdevice_ofpath = boot_devices[bootdevice_brom_id]; + + if (bootdevice_ofpath) + debug("%s: brom_bootdevice_id %x maps to '%s'\n", + __func__, bootdevice_brom_id, bootdevice_ofpath); + else + debug("%s: failed to resolve brom_bootdevice_id %x\n", + __func__, bootdevice_brom_id); + + return bootdevice_ofpath; +} + +u32 spl_boot_device(void) +{ + u32 boot_device = BOOT_DEVICE_MMC1; + +#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ + defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ + defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) + return BOOT_DEVICE_SPI; +#endif + if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) + return BOOT_DEVICE_BOOTROM; + + return boot_device; +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +__weak void rockchip_stimer_init(void) +{ +#ifndef CONFIG_ARM64 + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(COUNTER_FREQUENCY)); +#endif + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); +} + +__weak int arch_cpu_init(void) +{ + return 0; +} + +__weak int rk_board_init_f(void) +{ + return 0; +} + +void board_init_f(ulong dummy) +{ +#ifdef CONFIG_SPL_FRAMEWORK + int ret; +#if !defined(CONFIG_SUPPORT_TPL) + struct udevice *dev; +#endif +#endif + +#if !defined(CONFIG_SUPPORT_TPL) + rockchip_stimer_init(); + arch_cpu_init(); +#endif +#define EARLY_UART +#if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART) + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + printascii("U-Boot SPL board init"); +#endif + +#ifdef CONFIG_SPL_FRAMEWORK + ret = spl_early_init(); + if (ret) { + printf("spl_early_init() failed: %d\n", ret); + hang(); + } +#if !defined(CONFIG_SUPPORT_TPL) + debug("\nspl:init dram\n"); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("DRAM init failed: %d\n", ret); + return; + } +#endif + preloader_console_init(); +#else + /* Some SoCs like rk3036 does not use any frame work */ + sdram_init(); +#endif + + rk_board_init_f(); +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) + back_to_bootrom(BROM_BOOT_NEXTSTAGE); +#endif +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BOARD_INIT +__weak int rk_spl_board_init(void) +{ + return 0; +} + +static int setup_led(void) +{ +#ifdef CONFIG_SPL_LED + struct udevice *dev; + char *led_name; + int ret; + + led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); + if (!led_name) + return 0; + ret = led_get_by_label(led_name, &dev); + if (ret) { + debug("%s: get=%d\n", __func__, ret); + return ret; + } + ret = led_set_on(dev, 1); + if (ret) + return ret; +#endif + + return 0; +} + +void spl_board_init(void) +{ + int ret; + + ret = setup_led(); + + if (ret) { + debug("LED ret=%d\n", ret); + hang(); + } + + rk_spl_board_init(); +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) + back_to_bootrom(BROM_BOOT_NEXTSTAGE); +#endif +} +#endif diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c new file mode 100644 index 0000000..6f9fbaf --- /dev/null +++ b/arch/arm/mach-rockchip/tpl.c @@ -0,0 +1,111 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT +void puts(const char *str) +{ + while (*str) + putc(*str++); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), '\r'); + + NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c); +} +#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */ + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} + +__weak void rockchip_stimer_init(void) +{ +#ifndef CONFIG_ARM64 + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(COUNTER_FREQUENCY)); +#endif + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); +} + +__weak int arch_cpu_init(void) +{ + return 0; +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + /* + * Init the timer at the very beginning so that we can get more + * accurate value from timer_get_boot_us() + */ + rockchip_stimer_init(); + arch_cpu_init(); +#define EARLY_DEBUG +#ifdef EARLY_DEBUG + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " + U_BOOT_TIME ")\n"); +#endif + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + /* Init ARM arch timer */ + timer_init(); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("DRAM init failed: %d\n", ret); + return; + } + +#if defined(CONFIG_TPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_TPL_BOARD_INIT) + back_to_bootrom(BROM_BOOT_NEXTSTAGE); +#endif +} + +#ifndef CONFIG_SPL_FRAMEWORK +/* Place Holders */ +void board_init_r(gd_t *id, ulong dest_addr) +{ + /* + * Function attribute is no-return + * This Function never executes + */ + while (1) + ; +} +#endif