From patchwork Sun Jun 11 23:32:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1793716 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QfWNf01m7z20Vx for ; Mon, 12 Jun 2023 09:33:53 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3D9E4858CE; Mon, 12 Jun 2023 01:33:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 619D8847D6; Mon, 12 Jun 2023 01:33:31 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 96DF08479F for ; Mon, 12 Jun 2023 01:33:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4FDDC2F4; Sun, 11 Jun 2023 16:34:13 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2CD883F663; Sun, 11 Jun 2023 16:33:25 -0700 (PDT) From: Andre Przywara To: Jagan Teki Cc: Jernej Skrabec , Marek Vasut , Samuel Holland , Icenowy Zheng , Sam Edwards , =?utf-8?b?6Lev6L6J?= , u-boot@lists.denx.de, linux-sunxi@lists.linux.dev Subject: [PATCH v2 1/7] phy: sun4i-usb: Fix of_xlate() argument check Date: Mon, 12 Jun 2023 00:32:35 +0100 Message-Id: <20230611233241.14235-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20230611233241.14235-1-andre.przywara@arm.com> References: <20230611233241.14235-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean In its of_xlate() function, the Allwinner USB PHY driver compares the args_count variable against the number of implemented USB PHYs, although this is the *number of arguments* to the DT phandle property. Per the DT binding for this PHY device, this number is always one, so this check will always fail if the particular SoC implements exactly one USB PHY. So far this affected only the V3s (which has USB support disabled), but the F1C100s also sports one PHY only. Fix that check to compare args_count against exactly 1, and the args[0] content (requested PHY number) against the number of implemented PHYs. This fixes USB operation on the Allwinner V3s and allows to enable USB on the Allwinner F1C100s SoC. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/phy/allwinner/phy-sun4i-usb.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 6428163c188..dbea70f9a5e 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -372,7 +372,10 @@ static int sun4i_usb_phy_xlate(struct phy *phy, { struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev); - if (args->args_count >= data->cfg->num_phys) + if (args->args_count != 1) + return -EINVAL; + + if (args->args[0] >= data->cfg->num_phys) return -EINVAL; if (data->cfg->missing_phys & BIT(args->args[0])) From patchwork Sun Jun 11 23:32:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1793717 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QfWNt44YRz20Vx for ; Mon, 12 Jun 2023 09:34:06 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F39008479D; Mon, 12 Jun 2023 01:33:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id B74A585561; Mon, 12 Jun 2023 01:33:32 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 4A3168468E for ; Mon, 12 Jun 2023 01:33:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3BDF9AB6; Sun, 11 Jun 2023 16:34:15 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1AFF43F663; Sun, 11 Jun 2023 16:33:27 -0700 (PDT) From: Andre Przywara To: Jagan Teki Cc: Jernej Skrabec , Marek Vasut , Samuel Holland , Icenowy Zheng , Sam Edwards , =?utf-8?b?6Lev6L6J?= , u-boot@lists.denx.de, linux-sunxi@lists.linux.dev Subject: [PATCH v2 2/7] phy: sun4i-usb: add Allwinner F1C100s support Date: Mon, 12 Jun 2023 00:32:36 +0100 Message-Id: <20230611233241.14235-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20230611233241.14235-1-andre.przywara@arm.com> References: <20230611233241.14235-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The Allwinner F1C100s implements a single USB PHY, connected to its MUSB OTG controller. The USB PHY is of the simpler, older type (like the A10), the only real difference is that it's indeed only one PHY. Add a struct describing those F1C100s USB PHY properties, and connect it to the new compatible string. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/phy/allwinner/phy-sun4i-usb.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index dbea70f9a5e..2bf47fc36a7 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -648,6 +648,14 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = { .missing_phys = BIT(1) | BIT(2), }; +static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = { + .num_phys = 1, + .type = sun4i_a10_phy, + .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A10, + .dedicated_clocks = true, +}; + static const struct udevice_id sun4i_usb_phy_ids[] = { { .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg }, { .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg }, @@ -662,6 +670,7 @@ static const struct udevice_id sun4i_usb_phy_ids[] = { { .compatible = "allwinner,sun20i-d1-usb-phy", .data = (ulong)&sun20i_d1_cfg }, { .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg}, { .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg}, + { .compatible = "allwinner,suniv-f1c100s-usb-phy", .data = (ulong)&suniv_f1c100s_cfg }, { } }; From patchwork Sun Jun 11 23:32:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1793718 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QfWP72gSkz20Vx for ; Mon, 12 Jun 2023 09:34:19 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 17ED184704; Mon, 12 Jun 2023 01:33:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 8CC2D847D6; Mon, 12 Jun 2023 01:33:36 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 66CED847D6 for ; Mon, 12 Jun 2023 01:33:32 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 32087C14; Sun, 11 Jun 2023 16:34:17 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 074943F663; Sun, 11 Jun 2023 16:33:29 -0700 (PDT) From: Andre Przywara To: Jagan Teki Cc: Jernej Skrabec , Marek Vasut , Samuel Holland , Icenowy Zheng , Sam Edwards , =?utf-8?b?6Lev6L6J?= , u-boot@lists.denx.de, linux-sunxi@lists.linux.dev Subject: [PATCH v2 3/7] sunxi: Kconfig: rework PHY_USB_SUN4I selection Date: Mon, 12 Jun 2023 00:32:37 +0100 Message-Id: <20230611233241.14235-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20230611233241.14235-1-andre.przywara@arm.com> References: <20230611233241.14235-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean At the moment we use "select" in each Allwinner SoC's Kconfig section to include the USB PHY driver in the build. This means it cannot be disabled via Kconfig, although USB is not really a strictly required core functionality, and a particular board might not even include USB ports. Rework the Kconfig part by removing the "select" lines for each SoC's section, and instead letting it default to "y" in the PHY driver section itself. We use "depends on !" to exclude the few SoCs we don't support (yet). The Allwinner V3s does not enable USB (PHY) support at the moment, even though it should work: let the PHY default to "n" to keep the current behaviour. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec Tested-by: Sam Edwards --- arch/arm/mach-sunxi/Kconfig | 11 ----------- drivers/phy/allwinner/Kconfig | 6 +++++- 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 6dcbb096f74..e0b1bde35a9 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -207,7 +207,6 @@ endif config MACH_SUNXI_H3_H5 bool - select PHY_SUN4I_USB select SUNXI_DE2 select SUNXI_DRAM_DW select SUNXI_DRAM_DW_32BIT @@ -236,7 +235,6 @@ config MACH_SUNIV config MACH_SUN4I bool "sun4i (Allwinner A10)" select CPU_V7A - select PHY_SUN4I_USB select DRAM_SUN4I select SUNXI_GEN_SUN4I select SUPPORT_SPL @@ -247,7 +245,6 @@ config MACH_SUN5I bool "sun5i (Allwinner A13)" select CPU_V7A select DRAM_SUN4I - select PHY_SUN4I_USB select SUNXI_GEN_SUN4I select SUPPORT_SPL imply SPL_SYS_I2C_LEGACY @@ -261,7 +258,6 @@ config MACH_SUN6I select ARCH_SUPPORT_PSCI select SPL_ARMV7_SET_CORTEX_SMPEN select DRAM_SUN6I - select PHY_SUN4I_USB select SPL_I2C select SUN6I_PRCM select SUNXI_GEN_SUN6I @@ -277,7 +273,6 @@ config MACH_SUN7I select ARCH_SUPPORT_PSCI select SPL_ARMV7_SET_CORTEX_SMPEN select DRAM_SUN4I - select PHY_SUN4I_USB select SUNXI_GEN_SUN4I select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT @@ -291,7 +286,6 @@ config MACH_SUN8I_A23 select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI select DRAM_SUN8I_A23 - select PHY_SUN4I_USB select SPL_I2C select SUNXI_GEN_SUN6I select SUPPORT_SPL @@ -305,7 +299,6 @@ config MACH_SUN8I_A33 select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI select DRAM_SUN8I_A33 - select PHY_SUN4I_USB select SPL_I2C select SUNXI_GEN_SUN6I select SUPPORT_SPL @@ -316,7 +309,6 @@ config MACH_SUN8I_A83T bool "sun8i (Allwinner A83T)" select CPU_V7A select DRAM_SUN8I_A83T - select PHY_SUN4I_USB select SPL_I2C select SUNXI_GEN_SUN6I select MMC_SUNXI_HAS_NEW_MODE @@ -344,7 +336,6 @@ config MACH_SUN8I_R40 select SUPPORT_SPL select SUNXI_DRAM_DW select SUNXI_DRAM_DW_32BIT - select PHY_SUN4I_USB imply SPL_SYS_I2C_LEGACY config MACH_SUN8I_V3S @@ -372,7 +363,6 @@ config MACH_SUN9I config MACH_SUN50I bool "sun50i (Allwinner A64)" select ARM64 - select PHY_SUN4I_USB select SUN6I_PRCM select SUNXI_DE2 select SUNXI_GEN_SUN6I @@ -395,7 +385,6 @@ config MACH_SUN50I_H5 config MACH_SUN50I_H6 bool "sun50i (Allwinner H6)" select ARM64 - select PHY_SUN4I_USB select DRAM_SUN50I_H6 select SUN50I_GEN_H6 diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig index f8f1e99c4f5..565b4617b01 100644 --- a/drivers/phy/allwinner/Kconfig +++ b/drivers/phy/allwinner/Kconfig @@ -4,6 +4,10 @@ config PHY_SUN4I_USB bool "Allwinner Sun4I USB PHY driver" depends on ARCH_SUNXI + depends on !MACH_SUN9I + depends on !MACH_SUN50I_H616 + default n if MACH_SUN8I_V3S + default y select DM_REGULATOR select PHY help @@ -11,7 +15,7 @@ config PHY_SUN4I_USB sunxi SoCs. This driver controls the entire USB PHY block, both the USB OTG - parts, as well as the 2 regular USB 2 host PHYs. + parts, as well as the regular USB HCI host PHYs. config INITIAL_USB_SCAN_DELAY int "Delay initial USB scan by x ms to allow builtin devices to init" From patchwork Sun Jun 11 23:32:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1793719 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QfWPN1RmKz20Vx for ; Mon, 12 Jun 2023 09:34:32 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C5BA88476C; Mon, 12 Jun 2023 01:33:54 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 6E11B8479D; Mon, 12 Jun 2023 01:33:39 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id B497A85787 for ; Mon, 12 Jun 2023 01:33:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4A5EFD75; Sun, 11 Jun 2023 16:34:19 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F0E1B3F663; Sun, 11 Jun 2023 16:33:31 -0700 (PDT) From: Andre Przywara To: Jagan Teki Cc: Jernej Skrabec , Marek Vasut , Samuel Holland , Icenowy Zheng , Sam Edwards , =?utf-8?b?6Lev6L6J?= , u-boot@lists.denx.de, linux-sunxi@lists.linux.dev Subject: [PATCH v2 4/7] phy: sun4i-usb: Replace types with explicit quirk flags Date: Mon, 12 Jun 2023 00:32:38 +0100 Message-Id: <20230611233241.14235-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20230611233241.14235-1-andre.przywara@arm.com> References: <20230611233241.14235-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean So far we were assigning some crude "type" (SoC name, really) to each Allwinner USB PHY model, then guarding certain quirks based on this. This does not only look weird, but gets more or more cumbersome to maintain. Remove the bogus type names altogether, instead introduce flags for each quirk, and explicitly check for them. This improves readability, and simplifies future extensions. Port of Linux patch 8dd256bae653. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/phy/allwinner/phy-sun4i-usb.c | 41 ++++++--------------------- 1 file changed, 9 insertions(+), 32 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 2bf47fc36a7..88c1a3dc84a 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -73,26 +73,15 @@ #define MAX_PHYS 4 -enum sun4i_usb_phy_type { - sun4i_a10_phy, - sun6i_a31_phy, - sun8i_a33_phy, - sun8i_a83t_phy, - sun8i_h3_phy, - sun8i_r40_phy, - sun8i_v3s_phy, - sun50i_a64_phy, - sun50i_h6_phy, -}; - struct sun4i_usb_phy_cfg { int num_phys; - enum sun4i_usb_phy_type type; + int hsic_index; u32 disc_thresh; u32 hci_phy_ctl_clear; u8 phyctl_offset; bool dedicated_clocks; bool phy0_dual_route; + bool siddq_in_base; int missing_phys; }; @@ -200,7 +189,7 @@ static void sun4i_usb_phy_passby(struct phy *phy, bool enable) SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN; /* A83T USB2 is HSIC */ - if (data->cfg->type == sun8i_a83t_phy && usb_phy->id == 2) + if (data->cfg->hsic_index && usb_phy->id == data->cfg->hsic_index) bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT | SUNXI_HSIC; @@ -289,8 +278,7 @@ static int sun4i_usb_phy_init(struct phy *phy) writel(val, usb_phy->pmu + REG_HCI_PHY_CTL); } - if (data->cfg->type == sun8i_a83t_phy || - data->cfg->type == sun50i_h6_phy) { + if (data->cfg->siddq_in_base) { if (phy->id == 0) { val = readl(data->base + data->cfg->phyctl_offset); val |= PHY_CTL_VBUSVLDEXT; @@ -339,8 +327,7 @@ static int sun4i_usb_phy_exit(struct phy *phy) int ret; if (phy->id == 0) { - if (data->cfg->type == sun8i_a83t_phy || - data->cfg->type == sun50i_h6_phy) { + if (data->cfg->siddq_in_base) { void __iomem *phyctl = data->base + data->cfg->phyctl_offset; @@ -536,7 +523,6 @@ static int sun4i_usb_phy_probe(struct udevice *dev) static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = { .num_phys = 3, - .type = sun4i_a10_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = false, @@ -544,7 +530,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = { static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = { .num_phys = 2, - .type = sun4i_a10_phy, .disc_thresh = 2, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = false, @@ -552,7 +537,6 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = { static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = { .num_phys = 3, - .type = sun6i_a31_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = true, @@ -560,7 +544,6 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = { static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = { .num_phys = 3, - .type = sun4i_a10_phy, .disc_thresh = 2, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = false, @@ -568,7 +551,6 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = { static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = { .num_phys = 2, - .type = sun4i_a10_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = true, @@ -576,7 +558,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = { static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = { .num_phys = 2, - .type = sun8i_a33_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, @@ -584,14 +565,14 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = { static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = { .num_phys = 3, - .type = sun8i_a83t_phy, + .hsic_index = 2, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, + .siddq_in_base = true, }; static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { .num_phys = 4, - .type = sun8i_h3_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, @@ -601,7 +582,6 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = { .num_phys = 3, - .type = sun8i_r40_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, @@ -611,7 +591,6 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = { static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = { .num_phys = 1, - .type = sun8i_v3s_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, @@ -621,16 +600,15 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = { static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = { .num_phys = 2, - .type = sun50i_h6_phy, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, .hci_phy_ctl_clear = PHY_CTL_SIDDQ, .phy0_dual_route = true, + .siddq_in_base = true, }; static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = { .num_phys = 2, - .type = sun50i_a64_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, @@ -640,17 +618,16 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = { static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = { .num_phys = 4, - .type = sun50i_h6_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, .phy0_dual_route = true, + .siddq_in_base = true, .missing_phys = BIT(1) | BIT(2), }; static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = { .num_phys = 1, - .type = sun4i_a10_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = true, From patchwork Sun Jun 11 23:32:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1793720 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QfWPd1y8tz20Vx for ; Mon, 12 Jun 2023 09:34:45 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9C9CF8591B; Mon, 12 Jun 2023 01:33:56 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 6EAB685893; Mon, 12 Jun 2023 01:33:40 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 55EE785C5A for ; Mon, 12 Jun 2023 01:33:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 43EED1FB; Sun, 11 Jun 2023 16:34:21 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1506A3F663; Sun, 11 Jun 2023 16:33:33 -0700 (PDT) From: Andre Przywara To: Jagan Teki Cc: Jernej Skrabec , Marek Vasut , Samuel Holland , Icenowy Zheng , Sam Edwards , =?utf-8?b?6Lev6L6J?= , u-boot@lists.denx.de, linux-sunxi@lists.linux.dev Subject: [PATCH v2 5/7] phy: sun4i-usb: Add H616 USB PHY quirk support Date: Mon, 12 Jun 2023 00:32:39 +0100 Message-Id: <20230611233241.14235-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20230611233241.14235-1-andre.przywara@arm.com> References: <20230611233241.14235-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The H616 USB PHY is some kind of special snowflake: Only port2 works out of the box, but all other ports need some help from this port2 to work correctly: The CLK_BUS_PHY2 and RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in the PMU PHY control register needs to be cleared. For this register to be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask .... Follow the respective Linux patch (b45c6d80325b) and add a quirk bit, triggering the special sequence as outlined above, for PHYs other than PHY2: ungate this one special clock, and clear the SIDDQ bit. We also pick the clock and reset from PHY2 and enable them as well. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/phy/allwinner/phy-sun4i-usb.c | 46 +++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 88c1a3dc84a..c81811a7522 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -82,6 +82,7 @@ struct sun4i_usb_phy_cfg { bool dedicated_clocks; bool phy0_dual_route; bool siddq_in_base; + bool needs_phy2_siddq; int missing_phys; }; @@ -118,6 +119,7 @@ struct sun4i_usb_phy_plat { struct gpio_desc gpio_vbus_det; struct gpio_desc gpio_id_det; struct clk clocks; + struct clk clk2; struct reset_ctl resets; int id; }; @@ -272,6 +274,41 @@ static int sun4i_usb_phy_init(struct phy *phy) return ret; } + /* Some PHYs on some SoCs (the H616) need the help of PHY2 to work. */ + if (data->cfg->needs_phy2_siddq && phy->id != 2) { + struct sun4i_usb_phy_plat *phy2 = &data->usb_phy[2]; + + ret = clk_enable(&phy2->clocks); + if (ret) { + dev_err(phy->dev, "failed to enable aux clock\n"); + return ret; + } + + ret = reset_deassert(&phy2->resets); + if (ret) { + dev_err(phy->dev, "failed to deassert aux reset\n"); + return ret; + } + + /* + * This extra clock is just needed to access the + * REG_HCI_PHY_CTL PMU register for PHY2. + */ + ret = clk_enable(&phy2->clk2); + if (ret) { + dev_err(phy->dev, "failed to enable PHY2 clock\n"); + return ret; + } + + if (phy2->pmu && data->cfg->hci_phy_ctl_clear) { + val = readl(phy2->pmu + REG_HCI_PHY_CTL); + val &= ~data->cfg->hci_phy_ctl_clear; + writel(val, phy2->pmu + REG_HCI_PHY_CTL); + } + + clk_disable(&phy2->clk2); + } + if (usb_phy->pmu && data->cfg->hci_phy_ctl_clear) { val = readl(usb_phy->pmu + REG_HCI_PHY_CTL); val &= ~data->cfg->hci_phy_ctl_clear; @@ -500,6 +537,15 @@ static int sun4i_usb_phy_probe(struct udevice *dev) return ret; } + /* Helper clock from PHY2 for the H616 PHY quirk */ + snprintf(name, sizeof(name), "pmu%d_clk", i); + ret = clk_get_by_name_optional(dev, name, &phy->clk2); + if (ret) { + dev_err(dev, "failed to get pmu%d_clk clock phandle\n", + i); + return ret; + } + snprintf(name, sizeof(name), "usb%d_reset", i); ret = reset_get_by_name(dev, name, &phy->resets); if (ret) { From patchwork Sun Jun 11 23:32:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1793721 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QfWPt3scPz20Vx for ; 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spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 312BDC14; Sun, 11 Jun 2023 16:34:23 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0DB6F3F663; Sun, 11 Jun 2023 16:33:35 -0700 (PDT) From: Andre Przywara To: Jagan Teki Cc: Jernej Skrabec , Marek Vasut , Samuel Holland , Icenowy Zheng , Sam Edwards , =?utf-8?b?6Lev6L6J?= , u-boot@lists.denx.de, linux-sunxi@lists.linux.dev Subject: [PATCH v2 6/7] phy: sun4i: Add H616 USB PHY support Date: Mon, 12 Jun 2023 00:32:40 +0100 Message-Id: <20230611233241.14235-7-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20230611233241.14235-1-andre.przywara@arm.com> References: <20230611233241.14235-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Now that the Allwinner USB PHY driver supports the H616 quirk, let's enable support for USB ports on that SoC. We connect the compatible string to a new struct describing the SoCs USB PHY properties, and unblock the PHY driver selection in Kconfig. A later patch will enable USB support in the H616 boards' defconfigs. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/phy/allwinner/Kconfig | 1 - drivers/phy/allwinner/phy-sun4i-usb.c | 12 ++++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig index 565b4617b01..bb0bd8d5f81 100644 --- a/drivers/phy/allwinner/Kconfig +++ b/drivers/phy/allwinner/Kconfig @@ -5,7 +5,6 @@ config PHY_SUN4I_USB bool "Allwinner Sun4I USB PHY driver" depends on ARCH_SUNXI depends on !MACH_SUN9I - depends on !MACH_SUN50I_H616 default n if MACH_SUN8I_V3S default y select DM_REGULATOR diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index c81811a7522..77dffcad884 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -672,6 +672,17 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = { .missing_phys = BIT(1) | BIT(2), }; +static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = { + .num_phys = 4, + .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, + .phy0_dual_route = true, + .hci_phy_ctl_clear = PHY_CTL_SIDDQ, + .needs_phy2_siddq = true, + .siddq_in_base = true, +}; + static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = { .num_phys = 1, .disc_thresh = 3, @@ -693,6 +704,7 @@ static const struct udevice_id sun4i_usb_phy_ids[] = { { .compatible = "allwinner,sun20i-d1-usb-phy", .data = (ulong)&sun20i_d1_cfg }, { .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg}, { .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg}, + { .compatible = "allwinner,sun50i-h616-usb-phy", .data = (ulong)&sun50i_h616_cfg }, { .compatible = "allwinner,suniv-f1c100s-usb-phy", .data = (ulong)&suniv_f1c100s_cfg }, { } }; From patchwork Sun Jun 11 23:32:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1793722 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QfWQ82x2Xz20QH for ; Mon, 12 Jun 2023 09:35:12 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 20517860C3; Mon, 12 Jun 2023 01:34:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id ED8C98476C; Mon, 12 Jun 2023 01:33:43 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 2EABC857DF for ; Mon, 12 Jun 2023 01:33:40 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 201482F4; Sun, 11 Jun 2023 16:34:25 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F0A823F663; Sun, 11 Jun 2023 16:33:37 -0700 (PDT) From: Andre Przywara To: Jagan Teki Cc: Jernej Skrabec , Marek Vasut , Samuel Holland , Icenowy Zheng , Sam Edwards , =?utf-8?b?6Lev6L6J?= , u-boot@lists.denx.de, linux-sunxi@lists.linux.dev Subject: [PATCH v2 7/7] sunxi: H616: enable USB support for H616 boards Date: Mon, 12 Jun 2023 00:32:41 +0100 Message-Id: <20230611233241.14235-8-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20230611233241.14235-1-andre.przywara@arm.com> References: <20230611233241.14235-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Now that the PHY driver supports the H616 USB PHY, we can enable USB support for the two H616 boards. As the OrangePi Zero2 has a USB-C port hard-wired to peripheral mode, let's enable USB gadget mode for port 0, so people can use fastboot, ethernet or mass storage functionality. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- configs/orangepi_zero2_defconfig | 3 +++ configs/x96_mate_defconfig | 2 ++ 2 files changed, 5 insertions(+) diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index 6cb942f511a..4178ee6a286 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -19,3 +19,6 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y CONFIG_SPI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig index 122c1a99e32..32ef0a42ee2 100644 --- a/configs/x96_mate_defconfig +++ b/configs/x96_mate_defconfig @@ -18,3 +18,5 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y