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[61.227.119.36]) by smtp.gmail.com with ESMTPSA id 24-20020a631658000000b0051f15beba7fsm8211229pgw.67.2023.05.30.02.27.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 02:27:50 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 1/2][SRU][Lunar] drm/amdgpu: refine get gpu clock counter method Date: Tue, 30 May 2023 17:25:41 +0800 Message-Id: <20230530092542.1239871-2-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230530092542.1239871-1-vicamo.yang@canonical.com> References: <20230530092542.1239871-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.173; envelope-from=vicamo@gmail.com; helo=mail-pg1-f173.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Deucher , Tong Liu01 , Luben Tuikov Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Tong Liu01 BugLink: https://bugs.launchpad.net/bugs/2020685 [why] regGOLDEN_TSC_COUNT_LOWER/regGOLDEN_TSC_COUNT_UPPER are protected and unaccessible under sriov. The clock counter high bit may update during reading process. [How] Replace regGOLDEN_TSC_COUNT_LOWER/regGOLDEN_TSC_COUNT_UPPER with regCP_MES_MTIME_LO/regCP_MES_MTIME_HI to get gpu clock under sriov. Refine get gpu clock counter method to make the result more precise. Signed-off-by: Tong Liu01 Acked-by: Luben Tuikov Signed-off-by: Alex Deucher (cherry picked from commit 5591a051b86be170a84943698ab140342602ff7b) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index ddb7b8651ab4..2e1c67cfc1bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4641,11 +4641,24 @@ static int gfx_v11_0_post_soft_reset(void *handle) static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) { uint64_t clock; + uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; amdgpu_gfx_off_ctrl(adev, false); mutex_lock(&adev->gfx.gpu_clock_mutex); - clock = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER) | - ((uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER) << 32ULL); + if (amdgpu_sriov_vf(adev)) { + clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); + clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); + clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); + if (clock_counter_hi_pre != clock_counter_hi_after) + clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); + } else { + clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); + clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); + clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); + if (clock_counter_hi_pre != clock_counter_hi_after) + clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); + } + clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); mutex_unlock(&adev->gfx.gpu_clock_mutex); amdgpu_gfx_off_ctrl(adev, true); return clock; From patchwork Tue May 30 09:25:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1787371 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QVnBY5bTVz20Q4 for ; Tue, 30 May 2023 19:28:21 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1q3veJ-0000Fe-Nl; Tue, 30 May 2023 09:28:15 +0000 Received: from mail-pf1-f175.google.com ([209.85.210.175]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1q3veH-0000DE-OG for kernel-team@lists.ubuntu.com; Tue, 30 May 2023 09:28:13 +0000 Received: by mail-pf1-f175.google.com with SMTP id d2e1a72fcca58-64d2467d640so4890251b3a.1 for ; Tue, 30 May 2023 02:28:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685438891; x=1688030891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aYjlsvTneI3m29TkkHy6W/pxFdY2fodDXCgmP71vB1Q=; b=JfqKRCason56i0cc4uCLBs0OC97TOiFwLqTAY4/w/YvYKZVyveVC6VmnLpyACG2i/C Wm2t+clX/iQWGrXxijaqTbNenbw6+za+0WWk/kpwOgYbHmTqaXaf8OvGy+EVs61+WZFt K1r1/YqJUUEPbO4CfgBPZ9mKMMN/4fwAU4+FXJF1xsiO5C+L9k+TeN2ubJFULxNLt5zP UYcDCGeLb0qc3hio3oHYvhrIcYgwNnwBgFDuYcfJahuLtQJGR/c8ypDnZqcDdlS1PLQD wGFvqiAT0xpHMMjRg4eTR47oNHC9iEtbMCtkv7qUwkoZaOW7Ab31VL+8yCp+sIZSH2sh 0Q0w== X-Gm-Message-State: AC+VfDwkwLfVNhOgubynH+wnYTbAmSEActVsYPcWUaytIKtDTQrQFkc1 RQIvDXa1WL/VLsTbkLAhEGnViiKmmZY= X-Google-Smtp-Source: ACHHUZ6NxzRoZBNxsQOYKY9iTBZFd2d8iF24vCJd/D+MWociyqeapHLGMN0oqSW/BFY6746xe4ceuQ== X-Received: by 2002:a05:6a00:2351:b0:643:9e7c:3829 with SMTP id j17-20020a056a00235100b006439e7c3829mr2109634pfj.12.1685438891577; Tue, 30 May 2023 02:28:11 -0700 (PDT) Received: from localhost.localdomain (61-227-119-36.dynamic-ip.hinet.net. [61.227.119.36]) by smtp.gmail.com with ESMTPSA id 24-20020a631658000000b0051f15beba7fsm8211229pgw.67.2023.05.30.02.28.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 02:28:11 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 2/2][SRU][Lunar] drm/amdgpu/gfx11: update gpu_clock_counter logic Date: Tue, 30 May 2023 17:25:42 +0800 Message-Id: <20230530092542.1239871-3-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230530092542.1239871-1-vicamo.yang@canonical.com> References: <20230530092542.1239871-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.175; envelope-from=vicamo@gmail.com; helo=mail-pf1-f175.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Deucher , stable@vger.kernel.org, Hawking Zhang Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Alex Deucher BugLink: https://bugs.launchpad.net/bugs/2020685 This code was written prior to previous updates to this logic for other chips. The RSC registers are part of SMUIO which is an always on block so there is no need to disable gfxoff. Additionally add the carryover and preemption checks. v2: rebase Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 6.1.y: 5591a051b86b: drm/amdgpu: refine get gpu clock counter method Cc: stable@vger.kernel.org # 6.2.y: 5591a051b86b: drm/amdgpu: refine get gpu clock counter method Cc: stable@vger.kernel.org # 6.3.y: 5591a051b86b: drm/amdgpu: refine get gpu clock counter method (cherry picked from commit d5aa417808cf14c052ca042920b3c6b9f1dc6aa4) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 2e1c67cfc1bd..bfba3f20e460 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4643,24 +4643,27 @@ static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) uint64_t clock; uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; - amdgpu_gfx_off_ctrl(adev, false); - mutex_lock(&adev->gfx.gpu_clock_mutex); if (amdgpu_sriov_vf(adev)) { + amdgpu_gfx_off_ctrl(adev, false); + mutex_lock(&adev->gfx.gpu_clock_mutex); clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); if (clock_counter_hi_pre != clock_counter_hi_after) clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); + mutex_unlock(&adev->gfx.gpu_clock_mutex); + amdgpu_gfx_off_ctrl(adev, true); } else { + preempt_disable(); clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); if (clock_counter_hi_pre != clock_counter_hi_after) clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); + preempt_enable(); } clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); - mutex_unlock(&adev->gfx.gpu_clock_mutex); - amdgpu_gfx_off_ctrl(adev, true); + return clock; }