From patchwork Tue May 23 19:46:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jivan Hakobyan X-Patchwork-Id: 1785387 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=jm1XWOLd; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QQlGN2fhXz2020 for ; Wed, 24 May 2023 05:47:40 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0EF3D3858423 for ; Tue, 23 May 2023 19:47:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0EF3D3858423 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1684871258; bh=nDMbnYBykgQVWTR01YvOF3xb1TDZef0jIanW71rP7NM=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=jm1XWOLdQgw3N6akST0hYdGQmsI/aaY8V93Rrjw/tXHJGGgepqLbU6Hb5T9q8aKpD 3cKmEZIPGOCKe8rdiS2ajQsQxi0Xl1swrc7S6a+d9bhkHwHYgV6wQ0BRt1F762F4Fn QMgPV2qi57iBvjaV8xLFIijRXnng/sxN+ASaV8GA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by sourceware.org (Postfix) with ESMTPS id 3BF793858D37 for ; Tue, 23 May 2023 19:47:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3BF793858D37 Received: by mail-pg1-x536.google.com with SMTP id 41be03b00d2f7-53202149ae2so2102a12.3 for ; Tue, 23 May 2023 12:47:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684871236; x=1687463236; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=Q2FyH7CLQ0r5CWvqsID9lEY0VKuRESLI+rXUB9wwwIM=; b=VObD3r9dO8zptTq15dwnjZIozMbGNpdjbH38BjXQ3tCGQ2v4trBSD5UBbRTyjFvwjl Ge3qwqnJ6+fDOK+RxjWLZuWaA3RlBS8j8qzznRcYtMzHOuKBupvDLPHfaSA+80o0mBcR BTwdriyjmrMO/p2Jfd2ihRBE0fcMa63xP9KEi1+MO0z4bmLofYuHnt3iQYe3shxt1flb yPeEMBX0gGFCssUqhytP5zjcirmQ/4STCd2AnNa+nXytgklPspsSauevhiTatt66Tgcc 50gv8am6+t8zMSlAM1QFnj9x+LYWsBclBiiu+X9nEliQgkcexkh8B/W7HRr9VbL/VJ2Z /n1Q== X-Gm-Message-State: AC+VfDxCkrGl8qSuuNwy5xxRN3C4Q+qVQf6R4BTCU5Uuwzqg1CMvW0kE njXhVUpcQntkLPLVqt0DElv1hdy0g9gudbTosfFD/OAfofY= X-Google-Smtp-Source: ACHHUZ7fxj9XkRkfMeDhORJYUL+5xLRe1n2ljJaIV7hL3Hyy4JbsLBeAj2L5g4KzQqLb2Dcs5Ox6eT/9Mi+Sn+wPhYI= X-Received: by 2002:a17:90a:420b:b0:24c:5e6:7035 with SMTP id o11-20020a17090a420b00b0024c05e67035mr13991878pjg.30.1684871235682; Tue, 23 May 2023 12:47:15 -0700 (PDT) MIME-Version: 1.0 Date: Tue, 23 May 2023 23:46:59 +0400 Message-ID: Subject: RISC-V: Use extension instructions instead of bitwise "and" To: gcc-patches@gcc.gnu.org X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, HTML_MESSAGE, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jivan Hakobyan via Gcc-patches From: Jivan Hakobyan Reply-To: Jivan Hakobyan Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" In the case where the target supports extension instructions, it is preferable to use that instead of doing the same in other ways. For the following case void foo (unsigned long a, unsigned long* ptr) { ptr[0] = a & 0xffffffffUL; ptr[1] &= 0xffffffffUL; } GCC generates foo: li a5,-1 srli a5,a5,32 and a0,a0,a5 sd a0,0(a1) ld a4,8(a1) and a5,a4,a5 sd a5,8(a1) ret but it will be profitable to generate this one foo: zext.w a0,a0 sd a0,0(a1) lwu a5,8(a1) sd a5,8(a1) ret This patch fixes mentioned issue. It supports HI -> DI, HI->SI and SI -> DI extensions. gcc/ChangeLog: * config/riscv/riscv.md (and3): New expander. (*and3) New pattern. * config/riscv/predicates.md (arith_operand_or_mode_mask): New predicate. gcc/testsuite/ChangeLog: * gcc.target/riscv/and-extend-1.c: New test * gcc.target/riscv/and-extend-2.c: New test diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index ffcbb9a7589..70f570153ae 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -27,6 +27,12 @@ (ior (match_operand 0 "const_arith_operand") (match_operand 0 "register_operand"))) +(define_predicate "arith_operand_or_mode_mask" + (ior (match_operand 0 "arith_operand") + (and (match_code "const_int") + (match_test "INTVAL (op) == GET_MODE_MASK (HImode) + || INTVAL (op) == GET_MODE_MASK (SImode)")))) + (define_predicate "lui_operand" (and (match_code "const_int") (match_test "LUI_OPERAND (INTVAL (op))"))) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 124d8c95804..33336492812 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1342,9 +1342,46 @@ ;; For RV64, we don't expose the SImode operations to the rtl expanders, ;; but SImode versions exist for combine. +(define_expand "and3" + [(set (match_operand:X 0 "register_operand") + (and:X (match_operand:X 1 "register_operand") + (match_operand:X 2 "arith_operand_or_mode_mask")))] + "" +{ + if (CONST_INT_P (operands[2])) + { + enum machine_mode tmode = VOIDmode; + if (INTVAL (operands[2]) == GET_MODE_MASK (HImode)) + tmode = HImode; + else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode)) + tmode = SImode; + + if (tmode != VOIDmode) + { + rtx tmp = gen_lowpart (tmode, operands[1]); + emit_insn (gen_extend_insn (operands[0], tmp, mode, tmode, 1)); + DONE; + } + } + else + { + emit_move_insn (operands[0], gen_rtx_AND (mode, operands[1], operands[2])); + DONE; + } +}) + +(define_insn "*and3" + [(set (match_operand:X 0 "register_operand" "=r,r") + (and:X (match_operand:X 1 "register_operand" "%r,r") + (match_operand:X 2 "arith_operand" " r,I")))] + "" + "and%i2\t%0,%1,%2" + [(set_attr "type" "logical") + (set_attr "mode" "")]) + (define_insn "3" [(set (match_operand:X 0 "register_operand" "=r,r") - (any_bitwise:X (match_operand:X 1 "register_operand" "%r,r") + (any_or:X (match_operand:X 1 "register_operand" "%r,r") (match_operand:X 2 "arith_operand" " r,I")))] "" "%i2\t%0,%1,%2" diff --git a/gcc/testsuite/gcc.target/riscv/and-extend-1.c b/gcc/testsuite/gcc.target/riscv/and-extend-1.c new file mode 100644 index 00000000000..a270d287374 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/and-extend-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba_zbb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +foo(unsigned long a, unsigned long* ptr) +{ + ptr[0] = a & 0xffffffffUL; + ptr[1] &= 0xffffffffUL; +} + +void +foo2(unsigned long a, unsigned long* ptr) +{ + ptr[0] = a & 0xffff; + ptr[1] &= 0xffff; +} + +void +foo3(unsigned int a, unsigned int* ptr) +{ + ptr[0] = a & 0xffff; + ptr[1] &= 0xffff; +} + +/* { dg-final { scan-assembler-times "zext.w" 1 } } */ +/* { dg-final { scan-assembler-times "zext.h" 2 } } */ +/* { dg-final { scan-assembler-times "lwu" 1 } } */ +/* { dg-final { scan-assembler-times "lhu" 2 } } */ +/* { dg-final { scan-assembler-not "and\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/and-extend-2.c b/gcc/testsuite/gcc.target/riscv/and-extend-2.c new file mode 100644 index 00000000000..fe639cd1e82 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/and-extend-2.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zba_zbb -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +foo(unsigned long a, unsigned long* ptr) +{ + ptr[0] = a & 0xffffffffUL; + ptr[1] &= 0xffffffffUL; +} + +void +foo2(unsigned long a, unsigned long* ptr) +{ + ptr[0] = a & 0xffff; + ptr[1] &= 0xffff; +} + +void +foo3(unsigned int a, unsigned int* ptr) +{ + ptr[0] = a & 0xffff; + ptr[1] &= 0xffff; +} + +/* { dg-final { scan-assembler-times "zext.h" 2 } } */ +/* { dg-final { scan-assembler-times "lhu" 2 } } */ +/* { dg-final { scan-assembler-not "and\t" } } */