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Violators will be prosecuted; Fri, 23 Mar 2018 11:41:40 -0600 Received: from b03ledav001.gho.boulder.ibm.com (b03ledav001.gho.boulder.ibm.com [9.17.130.232]) by b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w2NHfebm4588002; Fri, 23 Mar 2018 10:41:40 -0700 Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 040476E03A; Fri, 23 Mar 2018 11:41:40 -0600 (MDT) Received: from otta.local (unknown [9.85.154.167]) by b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP id 572136E041; Fri, 23 Mar 2018 11:41:39 -0600 (MDT) Subject: [PATCH. rs6000] Fix PR84912: ICE using -m32 on __builtin_divde*, patch #2 From: Peter Bergner To: GCC Patches Cc: Segher Boessenkool References: Date: Fri, 23 Mar 2018 12:41:38 -0500 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: X-TM-AS-GCONF: 00 x-cbid: 18032317-0008-0000-0000-0000097F8629 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008730; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000255; SDB=6.01007321; UDB=6.00512956; IPR=6.00786609; MB=3.00020202; MTD=3.00000008; XFM=3.00000015; UTC=2018-03-23 17:41:41 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18032317-0009-0000-0000-0000468323FF Message-Id: <1f024cd8-59ec-ff67-cadf-6700ad119000@vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-03-23_11:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1803230201 X-IsSubscribed: yes This is the second patch to fix PR84912, which is an ICE when calling some extended divide builtin functions. This patch is relative to the first patch. This fixes the ICE by adding a new mask to the builtin functions that are ICEing and then enforcing it is set. I have also added a helpful error message in the case it is not set. This passed bootstrap and regtesting on powerpc64-linux with no regressions. Ok for mainline? Do we also want this backported to the open release branches too? Peter gcc/ PR target/84912 * config/rs6000/rs6000.h (RS6000_BTM_POWERPC64): New define. (RS6000_BTM_COMMON): Add RS6000_BTM_POWERPC64. * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add support for RS6000_BTM_POWERPC64. (rs6000_invalid_builtin): Add handling for RS6000_BTM_POWERPC64 (rs6000_builtin_mask_names): Add RS6000_BTM_POWERPC64. * config/rs6000/rs6000-builtin.def (BU_P7_POWERPC64_MISC_2): New macro definition. (DIVDE): Use it. (DIVDEU): Likewise. diff -urpN -X /home/bergner/cvs/dontdiff gcc-fsf-mainline-pr84912-2/gcc/config/rs6000/rs6000.h gcc-fsf-mainline-pr84912/gcc/config/rs6000/rs6000.h --- gcc-fsf-mainline-pr84912-2/gcc/config/rs6000/rs6000.h 2018-03-19 19:59:55.911285043 -0500 +++ gcc-fsf-mainline-pr84912/gcc/config/rs6000/rs6000.h 2018-03-22 19:57:21.051923201 -0500 @@ -2506,6 +2506,7 @@ extern int frame_pointer_needed; #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ +#define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */ #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ @@ -2526,6 +2527,7 @@ extern int frame_pointer_needed; | RS6000_BTM_DFP \ | RS6000_BTM_HARD_FLOAT \ | RS6000_BTM_LDBL128 \ + | RS6000_BTM_POWERPC64 \ | RS6000_BTM_FLOAT128 \ | RS6000_BTM_FLOAT128_HW) diff -urpN -X /home/bergner/cvs/dontdiff gcc-fsf-mainline-pr84912-2/gcc/config/rs6000/rs6000.c gcc-fsf-mainline-pr84912/gcc/config/rs6000/rs6000.c --- gcc-fsf-mainline-pr84912-2/gcc/config/rs6000/rs6000.c 2018-03-23 08:03:55.257469347 -0500 +++ gcc-fsf-mainline-pr84912/gcc/config/rs6000/rs6000.c 2018-03-23 08:03:42.707253487 -0500 @@ -3916,6 +3916,7 @@ rs6000_builtin_mask_calculate (void) | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0) | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0) | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0) + | ((TARGET_POWERPC64) ? RS6000_BTM_POWERPC64 : 0) | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0) | ((TARGET_HTM) ? RS6000_BTM_HTM : 0) | ((TARGET_DFP) ? RS6000_BTM_DFP : 0) @@ -15952,6 +15953,10 @@ rs6000_invalid_builtin (enum rs6000_buil name); else if ((fnmask & RS6000_BTM_FLOAT128) != 0) error ("builtin function %qs requires the %qs option", name, "-mfloat128"); + else if ((fnmask & (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64)) + == (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64)) + error ("builtin function %qs requires the %qs and %qs options", + name, "-mcpu=power7 (or newer)", "-m64 or -mpowerpc64"); else error ("builtin function %qs is not supported with the current options", name); @@ -36612,6 +36617,7 @@ static struct rs6000_opt_mask const rs60 { "hard-dfp", RS6000_BTM_DFP, false, false }, { "hard-float", RS6000_BTM_HARD_FLOAT, false, false }, { "long-double-128", RS6000_BTM_LDBL128, false, false }, + { "powerpc64", RS6000_BTM_POWERPC64, false, false }, { "float128", RS6000_BTM_FLOAT128, false, false }, { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false }, }; diff -urpN -X /home/bergner/cvs/dontdiff gcc-fsf-mainline-pr84912-2/gcc/config/rs6000/rs6000-builtin.def gcc-fsf-mainline-pr84912/gcc/config/rs6000/rs6000-builtin.def --- gcc-fsf-mainline-pr84912-2/gcc/config/rs6000/rs6000-builtin.def 2018-03-23 08:03:55.257469347 -0500 +++ gcc-fsf-mainline-pr84912/gcc/config/rs6000/rs6000-builtin.def 2018-03-23 08:03:42.707253487 -0500 @@ -646,6 +646,15 @@ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ +#define BU_P7_POWERPC64_MISC_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_POPCNTD \ + | RS6000_BTM_POWERPC64, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + #define BU_P7_MISC_X(ENUM, NAME, ATTR) \ RS6000_BUILTIN_X (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_" NAME, /* NAME */ \ @@ -2311,8 +2320,8 @@ BU_P9V_OVERLOAD_1 (VCTZLSBB, "vctzlsbb") /* 2 argument extended divide functions added in ISA 2.06. */ BU_P7_MISC_2 (DIVWE, "divwe", CONST, dive_si) BU_P7_MISC_2 (DIVWEU, "divweu", CONST, diveu_si) -BU_P7_MISC_2 (DIVDE, "divde", CONST, dive_di) -BU_P7_MISC_2 (DIVDEU, "divdeu", CONST, diveu_di) +BU_P7_POWERPC64_MISC_2 (DIVDE, "divde", CONST, dive_di) +BU_P7_POWERPC64_MISC_2 (DIVDEU, "divdeu", CONST, diveu_di) /* 1 argument DFP (decimal floating point) functions added in ISA 2.05. */ BU_DFP_MISC_1 (DXEX, "dxex", CONST, dfp_dxex_dd)