From patchwork Mon May 8 18:16:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1778524 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=HJGrfWGs; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4QFTyn45sqz214X for ; Tue, 9 May 2023 04:17:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229492AbjEHSRB (ORCPT ); Mon, 8 May 2023 14:17:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230187AbjEHSRA (ORCPT ); Mon, 8 May 2023 14:17:00 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DF535BBE for ; Mon, 8 May 2023 11:17:00 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9715262135 for ; Mon, 8 May 2023 18:16:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6522DC433A0; Mon, 8 May 2023 18:16:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683569819; bh=05ZEnpDryaZ3pWwm2uM1BaK+nfW//+toX2uQFMeA9T4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HJGrfWGsDd1s7R5AE+0X9NTaSLnSiTl1CDjI2qlfcq8hhAqOCmAzMcydtEFIvBxYf kEQuQgx6k6zACnTIy2DQIAThvlziT4MzdAtavBoIJ+AoY6AMxPuJU2dXPxW+YKuNqX ZcWyVTekYnD9VAlWfQ/qEk0odrHvs1Z4RfkKOJ84kpsCTlZja+VwTzuSkmWSxSUY65 cAt7YdetUsJq7H6vdJPHzQtJoEEzngINLFx80lTw1eJvepAaziMwmcfh8NXI2fXban nScP2fYPcgIYUuIXBjKAceSEWgoe4x2zOVy7EpGAFoQeSPnkxqFwFQpSmiPXRRgqHR h0Yt4/U4EPHrg== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Heiko Stuebner , Andrew Jones , Sunil V L , Yangyu Chen , devicetree@vger.kernel.org Subject: [RFC 1/6] dt-bindings: riscv: clarify what an unversioned extension means Date: Mon, 8 May 2023 19:16:21 +0100 Message-Id: <20230508-decibel-fender-532248c8f8ed@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230508-hypnotic-phobia-99598439d828@spud> References: <20230508-hypnotic-phobia-99598439d828@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1402; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=pGmr6rcDfQk2g8LcKq7L3T1Gg5LY7Zpc7WjhfhPcmv8=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmRNqXs1UuN814vn8Sa0ftPPlY/qv0kw/MDHrvlzNnmL fZ+EqTUUcrCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIkYqjAy9C6zY3LI67n333be fu4JGzQVn7mGCx7aetLUcHrggz8Z6gz/E/Ncdueu3ZM/WX156Ko9SwoPMs54b6hXwKaUckDT+Fw 3NwA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley C'est la vie, the spec folks reserve the ability to make incompatible changes between major versions of an extension. Their idea of backwards compatibility appears driven by the hardware perspective - it's backwards compatible if a later version is a subset of the existing extension. IOW, if you supported `x` in vN, you still support `x` in vN+1. However in software terms, code that was built for the vN's `x` extension may not work with the new definition. Signed-off-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/riscv/cpus.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index db5253a2a74a..405915b04d69 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -91,6 +91,9 @@ properties: Notably, riscv,isa was defined prior to the creation of the Zicsr and Zifencei extensions and thus "i" implies "zicsr_zifencei". + For the sake of backwards compatibility, an unversioned + extension means that the hart/platform is capable of + supporting version 1.0.0 of the extension. While the isa strings in ISA specification are case insensitive, letters in the riscv,isa string must be all From patchwork Mon May 8 18:16:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1778525 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=LpCAVUax; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4QFTyp3xVSz20fl for ; Tue, 9 May 2023 04:17:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230187AbjEHSRF (ORCPT ); Mon, 8 May 2023 14:17:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232779AbjEHSRE (ORCPT ); Mon, 8 May 2023 14:17:04 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B4175FE8 for ; Mon, 8 May 2023 11:17:03 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id AA98A62F0F for ; Mon, 8 May 2023 18:17:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7550CC4339C; Mon, 8 May 2023 18:16:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683569822; bh=pEkQiWBINoXiTLpYTJ+D1743e4SOfUpdwjwXGQmi2Nk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LpCAVUaxcJjhoad5gbeqsUQCfaua+zg6IbA5rkPbTdwywu2JKINyDuAdkH7BIzECp FGXurYzC2J/OgJgceOMyePFn0+i9ll10Xs7l1qSVdNvvZmGQFn5BlxkCIGLPSCU7Zx 78U2CcMMAvcG+15+JBjCBSaHVNmjA/4WRs7O0R7+7JCOnbBBn/KbvcH0TYsXod7j71 hJ82onfdcnNyPY9edo8xz8xHVmu1Mt1BZLTmb8YdVvVRKz9ntuemhnyiTB9LFKPwhL EJ7W6SOmU2xtJe/ihfsP/hpaThNWYHyze+7zwmOAwvF44liqTxobAPUbWEHYwRZaO5 6VNDvFIWa1yPA== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Heiko Stuebner , Andrew Jones , Sunil V L , Yangyu Chen , devicetree@vger.kernel.org Subject: [RFC 2/6] dt-bindings: riscv: add riscv,isa-extension-* property and incompatible example Date: Mon, 8 May 2023 19:16:22 +0100 Message-Id: <20230508-sneeze-cesarean-d1aff8be9cc8@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230508-hypnotic-phobia-99598439d828@spud> References: <20230508-hypnotic-phobia-99598439d828@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3388; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=mr+KTOsZI6CeMW3M1d3JDMm2IRvhFpi9WHx/17JxyMg=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmRNqUqQpc3/nj4h//xeaPUtb86SlI0GVYZLykrf5tq+ 1RzZ5FJRykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACbyTIPhn7rL/Jb6hHuPuW2L P6o2LojcddjYO/DrjX82F5QKUw7fvsvwT2F1xbvzjdWcjxW2+t92Welp6KV85kzi7oD8O1f7eI/ 5cgEA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley This dt-binding is illustrative *only*, it doesn't yet do what I want it to do in terms of enforcement etc. I am yet to figure out exactly how to wrangle the binding such that the individual properties have more generous versions than the generic pattern property. This binding *will* generate errors, and needs rework before it can seriously be considered. Nevertheless, it should demonstrate how I intend such a property be used. Not-signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/cpus.yaml | 61 ++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 405915b04d69..cccb3b2ae23d 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -100,6 +100,15 @@ properties: lowercase. $ref: "/schemas/types.yaml#/definitions/string" pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ + deprecated: true + + riscv,isa-base: + description: + Identifies the base ISA supported by a hart. + $ref: "/schemas/types.yaml#/definitions/string" + enum: + - rv32i + - rv64i # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false @@ -136,8 +145,32 @@ properties: DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. + riscv,isa-extension-v: + description: RISC-V Vector extension + $ref: "/schemas/types.yaml#/definitions/string" + oneOf: + - const: v1.0.0 + description: the original incarnation + - const: v1.0.1 + description: backwards compat was broken here + +patternProperties: + "^riscv,isa-extension-*": + description: + Catch-all property for ISA extensions that do not need any special + handling, and of which all known versions are compatible with their + original revision. + $ref: "/schemas/types.yaml#/definitions/string" + enum: + - v1.0.0 + +oneOf: + - required: + - riscv,isa-base + - required: + - riscv,isa + required: - - riscv,isa - interrupt-controller additionalProperties: true @@ -208,4 +241,30 @@ examples: }; }; }; + + - | + // Example 3: Extension specification + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + reg = <0>; + compatible = "riscv"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-f = "v1.0.0"; + riscv,isa-extension-d = "v1.0.0"; + riscv,isa-extension-c = "v2.0.0"; + riscv,isa-extension-v = "v1.0.1"; + mmu-type = "riscv,sv48"; + interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; ...