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(haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 43C2B60593; Mon, 8 May 2023 12:01:35 +1000 (AEST) From: Rohan McLure To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 01/12] powerpc: qspinlock: Fix qnode->locked value interpretation Date: Mon, 8 May 2023 12:01:09 +1000 Message-Id: <20230508020120.218494-2-rmclure@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230508020120.218494-1-rmclure@linux.ibm.com> References: <20230508020120.218494-1-rmclure@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: V5L0DOQoKqy8ydLqq0FOxiWsvHGcn1lK X-Proofpoint-ORIG-GUID: O1QdXCtfF48cbGGCCGoI-AwnCfKjROWZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-07_10,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 phishscore=0 mlxlogscore=908 bulkscore=0 suspectscore=0 clxscore=1015 malwarescore=0 spamscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305080009 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rohan McLure , npiggin@gmail.com, arnd@arndb.de Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" A comment accompanying the locked attribute of a qnode assigns a value of 1 to mean that the lock has been acquired. The usages of this variable however assume opposite semantics. Update usages so that the assertions of this comment are reflected in this file. Signed-off-by: Rohan McLure --- arch/powerpc/lib/qspinlock.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/lib/qspinlock.c b/arch/powerpc/lib/qspinlock.c index e4bd145255d0..9cf93963772b 100644 --- a/arch/powerpc/lib/qspinlock.c +++ b/arch/powerpc/lib/qspinlock.c @@ -435,7 +435,7 @@ static __always_inline bool yield_to_prev(struct qspinlock *lock, struct qnode * smp_rmb(); /* See __yield_to_locked_owner comment */ - if (!node->locked) { + if (node->locked) { yield_to_preempted(prev_cpu, yield_count); spin_begin(); return preempted; @@ -566,7 +566,7 @@ static __always_inline void queued_spin_lock_mcs_queue(struct qspinlock *lock, b node->lock = lock; node->cpu = smp_processor_id(); node->yield_cpu = -1; - node->locked = 0; + node->locked = 1; tail = encode_tail_cpu(node->cpu); @@ -584,7 +584,7 @@ static __always_inline void queued_spin_lock_mcs_queue(struct qspinlock *lock, b /* Wait for mcs node lock to be released */ spin_begin(); - while (!node->locked) { + while (node->locked) { spec_barrier(); if (yield_to_prev(lock, node, old, paravirt)) @@ -693,13 +693,13 @@ static __always_inline void queued_spin_lock_mcs_queue(struct qspinlock *lock, b */ if (paravirt && pv_prod_head) { int next_cpu = next->cpu; - WRITE_ONCE(next->locked, 1); + WRITE_ONCE(next->locked, 0); if (_Q_SPIN_MISO) asm volatile("miso" ::: "memory"); if (vcpu_is_preempted(next_cpu)) prod_cpu(next_cpu); } else { - WRITE_ONCE(next->locked, 1); + WRITE_ONCE(next->locked, 0); if (_Q_SPIN_MISO) asm volatile("miso" ::: "memory"); } From patchwork Mon May 8 02:01:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohan McLure X-Patchwork-Id: 1778216 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; 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(haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 47EC66033D; Mon, 8 May 2023 12:01:35 +1000 (AEST) From: Rohan McLure To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 02/12] powerpc: qspinlock: Mark accesses to qnode lock checks Date: Mon, 8 May 2023 12:01:10 +1000 Message-Id: <20230508020120.218494-3-rmclure@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230508020120.218494-1-rmclure@linux.ibm.com> References: <20230508020120.218494-1-rmclure@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: MlrWh0imlR7sXcPYqhyrFdFrHC8jFONp X-Proofpoint-ORIG-GUID: LmgBUdHKtYj0mS-4zefstaUfqLsEIKmw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-07_10,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 suspectscore=0 mlxlogscore=999 mlxscore=0 spamscore=0 clxscore=1015 phishscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305080012 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rohan McLure , npiggin@gmail.com, arnd@arndb.de Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The powerpc implemenation of qspinlocks will both poll and spin on the bitlock guarding a qnode. Mark these accesses with READ_ONCE to convey to KCSAN that polling is intentional here. Signed-off-by: Rohan McLure Reviewed-by: Nicholas Piggin --- arch/powerpc/lib/qspinlock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/lib/qspinlock.c b/arch/powerpc/lib/qspinlock.c index 9cf93963772b..579290d55abf 100644 --- a/arch/powerpc/lib/qspinlock.c +++ b/arch/powerpc/lib/qspinlock.c @@ -435,7 +435,7 @@ static __always_inline bool yield_to_prev(struct qspinlock *lock, struct qnode * smp_rmb(); /* See __yield_to_locked_owner comment */ - if (node->locked) { + if (READ_ONCE(node->locked)) { yield_to_preempted(prev_cpu, yield_count); spin_begin(); return preempted; @@ -584,7 +584,7 @@ static __always_inline void queued_spin_lock_mcs_queue(struct qspinlock *lock, b /* Wait for mcs node lock to be released */ spin_begin(); - while (node->locked) { + while (READ_ONCE(node->locked)) { spec_barrier(); if (yield_to_prev(lock, node, old, paravirt)) From patchwork Mon May 8 02:01:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohan McLure X-Patchwork-Id: 1778207 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Mon, 8 May 2023 02:01:37 +0000 (GMT) Received: from civic.. (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 4B0D66059A; Mon, 8 May 2023 12:01:35 +1000 (AEST) From: Rohan McLure To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 03/12] powerpc: qspinlock: Enforce qnode writes prior to publishing to queue Date: Mon, 8 May 2023 12:01:11 +1000 Message-Id: <20230508020120.218494-4-rmclure@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230508020120.218494-1-rmclure@linux.ibm.com> References: <20230508020120.218494-1-rmclure@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: IzWvHtredjitbRjUej63C6vCtqfniF4f X-Proofpoint-ORIG-GUID: 7tdgY4RIDyXymbmgG9Rz1otEbbgS-yZ- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-07_10,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=976 spamscore=0 suspectscore=0 clxscore=1011 impostorscore=0 mlxscore=0 malwarescore=0 phishscore=0 bulkscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305080009 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rohan McLure , npiggin@gmail.com, arnd@arndb.de Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Use a compiler barrier to enforce that all fields of a new struct qnode be written to (especially the lock value) before publishing the qnode to the waitqueue. Signed-off-by: Rohan McLure --- arch/powerpc/lib/qspinlock.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/lib/qspinlock.c b/arch/powerpc/lib/qspinlock.c index 579290d55abf..d548001a86be 100644 --- a/arch/powerpc/lib/qspinlock.c +++ b/arch/powerpc/lib/qspinlock.c @@ -567,6 +567,10 @@ static __always_inline void queued_spin_lock_mcs_queue(struct qspinlock *lock, b node->cpu = smp_processor_id(); node->yield_cpu = -1; node->locked = 1; + /* + * Assign all attributes of a node before it can be published. + */ + barrier(); tail = encode_tail_cpu(node->cpu); From patchwork Mon May 8 02:01:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohan McLure X-Patchwork-Id: 1778206 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; 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(haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 4E568605A5; Mon, 8 May 2023 12:01:35 +1000 (AEST) From: Rohan McLure To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 04/12] asm-generic/mmiowb: Mark accesses to fix KCSAN warnings Date: Mon, 8 May 2023 12:01:12 +1000 Message-Id: <20230508020120.218494-5-rmclure@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230508020120.218494-1-rmclure@linux.ibm.com> References: <20230508020120.218494-1-rmclure@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: RTKNhKV7DwAwOpasNHOWs101493OvhsI X-Proofpoint-ORIG-GUID: N_vd80AdTKzx81U399P0Mz1blHbH64pa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-07_10,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=948 spamscore=0 suspectscore=0 clxscore=1015 impostorscore=0 mlxscore=0 malwarescore=0 phishscore=0 bulkscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305080009 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arnd@arndb.de, npiggin@gmail.com, Rohan McLure , Gautam Menghani Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Prior to this patch, data races are detectable by KCSAN of the following forms: [1] Asynchronous calls to mmiowb_set_pending() from an interrupt context or otherwise outside of a critical section [2] Interrupted critical sections, where the interrupt will itself acquire a lock In case [1], calling context does not need an mmiowb() call to be issued, otherwise it would do so itself. Such calls to mmiowb_set_pending() are either idempotent or no-ops. In case [2], irrespective of when the interrupt occurs, the interrupt will acquire and release its locks prior to its return, nesting_count will continue balanced. In the worst case, the interrupted critical section during a mmiowb_spin_unlock() call observes an mmiowb to be pending and afterward is interrupted, leading to an extraneous call to mmiowb(). This data race is clearly innocuous. Mark all potentially asynchronous memory accesses with READ_ONCE or WRITE_ONCE, including increments and decrements to nesting_count. This has the effect of removing KCSAN warnings at consumer's callsites. Signed-off-by: Rohan McLure Reported-by: Michael Ellerman Reported-by: Gautam Menghani Acked-by: Arnd Bergmann Tested-by: Gautam Menghani --- include/asm-generic/mmiowb.h | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/include/asm-generic/mmiowb.h b/include/asm-generic/mmiowb.h index 5698fca3bf56..0b8b794150db 100644 --- a/include/asm-generic/mmiowb.h +++ b/include/asm-generic/mmiowb.h @@ -35,27 +35,32 @@ DECLARE_PER_CPU(struct mmiowb_state, __mmiowb_state); static inline void mmiowb_set_pending(void) { struct mmiowb_state *ms = __mmiowb_state(); + u16 nesting_count = READ_ONCE(ms->nesting_count); - if (likely(ms->nesting_count)) - ms->mmiowb_pending = ms->nesting_count; + if (likely(nesting_count)) + WRITE_ONCE(ms->mmiowb_pending, nesting_count); } static inline void mmiowb_spin_lock(void) { struct mmiowb_state *ms = __mmiowb_state(); - ms->nesting_count++; + + /* Increment need not be atomic. Nestedness is balanced over interrupts. */ + WRITE_ONCE(ms->nesting_count, READ_ONCE(ms->nesting_count) + 1); } static inline void mmiowb_spin_unlock(void) { struct mmiowb_state *ms = __mmiowb_state(); + u16 pending = READ_ONCE(ms->mmiowb_pending); - if (unlikely(ms->mmiowb_pending)) { - ms->mmiowb_pending = 0; + WRITE_ONCE(ms->mmiowb_pending, 0); + if (unlikely(pending)) { mmiowb(); } - ms->nesting_count--; + /* Decrement need not be atomic. Nestedness is balanced over interrupts. */ + WRITE_ONCE(ms->nesting_count, READ_ONCE(ms->nesting_count) - 1); } #else #define mmiowb_set_pending() do { } while (0) From patchwork Mon May 8 02:01:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohan McLure X-Patchwork-Id: 1778213 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=YYHmNFAf; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QF4Th6lkfz1ymw for ; Mon, 8 May 2023 12:08:56 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4QF4Th5gXmz3fJ7 for ; Mon, 8 May 2023 12:08:56 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=YYHmNFAf; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0b-001b2d01.pphosted.com; envelope-from=rmclure@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=YYHmNFAf; dkim-atps=neutral Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4QF4Kj6Ygmz3c96 for ; Mon, 8 May 2023 12:02:01 +1000 (AEST) Received: from pps.filterd (m0353723.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3481ikBl003456; Mon, 8 May 2023 02:01:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=YRiUUrC4V/WfA6JMSAR+2kIH+01rtqNqFnMogbY60+8=; b=YYHmNFAf8WmABHu9PKObGhl8+1Hzvb11+HqpAeGKLNyHd/N1AxCFSB/onVNXd0N5vfah oA4aEG44iXmzBlVabgN8MGZ8uuPRbMb/weGnigl0mhJLoIy6pghPLSk++W+T3arFqD2d 9qvMjB8scljdApy4XXkXjyGKZ666k/P330o2XRVtqChdQ1fvUKMKXlIRz4I54z2uo1w9 O0dGdCt2l+REd+27EUCcnLuQQzIgNY6ehz8gCPSigm4wNF2tn3UQjjgtW6vrK79IdB6y rz64fJHzlDyZ1k4HzqpbRsARCpq3P+oQxMGcujubIwoxMR+3iyUx9wFnrl3KlZjeLkKL hg== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3qeqpcr9yh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 May 2023 02:01:45 +0000 Received: from m0353723.ppops.net (m0353723.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3481uNtK003683; Mon, 8 May 2023 02:01:45 GMT Received: from ppma06ams.nl.ibm.com (66.31.33a9.ip4.static.sl-reverse.com [169.51.49.102]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3qeqpcr9y4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 May 2023 02:01:44 +0000 Received: from pps.filterd (ppma06ams.nl.ibm.com [127.0.0.1]) by ppma06ams.nl.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 3481YxLL021745; Mon, 8 May 2023 02:01:43 GMT Received: from smtprelay01.fra02v.mail.ibm.com ([9.218.2.227]) by ppma06ams.nl.ibm.com (PPS) with ESMTPS id 3qde5fgu2r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 May 2023 02:01:43 +0000 Received: from smtpav06.fra02v.mail.ibm.com (smtpav06.fra02v.mail.ibm.com [10.20.54.105]) by smtprelay01.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 34821eVC66257274 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 8 May 2023 02:01:40 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A104B20049; Mon, 8 May 2023 02:01:40 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 203B720043; Mon, 8 May 2023 02:01:40 +0000 (GMT) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 8 May 2023 02:01:40 +0000 (GMT) Received: from civic.. (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 520E4605A6; Mon, 8 May 2023 12:01:35 +1000 (AEST) From: Rohan McLure To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 05/12] powerpc: Mark [h]ssr_valid accesses in check_return_regs_valid Date: Mon, 8 May 2023 12:01:13 +1000 Message-Id: <20230508020120.218494-6-rmclure@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230508020120.218494-1-rmclure@linux.ibm.com> References: <20230508020120.218494-1-rmclure@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: MEhZNDYR4mIDkZVkucmJShfqEAAlOKBo X-Proofpoint-ORIG-GUID: Wj5voPRuBAwvQdzy4uVSf8IoLEsbjwTk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-07_10,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 suspectscore=0 mlxlogscore=492 mlxscore=0 spamscore=0 clxscore=1015 phishscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305080009 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rohan McLure , npiggin@gmail.com, arnd@arndb.de Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Checks to see if the [H]SRR registers have been clobbered by (soft) NMI interrupts imply the possibility for a data race on the [h]srr_valid entries in the PACA. Annotate accesses to these fields with READ_ONCE, removing the need for the barrier. The diagnostic can use plain-access reads and writes, but annotate with data_race. Signed-off-by: Rohan McLure Reported-by: Michael Ellerman Reviewed-by: Nicholas Piggin --- arch/powerpc/include/asm/ptrace.h | 4 ++-- arch/powerpc/kernel/interrupt.c | 14 ++++++-------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h index 0eb90a013346..9db8b16567e2 100644 --- a/arch/powerpc/include/asm/ptrace.h +++ b/arch/powerpc/include/asm/ptrace.h @@ -180,8 +180,8 @@ void do_syscall_trace_leave(struct pt_regs *regs); static inline void set_return_regs_changed(void) { #ifdef CONFIG_PPC_BOOK3S_64 - local_paca->hsrr_valid = 0; - local_paca->srr_valid = 0; + WRITE_ONCE(local_paca->hsrr_valid, 0); + WRITE_ONCE(local_paca->srr_valid, 0); #endif } diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrupt.c index e34c72285b4e..1f033f11b871 100644 --- a/arch/powerpc/kernel/interrupt.c +++ b/arch/powerpc/kernel/interrupt.c @@ -125,7 +125,7 @@ static notrace void check_return_regs_valid(struct pt_regs *regs) case 0x1600: case 0x1800: validp = &local_paca->hsrr_valid; - if (!*validp) + if (!READ_ONCE(*validp)) return; srr0 = mfspr(SPRN_HSRR0); @@ -135,7 +135,7 @@ static notrace void check_return_regs_valid(struct pt_regs *regs) break; default: validp = &local_paca->srr_valid; - if (!*validp) + if (!READ_ONCE(*validp)) return; srr0 = mfspr(SPRN_SRR0); @@ -161,19 +161,17 @@ static notrace void check_return_regs_valid(struct pt_regs *regs) * such things will get caught most of the time, statistically * enough to be able to get a warning out. */ - barrier(); - - if (!*validp) + if (!READ_ONCE(*validp)) return; - if (!warned) { - warned = true; + if (!data_race(warned)) { + data_race(warned = true); printk("%sSRR0 was: %lx should be: %lx\n", h, srr0, regs->nip); printk("%sSRR1 was: %lx should be: %lx\n", h, srr1, regs->msr); show_regs(regs); } - *validp = 0; /* fixup */ + WRITE_ONCE(*validp, 0); /* fixup */ #endif } From patchwork Mon May 8 02:01:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohan McLure X-Patchwork-Id: 1778215 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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(haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 5541960595; Mon, 8 May 2023 12:01:35 +1000 (AEST) From: Rohan McLure To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 06/12] powerpc: Mark accesses to power_save callback in arch_cpu_idle Date: Mon, 8 May 2023 12:01:14 +1000 Message-Id: <20230508020120.218494-7-rmclure@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230508020120.218494-1-rmclure@linux.ibm.com> References: <20230508020120.218494-1-rmclure@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: bmSFBcdVCw2-gH2swHtps0m_NhoEcDP7 X-Proofpoint-ORIG-GUID: _a4ErqOldh5Pci7cJD1dxKvaniVa_1z- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-07_10,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=943 lowpriorityscore=0 clxscore=1015 malwarescore=0 suspectscore=0 priorityscore=1501 impostorscore=0 adultscore=0 mlxscore=0 spamscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305080012 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rohan McLure , npiggin@gmail.com, arnd@arndb.de Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The power_save callback can be overwritten by another core at boot time. Specifically, null values will be replaced exactly once with the callback suitable for the particular platform (PowerNV / pseries lpars). Mark reads to this variable with READ_ONCE to signal to KCSAN that this race is acceptable, as well as to rule-out the possibility for compiler reorderings leading to calling a null pointer. Signed-off-by: Rohan McLure --- arch/powerpc/kernel/idle.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c index b1c0418b25c8..a1589bb97c98 100644 --- a/arch/powerpc/kernel/idle.c +++ b/arch/powerpc/kernel/idle.c @@ -43,10 +43,12 @@ __setup("powersave=off", powersave_off); void arch_cpu_idle(void) { + void (*power_save)(void) = READ_ONCE(ppc_md.power_save); + ppc64_runlatch_off(); - if (ppc_md.power_save) { - ppc_md.power_save(); + if (power_save) { + power_save(); /* * Some power_save functions return with * interrupts enabled, some don't. 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(haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 58A98605B2; Mon, 8 May 2023 12:01:35 +1000 (AEST) From: Rohan McLure To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 07/12] powerpc: powernv: Fix KCSAN datarace warnings on idle_state contention Date: Mon, 8 May 2023 12:01:15 +1000 Message-Id: <20230508020120.218494-8-rmclure@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230508020120.218494-1-rmclure@linux.ibm.com> References: <20230508020120.218494-1-rmclure@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: MnAk8kYx3r-I4SC5vbKV9yW0v0yRb3zW X-Proofpoint-ORIG-GUID: up9ajB8EmtO4XBd4ArvTt2AXEUZeAgp1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-07_10,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 suspectscore=0 clxscore=1015 impostorscore=0 mlxscore=0 malwarescore=0 phishscore=0 bulkscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305080009 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rohan McLure , arnd@arndb.de, npiggin@gmail.com, Rohan McLure Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The idle_state entry in the PACA on PowerNV features a bit which is atomically tested and set through ldarx/stdcx. to be used as a spinlock. This lock then guards access to other bit fields of idle_state. KCSAN cannot differentiate between any of these bitfield accesses as they all are implemented by 8-byte store/load instructions, thus cores contending on the bit-lock appear to data race with modifications to idle_state. Separate the bit-lock entry from the data guarded by the lock to avoid the possibility of data races being detected by KCSAN. Suggested-by: Nicholas Piggin Signed-off-by: Rohan McLure --- arch/powerpc/include/asm/paca.h | 1 + arch/powerpc/platforms/powernv/idle.c | 20 +++++++++++--------- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h index da0377f46597..cb325938766a 100644 --- a/arch/powerpc/include/asm/paca.h +++ b/arch/powerpc/include/asm/paca.h @@ -191,6 +191,7 @@ struct paca_struct { #ifdef CONFIG_PPC_POWERNV /* PowerNV idle fields */ /* PNV_CORE_IDLE_* bits, all siblings work on thread 0 paca */ + unsigned long idle_lock; /* A value of 1 means acquired */ unsigned long idle_state; union { /* P7/P8 specific fields */ diff --git a/arch/powerpc/platforms/powernv/idle.c b/arch/powerpc/platforms/powernv/idle.c index 841cb7f31f4f..97dbb7bc2b00 100644 --- a/arch/powerpc/platforms/powernv/idle.c +++ b/arch/powerpc/platforms/powernv/idle.c @@ -246,9 +246,9 @@ static inline void atomic_lock_thread_idle(void) { int cpu = raw_smp_processor_id(); int first = cpu_first_thread_sibling(cpu); - unsigned long *state = &paca_ptrs[first]->idle_state; + unsigned long *lock = &paca_ptrs[first]->idle_lock; - while (unlikely(test_and_set_bit_lock(NR_PNV_CORE_IDLE_LOCK_BIT, state))) + while (unlikely(test_and_set_bit_lock(NR_PNV_CORE_IDLE_LOCK_BIT, lock))) barrier(); } @@ -258,29 +258,31 @@ static inline void atomic_unlock_and_stop_thread_idle(void) int first = cpu_first_thread_sibling(cpu); unsigned long thread = 1UL << cpu_thread_in_core(cpu); unsigned long *state = &paca_ptrs[first]->idle_state; + unsigned long *lock = &paca_ptrs[first]->idle_lock; u64 s = READ_ONCE(*state); u64 new, tmp; - BUG_ON(!(s & PNV_CORE_IDLE_LOCK_BIT)); + BUG_ON(!(READ_ONCE(*lock) & PNV_CORE_IDLE_LOCK_BIT)); BUG_ON(s & thread); again: - new = (s | thread) & ~PNV_CORE_IDLE_LOCK_BIT; + new = s | thread; tmp = cmpxchg(state, s, new); if (unlikely(tmp != s)) { s = tmp; goto again; } + clear_bit_unlock(NR_PNV_CORE_IDLE_LOCK_BIT, lock); } static inline void atomic_unlock_thread_idle(void) { int cpu = raw_smp_processor_id(); int first = cpu_first_thread_sibling(cpu); - unsigned long *state = &paca_ptrs[first]->idle_state; + unsigned long *lock = &paca_ptrs[first]->idle_lock; - BUG_ON(!test_bit(NR_PNV_CORE_IDLE_LOCK_BIT, state)); - clear_bit_unlock(NR_PNV_CORE_IDLE_LOCK_BIT, state); + BUG_ON(!test_bit(NR_PNV_CORE_IDLE_LOCK_BIT, lock)); + clear_bit_unlock(NR_PNV_CORE_IDLE_LOCK_BIT, lock); } /* P7 and P8 */ @@ -380,9 +382,9 @@ static unsigned long power7_idle_insn(unsigned long type) sprs.uamor = mfspr(SPRN_UAMOR); } - local_paca->thread_idle_state = type; + WRITE_ONCE(local_paca->thread_idle_state, type); srr1 = isa206_idle_insn_mayloss(type); /* go idle */ - local_paca->thread_idle_state = PNV_THREAD_RUNNING; + WRITE_ONCE(local_paca->thread_idle_state, PNV_THREAD_RUNNING); WARN_ON_ONCE(!srr1); WARN_ON_ONCE(mfmsr() & (MSR_IR|MSR_DR)); From patchwork Mon May 8 02:01:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohan McLure X-Patchwork-Id: 1778211 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Mon, 8 May 2023 02:01:40 +0000 (GMT) Received: from civic.. (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 5CD0C605DC; Mon, 8 May 2023 12:01:35 +1000 (AEST) From: Rohan McLure To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 08/12] powerpc: Annotate accesses to ipi message flags Date: Mon, 8 May 2023 12:01:16 +1000 Message-Id: <20230508020120.218494-9-rmclure@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230508020120.218494-1-rmclure@linux.ibm.com> References: <20230508020120.218494-1-rmclure@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 7TWjvqK-IPPKTZw4yUk6cOpKGfMa6Jkq X-Proofpoint-GUID: yzdY7YGFNMHMqIlbyPXwGKgXEZGbm9MX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-07_10,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 suspectscore=0 phishscore=0 mlxscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 malwarescore=0 mlxlogscore=864 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305080009 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rohan McLure , npiggin@gmail.com, arnd@arndb.de Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" IPI message flags are observed and consequently consumed in the smp_ipi_demux_relaxed function, which handles these message sources until it observes none more arriving. Mark the checked loop guard with READ_ONCE, to signal to KCSAN that the read is known to be volatile, and that non-determinism is expected. Signed-off-by: Rohan McLure --- arch/powerpc/kernel/smp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 6b90f10a6c81..00b74d66b771 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -348,7 +348,7 @@ irqreturn_t smp_ipi_demux_relaxed(void) if (all & IPI_MESSAGE(PPC_MSG_NMI_IPI)) nmi_ipi_action(0, NULL); #endif - } while (info->messages); + } while (READ_ONCE(info->messages)); return IRQ_HANDLED; } From patchwork Mon May 8 02:01:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohan McLure X-Patchwork-Id: 1778209 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; 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(haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 5FFDD605AB; Mon, 8 May 2023 12:01:35 +1000 (AEST) From: Rohan McLure To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 09/12] powerpc: Mark writes registering ipi to host cpu through kvm Date: Mon, 8 May 2023 12:01:17 +1000 Message-Id: <20230508020120.218494-10-rmclure@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230508020120.218494-1-rmclure@linux.ibm.com> References: <20230508020120.218494-1-rmclure@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Or5tA-ctvLLhGAk9Pk5TENl6cHkbtqja X-Proofpoint-ORIG-GUID: Cao2PyW_VoKIoOSwGMxauOJAgG3DG6ZE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-07_10,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 phishscore=0 mlxlogscore=711 bulkscore=0 suspectscore=0 clxscore=1015 malwarescore=0 spamscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305080009 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rohan McLure , npiggin@gmail.com, arnd@arndb.de Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Mark writes to hypervisor ipi state so that KCSAN recognises these asynchronous issue of kvmppc_{set,clear}_host_ipi to be intended, with atomic writes. Signed-off-by: Rohan McLure --- arch/powerpc/include/asm/kvm_ppc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h index bc57d058ad5b..d701df006c08 100644 --- a/arch/powerpc/include/asm/kvm_ppc.h +++ b/arch/powerpc/include/asm/kvm_ppc.h @@ -548,12 +548,12 @@ static inline void kvmppc_set_host_ipi(int cpu) * pairs with the barrier in kvmppc_clear_host_ipi() */ smp_mb(); - paca_ptrs[cpu]->kvm_hstate.host_ipi = 1; + WRITE_ONCE(paca_ptrs[cpu]->kvm_hstate.host_ipi, 1); } static inline void kvmppc_clear_host_ipi(int cpu) { - paca_ptrs[cpu]->kvm_hstate.host_ipi = 0; + WRITE_ONCE(paca_ptrs[cpu]->kvm_hstate.host_ipi, 0); /* * order clearing of host_ipi flag vs. processing of IPI messages * From patchwork Mon May 8 02:01:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohan McLure X-Patchwork-Id: 1778217 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Mon, 8 May 2023 02:01:40 +0000 (GMT) Received: from civic.. (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 629DE605F3; Mon, 8 May 2023 12:01:35 +1000 (AEST) From: Rohan McLure To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 10/12] powerpc: powernv: Annotate data races in opal events Date: Mon, 8 May 2023 12:01:18 +1000 Message-Id: <20230508020120.218494-11-rmclure@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230508020120.218494-1-rmclure@linux.ibm.com> References: <20230508020120.218494-1-rmclure@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: mdwNrDbLf4Qba6RXdhtsox7-S1XbO_KG X-Proofpoint-GUID: ZpwtSKUcXZYJwYc1Ep_CpfyCnzs96hvC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-07_10,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 suspectscore=0 phishscore=0 mlxscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 malwarescore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305080012 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rohan McLure , npiggin@gmail.com, arnd@arndb.de Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The kopald thread handles opal events as they appear, but by polling a static bit-vector in last_outstanding_events. Annotate these data races accordingly. We are not at risk of missing events, but use of READ_ONCE, WRITE_ONCE will assist readers in seeing that kopald only consumes the events it is aware of when it is scheduled. Also removes extraneous KCSAN warnings. Signed-off-by: Rohan McLure Reviewed-by: Nicholas Piggin --- arch/powerpc/platforms/powernv/opal-irqchip.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/platforms/powernv/opal-irqchip.c b/arch/powerpc/platforms/powernv/opal-irqchip.c index d55652b5f6fa..f9a7001dacb7 100644 --- a/arch/powerpc/platforms/powernv/opal-irqchip.c +++ b/arch/powerpc/platforms/powernv/opal-irqchip.c @@ -59,7 +59,7 @@ void opal_handle_events(void) cond_resched(); } - last_outstanding_events = 0; + WRITE_ONCE(last_outstanding_events, 0); if (opal_poll_events(&events) != OPAL_SUCCESS) return; e = be64_to_cpu(events) & opal_event_irqchip.mask; @@ -69,7 +69,7 @@ void opal_handle_events(void) bool opal_have_pending_events(void) { - if (last_outstanding_events & opal_event_irqchip.mask) + if (READ_ONCE(last_outstanding_events) & opal_event_irqchip.mask) return true; return false; } @@ -124,7 +124,7 @@ static irqreturn_t opal_interrupt(int irq, void *data) __be64 events; opal_handle_interrupt(virq_to_hw(irq), &events); - last_outstanding_events = be64_to_cpu(events); + WRITE_ONCE(last_outstanding_events, be64_to_cpu(events)); if (opal_have_pending_events()) opal_wake_poller(); From patchwork Mon May 8 02:01:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohan McLure X-Patchwork-Id: 1778214 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=b5d5vTue; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QF4Vw5lBsz1ymw for ; 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(haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 65B746060A; Mon, 8 May 2023 12:01:35 +1000 (AEST) From: Rohan McLure To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 11/12] powerpc: powernv: Annotate asynchronous access to opal tokens Date: Mon, 8 May 2023 12:01:19 +1000 Message-Id: <20230508020120.218494-12-rmclure@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230508020120.218494-1-rmclure@linux.ibm.com> References: <20230508020120.218494-1-rmclure@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: pw5Ad5v3A6QSth539JY25IwEZjebUFw2 X-Proofpoint-GUID: zpF284ZQPe7Mteqi6iromdO6RRoRxucv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-07_10,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 priorityscore=1501 spamscore=0 phishscore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 suspectscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305080012 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rohan McLure , npiggin@gmail.com, arnd@arndb.de Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The opal-async.c unit contains code for polling event sources, which implies intentional data races. Ensure that the compiler will atomically access such variables by means of {READ,WRITE}_ONCE calls, which in turn inform KCSAN that polling behaviour is intended. Signed-off-by: Rohan McLure --- arch/powerpc/platforms/powernv/opal-async.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/platforms/powernv/opal-async.c b/arch/powerpc/platforms/powernv/opal-async.c index c094fdf5825c..282d2ac6fbb0 100644 --- a/arch/powerpc/platforms/powernv/opal-async.c +++ b/arch/powerpc/platforms/powernv/opal-async.c @@ -146,7 +146,7 @@ int opal_async_wait_response(uint64_t token, struct opal_msg *msg) * functional. */ opal_wake_poller(); - wait_event(opal_async_wait, opal_async_tokens[token].state + wait_event(opal_async_wait, READ_ONCE(opal_async_tokens[token].state) == ASYNC_TOKEN_COMPLETED); memcpy(msg, &opal_async_tokens[token].response, sizeof(*msg)); @@ -185,7 +185,7 @@ int opal_async_wait_response_interruptible(uint64_t token, struct opal_msg *msg) * interruptible version before doing anything else with the * token. */ - if (opal_async_tokens[token].state == ASYNC_TOKEN_ALLOCATED) { + if (READ_ONCE(opal_async_tokens[token].state) == ASYNC_TOKEN_ALLOCATED) { spin_lock_irqsave(&opal_async_comp_lock, flags); if (opal_async_tokens[token].state == ASYNC_TOKEN_ALLOCATED) opal_async_tokens[token].state = ASYNC_TOKEN_DISPATCHED; @@ -199,7 +199,7 @@ int opal_async_wait_response_interruptible(uint64_t token, struct opal_msg *msg) */ opal_wake_poller(); ret = wait_event_interruptible(opal_async_wait, - opal_async_tokens[token].state == + READ_ONCE(opal_async_tokens[token].state) == ASYNC_TOKEN_COMPLETED); if (!ret) memcpy(msg, &opal_async_tokens[token].response, sizeof(*msg)); From patchwork Mon May 8 02:01:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohan McLure X-Patchwork-Id: 1778212 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; 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(haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 68A73605F2; Mon, 8 May 2023 12:01:35 +1000 (AEST) From: Rohan McLure To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 12/12] powerpc: Mark asynchronous accesses to irq_data Date: Mon, 8 May 2023 12:01:20 +1000 Message-Id: <20230508020120.218494-13-rmclure@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230508020120.218494-1-rmclure@linux.ibm.com> References: <20230508020120.218494-1-rmclure@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: F0PGzsKeR-Nt9j1EJXVc8hOp21M-NiKw X-Proofpoint-ORIG-GUID: 9kWjnsl5ccv3dOAYQB8yaBSJAqLYJoiD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-07_10,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 suspectscore=0 mlxlogscore=999 mlxscore=0 spamscore=0 clxscore=1015 phishscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305080009 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rohan McLure , npiggin@gmail.com, arnd@arndb.de Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" KCSAN revealed that while irq_data entries are written to either from behind a mutex, or otherwise atomically, accesses to irq_data->hwirq can occur asynchronously, without volatile annotation. Mark these accesses with READ_ONCE to avoid unfortunate compiler reorderings and remove KCSAN warnings. Signed-off-by: Rohan McLure --- arch/powerpc/kernel/irq.c | 2 +- arch/powerpc/platforms/powernv/pci-ioda.c | 12 ++++++------ include/linux/irq.h | 2 +- kernel/irq/irqdomain.c | 4 ++-- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 6f7d4edaa0bc..4ac192755510 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c @@ -353,7 +353,7 @@ void do_softirq_own_stack(void) irq_hw_number_t virq_to_hw(unsigned int virq) { struct irq_data *irq_data = irq_get_irq_data(virq); - return WARN_ON(!irq_data) ? 0 : irq_data->hwirq; + return WARN_ON(!irq_data) ? 0 : READ_ONCE(irq_data->hwirq); } EXPORT_SYMBOL_GPL(virq_to_hw); diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index f851f4983423..141491e86bba 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -1986,7 +1986,7 @@ int64_t pnv_opal_pci_msi_eoi(struct irq_data *d) struct pci_controller *hose = irq_data_get_irq_chip_data(d->parent_data); struct pnv_phb *phb = hose->private_data; - return opal_pci_msi_eoi(phb->opal_id, d->parent_data->hwirq); + return opal_pci_msi_eoi(phb->opal_id, READ_ONCE(d->parent_data->hwirq)); } /* @@ -2162,11 +2162,11 @@ static void pnv_msi_compose_msg(struct irq_data *d, struct msi_msg *msg) struct pnv_phb *phb = hose->private_data; int rc; - rc = __pnv_pci_ioda_msi_setup(phb, pdev, d->hwirq, + rc = __pnv_pci_ioda_msi_setup(phb, pdev, READ_ONCE(d->hwirq), entry->pci.msi_attrib.is_64, msg); if (rc) dev_err(&pdev->dev, "Failed to setup %s-bit MSI #%ld : %d\n", - entry->pci.msi_attrib.is_64 ? "64" : "32", d->hwirq, rc); + entry->pci.msi_attrib.is_64 ? "64" : "32", data_race(d->hwirq), rc); } /* @@ -2184,7 +2184,7 @@ static void pnv_msi_eoi(struct irq_data *d) * since it is translated into a vector number in * OPAL, use that directly. */ - WARN_ON_ONCE(opal_pci_msi_eoi(phb->opal_id, d->hwirq)); + WARN_ON_ONCE(opal_pci_msi_eoi(phb->opal_id, READ_ONCE(d->hwirq))); } irq_chip_eoi_parent(d); @@ -2263,9 +2263,9 @@ static void pnv_irq_domain_free(struct irq_domain *domain, unsigned int virq, struct pnv_phb *phb = hose->private_data; pr_debug("%s bridge %pOF %d/%lx #%d\n", __func__, hose->dn, - virq, d->hwirq, nr_irqs); + virq, data_race(d->hwirq), nr_irqs); - msi_bitmap_free_hwirqs(&phb->msi_bmp, d->hwirq, nr_irqs); + msi_bitmap_free_hwirqs(&phb->msi_bmp, READ_ONCE(d->hwirq), nr_irqs); /* XIVE domain is cleared through ->msi_free() */ } diff --git a/include/linux/irq.h b/include/linux/irq.h index b1b28affb32a..a6888bcb3c5b 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -452,7 +452,7 @@ static inline bool irqd_affinity_on_activate(struct irq_data *d) static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) { - return d->hwirq; + return READ_ONCE(d->hwirq); } /** diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index f34760a1e222..dd9054494f84 100644 --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -549,7 +549,7 @@ static void irq_domain_disassociate(struct irq_domain *domain, unsigned int irq) "virq%i doesn't exist; cannot disassociate\n", irq)) return; - hwirq = irq_data->hwirq; + hwirq = READ_ONCE(irq_data->hwirq); mutex_lock(&domain->root->mutex); @@ -948,7 +948,7 @@ struct irq_desc *__irq_resolve_mapping(struct irq_domain *domain, if (irq_domain_is_nomap(domain)) { if (hwirq < domain->hwirq_max) { data = irq_domain_get_irq_data(domain, hwirq); - if (data && data->hwirq == hwirq) + if (data && READ_ONCE(data->hwirq) == hwirq) desc = irq_data_to_desc(data); if (irq && desc) *irq = hwirq;