From patchwork Tue Mar 28 13:02:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jayesh Choudhary X-Patchwork-Id: 1762312 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=uM8sV8/n; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Pm8x04tsGz1yYS for ; Wed, 29 Mar 2023 00:02:44 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0F13585746; Tue, 28 Mar 2023 15:02:29 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="uM8sV8/n"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 02C5E85CB6; Tue, 28 Mar 2023 15:02:26 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1772485C6E for ; Tue, 28 Mar 2023 15:02:05 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=j-choudhary@ti.com Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32SD24Tt075572 for ; Tue, 28 Mar 2023 08:02:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1680008524; bh=hDbJ6jqJY6Ifyd8roAhbHVebDjWYzP/faOixweZkn7I=; h=From:To:CC:Subject:Date; b=uM8sV8/n+8jFFTADyxJ0lWkCVD6DwlnDbIPxBeuz3MyooY8HpedPdElQGbGG6HlN9 bd/PjCCGyl0g1l24zZVqcou+vsGzVWcgA1KEdFOhxZ9PROr2/727xeIPoJR5RaAXwA n4U9Y/BGOE2YwYnCQWa5nXVwMQAgg1JwOQjtS+Xc= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32SD23Ih105060 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Tue, 28 Mar 2023 08:02:04 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 28 Mar 2023 08:02:02 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 28 Mar 2023 08:02:02 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32SD22b5112598; Tue, 28 Mar 2023 08:02:02 -0500 From: Jayesh Choudhary To: CC: , , , Subject: [PATCH] arch: mach-k3: j721s2_init: Disable the firewalls Date: Tue, 28 Mar 2023 18:32:01 +0530 Message-ID: <20230328130201.324528-1-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Some firewalls enabled by ROM are still left on. So some address space is inaccessible to the bootloader. For example, in OSPI boot mode we get an exception and the system hangs. Therefore, disable all the firewalls left on by the ROM. Signed-off-by: Jayesh Choudhary Reviewed-by: Andrew Davis Reviewed-by: Manorit Chawdhry --- arch/arm/mach-k3/j721s2_init.c | 53 ++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c index 09e55ed456..7d347b5156 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2_init.c @@ -22,6 +22,51 @@ #include #include +struct fwl_data cbass_hc_cfg0_fwls[] = { + { "PCIE0_CFG", 2577, 7 }, + { "EMMC8SS0_CFG", 2579, 4 }, + { "USB3SS0_CORE", 2580, 4 }, + { "USB3SS1_CORE", 2581, 1 }, +}, cbass_hc2_fwls[] = { + { "PCIE0", 2547, 24 }, + { "HC2_WIZ16B8M4CT2", 2552, 1 }, +}, cbass_rc_cfg0_fwls[] = { + { "EMMCSD4SS0_CFG", 2400, 4 }, +}, infra_cbass0_fwls[] = { + { "PSC0", 5, 1 }, + { "PLL_CTRL0", 6, 1 }, + { "PLL_MMR0", 8, 26 }, + { "CTRL_MMR0", 9, 16 }, + { "GPIO0", 16, 1 }, +}, mcu_cbass0_fwls[] = { + { "MCU_R5FSS0_CORE0", 1024, 4 }, + { "MCU_R5FSS0_CORE0_CFG", 1025, 3 }, + { "MCU_R5FSS0_CORE1", 1028, 4 }, + { "MCU_R5FSS0_CORE1_CFG", 1029, 1 }, + { "MCU_FSS0_CFG", 1032, 12 }, + { "MCU_FSS0_S1", 1033, 8 }, + { "MCU_FSS0_S0", 1036, 8 }, + { "MCU_PSROM49152X32", 1048, 1 }, + { "MCU_MSRAM128KX64", 1050, 8 }, + { "MCU_MSRAM128KX64_CFG", 1051, 1 }, + { "MCU_TIMER0", 1056, 1 }, + { "MCU_TIMER9", 1065, 1 }, + { "MCU_USART0", 1120, 1 }, + { "MCU_I2C0", 1152, 1 }, + { "MCU_CTRL_MMR0", 1200, 8 }, + { "MCU_PLL_MMR0", 1201, 3 }, + { "MCU_CPSW0", 1220, 2 }, +}, wkup_cbass0_fwls[] = { + { "WKUP_PSC0", 129, 1 }, + { "WKUP_PLL_CTRL0", 130, 1 }, + { "WKUP_CTRL_MMR0", 131, 16 }, + { "WKUP_GPIO0", 132, 1 }, + { "WKUP_I2C0", 144, 1 }, + { "WKUP_USART0", 160, 1 }, +}, navss_cbass0_fwls[] = { + { "NACSS_VIRT0", 6253, 1 }, +}; + static void ctrl_mmr_unlock(void) { /* Unlock all WKUP_CTRL_MMR0 module registers */ @@ -150,6 +195,14 @@ void k3_spl_init(void) if (ret) panic("Failed to initialize clk-k3!\n"); } + + remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls)); + remove_fwl_configs(cbass_hc2_fwls, ARRAY_SIZE(cbass_hc2_fwls)); + remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls)); + remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls)); + remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls)); + remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls)); + remove_fwl_configs(navss_cbass0_fwls, ARRAY_SIZE(navss_cbass0_fwls)); } /* Output System Firmware version info */