From patchwork Tue Mar 20 10:41:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick DELAUNAY X-Patchwork-Id: 888153 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4058cx526hz9sX0 for ; Tue, 20 Mar 2018 21:41:53 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 56650C21DFD; Tue, 20 Mar 2018 10:41:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3E98CC21C57; Tue, 20 Mar 2018 10:41:47 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B7D43C21C57; Tue, 20 Mar 2018 10:41:45 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id 714F7C21C29 for ; Tue, 20 Mar 2018 10:41:45 +0000 (UTC) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w2KAd2qO026758; Tue, 20 Mar 2018 11:41:43 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2grs18fgqr-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 20 Mar 2018 11:41:43 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6F17C49; Tue, 20 Mar 2018 10:41:42 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5899225E6; Tue, 20 Mar 2018 10:41:42 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by Safex1hubcas24.st.com (10.75.90.94) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 20 Mar 2018 11:41:42 +0100 Received: from localhost (10.201.23.85) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 20 Mar 2018 11:41:41 +0100 From: Patrick Delaunay To: Date: Tue, 20 Mar 2018 11:41:23 +0100 Message-ID: <1521542486-4827-1-git-send-email-patrick.delaunay@st.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.201.23.85] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-03-20_05:, , signatures=0 Cc: Tom Rini , Benjamin GAIGNARD Subject: [U-Boot] [PATCH 1/4] arm: timer: get frequency for arch timer armv7 in cp15 cntfrq X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Manage dynamic value for armv7 arch clock timer, when CONFIG_SYS_HZ_CLOCK is not defined. Get frequency from CP15 cntfrq information, initialized for example by first boot stage, clock driver or by BootRom. Signed-off-by: Patrick Delaunay --- arch/arm/cpu/armv7/arch_timer.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c index 545c518..3bcb944 100644 --- a/arch/arm/cpu/armv7/arch_timer.c +++ b/arch/arm/cpu/armv7/arch_timer.c @@ -12,12 +12,26 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_SYS_HZ_CLOCK +static inline u32 read_cntfrq(void) +{ + u32 frq; + + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq)); + return frq; +} +#endif + int timer_init(void) { gd->arch.tbl = 0; gd->arch.tbu = 0; +#ifdef CONFIG_SYS_HZ_CLOCK gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; +#else + gd->arch.timer_rate_hz = read_cntfrq(); +#endif return 0; } @@ -36,7 +50,7 @@ unsigned long long get_ticks(void) ulong timer_get_boot_us(void) { - return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / 1000000); + return lldiv(get_ticks(), gd->arch.timer_rate_hz / 1000000); } ulong get_tbclk(void) From patchwork Tue Mar 20 10:45:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick DELAUNAY X-Patchwork-Id: 888156 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4058jN5FzDz9sX0 for ; Tue, 20 Mar 2018 21:45:44 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id F1CF2C21C50; Tue, 20 Mar 2018 10:45:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4EC9AC21C29; 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Tue, 20 Mar 2018 10:45:35 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 20 Mar 2018 11:45:35 +0100 Received: from localhost (10.201.23.85) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 20 Mar 2018 11:45:35 +0100 From: Patrick Delaunay To: Date: Tue, 20 Mar 2018 11:45:14 +0100 Message-ID: <1521542716-5425-2-git-send-email-patrick.delaunay@st.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.201.23.85] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-03-20_05:, , signatures=0 Cc: Tom Rini , Benjamin GAIGNARD Subject: [U-Boot] [PATCH 2/4] stm32mp: add syscon for STGEN X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add STGEN as SYSCON device: allow access to device address defined in device tree Signed-off-by: Patrick Delaunay --- arch/arm/dts/stm32mp157-u-boot.dtsi | 7 +++++++ arch/arm/mach-stm32mp/Makefile | 1 + arch/arm/mach-stm32mp/include/mach/stm32.h | 5 +++++ arch/arm/mach-stm32mp/syscon.c | 23 +++++++++++++++++++++++ 4 files changed, 36 insertions(+) create mode 100644 arch/arm/mach-stm32mp/syscon.c diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi index d374b2b..7a9a4ce 100644 --- a/arch/arm/dts/stm32mp157-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157-u-boot.dtsi @@ -31,6 +31,13 @@ soc { u-boot,dm-pre-reloc; }; + + stgen: stgen@5C008000 { + compatible = "st,stm32-stgen"; + reg = <0x5C008000 0x1000>; + status = "okay"; + u-boot,dm-pre-reloc; + }; }; &clk_hsi { diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index 4620869..a495c53 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -6,5 +6,6 @@ obj-y += cpu.o obj-y += dram_init.o +obj-y += syscon.o obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 40faeb0..c7a2789 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -25,6 +25,11 @@ #define STM32_DDR_SIZE SZ_1G #ifndef __ASSEMBLY__ +/* enumerated used to identify the SYSCON driver instance */ +enum { + STM32MP_SYSCON_UNKNOWN, + STM32MP_SYSCON_STGEN, +}; /* * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c new file mode 100644 index 0000000..5641745 --- /dev/null +++ b/arch/arm/mach-stm32mp/syscon.c @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#include +#include +#include +#include + +static const struct udevice_id stm32mp_syscon_ids[] = { + { .compatible = "st,stm32-stgen", + .data = STM32MP_SYSCON_STGEN }, + { } +}; + +U_BOOT_DRIVER(syscon_stm32mp) = { + .name = "stmp32mp_syscon", + .id = UCLASS_SYSCON, + .of_match = stm32mp_syscon_ids, + .bind = dm_scan_fdt_dev, +}; From patchwork Tue Mar 20 10:41:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick DELAUNAY X-Patchwork-Id: 888154 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4058fT4jC0z9sX0 for ; Tue, 20 Mar 2018 21:43:13 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 37FD7C21D8A; Tue, 20 Mar 2018 10:43:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D872CC21CB1; Tue, 20 Mar 2018 10:43:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E6D47C21D65; Tue, 20 Mar 2018 10:43:01 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id 9E943C21CB1 for ; Tue, 20 Mar 2018 10:43:01 +0000 (UTC) Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w2KAdWs3027841; Tue, 20 Mar 2018 11:43:00 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2grsc1yg18-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 20 Mar 2018 11:43:00 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5136F34; Tue, 20 Mar 2018 10:43:00 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2134325C2; Tue, 20 Mar 2018 10:43:00 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 20 Mar 2018 11:43:00 +0100 Received: from localhost (10.201.23.85) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 20 Mar 2018 11:42:59 +0100 From: Patrick Delaunay To: Date: Tue, 20 Mar 2018 11:41:25 +0100 Message-ID: <1521542486-4827-3-git-send-email-patrick.delaunay@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521542486-4827-1-git-send-email-patrick.delaunay@st.com> References: <1521542486-4827-1-git-send-email-patrick.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.85] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-03-20_05:, , signatures=0 Cc: Tom Rini , Benjamin GAIGNARD Subject: [U-Boot] [PATCH 3/4] clock: stm32mp1: add stgen clock source change support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The STGEN is the clock source for the Cortex A7 arch timer. So after modification of its frequency, CP15 cntfreq is updated and a new timer init is performed. Signed-off-by: Patrick Delaunay --- drivers/clk/clk_stm32mp1.c | 46 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 55b0f79..c67aa44 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -27,6 +27,15 @@ #define TIMEOUT_200MS 200000 #define TIMEOUT_1S 1000000 +/* STGEN registers */ +#define STGENC_CNTCR 0x00 +#define STGENC_CNTSR 0x04 +#define STGENC_CNTCVL 0x08 +#define STGENC_CNTCVU 0x0C +#define STGENC_CNTFID0 0x20 + +#define STGENC_CNTCR_EN BIT(0) + /* RCC registers */ #define RCC_OCENSETR 0x0C #define RCC_OCENCLRR 0x10 @@ -1377,6 +1386,36 @@ static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc) return ret; } +static void stgen_config(struct stm32mp1_clk_priv *priv) +{ + int p; + u32 stgenc, cntfid0; + ulong rate; + + stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN); + + cntfid0 = readl(stgenc + STGENC_CNTFID0); + p = stm32mp1_clk_get_parent(priv, STGEN_K); + rate = stm32mp1_clk_get(priv, p); + + if (cntfid0 != rate) { + pr_debug("System Generic Counter (STGEN) update\n"); + clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); + writel(0x0, stgenc + STGENC_CNTCVL); + writel(0x0, stgenc + STGENC_CNTCVU); + writel(rate, stgenc + STGENC_CNTFID0); + setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); + + __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate)); + + /* need to update gd->arch.timer_rate_hz with new frequency */ + timer_init(); + pr_debug("gd->arch.timer_rate_hz = %x\n", + (u32)gd->arch.timer_rate_hz); + pr_debug("Tick = %x\n", (u32)(get_ticks())); + } +} + static int set_clkdiv(unsigned int clkdiv, u32 address) { u32 val; @@ -1544,8 +1583,10 @@ static int stm32mp1_clktree(struct udevice *dev) /* configure HSIDIV */ debug("configure HSIDIV\n"); - if (priv->osc[_HSI]) + if (priv->osc[_HSI]) { stm32mp1_hsidiv(rcc, priv->osc[_HSI]); + stgen_config(priv); + } /* select DIV */ debug("select DIV\n"); @@ -1634,6 +1675,9 @@ static int stm32mp1_clktree(struct udevice *dev) pkcs_config(priv, CLK_CKPER_DISABLED); } + /* STGEN clock source can change with CLK_STGEN_XXX */ + stgen_config(priv); + debug("oscillator off\n"); /* switch OFF HSI if not found in device-tree */ if (!priv->osc[_HSI]) From patchwork Tue Mar 20 10:41:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick DELAUNAY X-Patchwork-Id: 888155 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4058gM52N4z9sX0 for ; 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Tue, 20 Mar 2018 11:43:07 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 205B541; Tue, 20 Mar 2018 10:43:07 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DC78225D0; Tue, 20 Mar 2018 10:43:06 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 20 Mar 2018 11:43:06 +0100 Received: from localhost (10.201.23.85) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 20 Mar 2018 11:43:06 +0100 From: Patrick Delaunay To: Date: Tue, 20 Mar 2018 11:41:26 +0100 Message-ID: <1521542486-4827-4-git-send-email-patrick.delaunay@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521542486-4827-1-git-send-email-patrick.delaunay@st.com> References: <1521542486-4827-1-git-send-email-patrick.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.85] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-03-20_05:, , signatures=0 Cc: Tom Rini , Benjamin GAIGNARD Subject: [U-Boot] [PATCH 4/4] stm32mp1: change STGEN clock source to HSE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" No more use static frequency HSI = 64MHz for STGEN clock but HSE (with higher accurency) by default. Need to remove CONFIG_SYS_HZ_CLOCK as arch timer frequency is provided at boot by BootRom and cp15 cntfrq and modified during clock tree initialization if needed. When HSI is no more used by any device, this internal oscillator can be switched off to reduce consumption. Signed-off-by: Patrick Delaunay --- arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 1 + include/configs/stm32mp1.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index 5d43753..2caa939 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -76,6 +76,7 @@ st,pkcs = < CLK_CKPER_DISABLED CLK_SDMMC12_PLL3R + CLK_STGEN_HSE CLK_I2C46_PCLK5 CLK_I2C12_PCLK1 CLK_SDMMC3_PLL3R diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index 8159101..da0e259 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -18,7 +18,6 @@ */ #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_ARCH_TIMER -#define CONFIG_SYS_HZ_CLOCK 64000000 /* * malloc() pool size