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[167.179.157.192]) by smtp.gmail.com with ESMTPSA id f5-20020aa78b05000000b005d9984a947bsm11662650pfd.139.2023.03.23.03.36.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 03:36:12 -0700 (PDT) From: Jonathan Liu To: u-boot@lists.denx.de Cc: Kever Yang , YouMin Chen , Jagan Teki , Jonathan Liu Subject: [PATCH] ram: rk3399: add missing high row detection Date: Thu, 23 Mar 2023 21:35:58 +1100 Message-Id: <20230323103558.185456-1-net147@gmail.com> X-Mailer: git-send-email 2.40.0 MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 23 Mar 2023 13:18:17 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean For 2 GB LPDDR4 single-rank RAM with 16 rows, the Rockchip ddr init bin prints: "Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB" U-Boot TPL prints: "BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB" Add missing high row detection so that U-Boot TPL prints Row=16, same as the Rockchip ddr init bin: "BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB" Signed-off-by: Jonathan Liu Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index b1fea04e84..b597448203 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -2749,6 +2749,8 @@ static u64 dram_detect_cap(struct dram_info *dram, /* detect cs1 row */ sdram_detect_cs1_row(cap_info, params->base.dramtype); + sdram_detect_high_row(cap_info); + /* detect die bw */ sdram_detect_dbw(cap_info, params->base.dramtype);