From patchwork Wed Mar 22 12:15:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 1759797 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PhSBL2snjz247d for ; Wed, 22 Mar 2023 23:16:26 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 69AEC3850431 for ; Wed, 22 Mar 2023 12:16:24 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by sourceware.org (Postfix) with ESMTPS id 8A10C3850863 for ; Wed, 22 Mar 2023 12:16:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8A10C3850863 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp85t1679487360t6m7n54p Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 22 Mar 2023 20:15:59 +0800 (CST) X-QQ-SSF: 01400000000000E0N000000A0000000 X-QQ-FEAT: +ynUkgUhZJnoh7CkChI1oODHMkWAjyXxGYp8AdIFvyiXh5skMXrpj3BJdmX44 jXqeCX9DfDHYdYVPIoAtPzqIUmm9WDRWFgrD7PyB19An8kaJI85HOii2nGNwuiklZ7Ji+kp qKH56VLlcUQ5EDTo/N0XRDRD4Ml5pIpil0fAG1vWeSla7wGxN25Li/KLFxjPERo/pkv94lT AyC8dGtKyHNabF0XnMTOTEn88KNZOn/NeaMfhNeXqBpb5sFtLyaALD71pIrOuSTIer3cOQw PhH7lrDafZS+NK08d+WHRomGyyQRfNXLb81EpQtL1vlsnYWy034TNVh7eAIXdVeCagBRjFX SRjG0RCTcthWhpAkz9ENdsoTglMcngqra8Wy3XdhUZNh2hzsCwcP0fV1QqEuEbMQCBgOjyC +vh12CwHnOqOoqO95qRDYQ== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Fix redundant vmv1r.v instruction in vmsge.vx codegen Date: Wed, 22 Mar 2023 20:15:56 +0800 Message-Id: <20230322121556.94496-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong Current expansion of vmsge will make RA produce redundant vmv1r.v. testcase: void f1 (void * in, void *out, int32_t x) { vbool32_t mask = *(vbool32_t*)in; asm volatile ("":::"memory"); vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, x, 4); vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (mask, m3, v, x, 4); m4 = __riscv_vmsge_vv_i32m1_b32_m (m4, v2, v2, 4); __riscv_vsm_v_b32 (out, m4, 4); } Before this patch: f1: vsetvli a5,zero,e8,mf4,ta,ma vlm.v v0,0(a0) vsetivli zero,4,e32,m1,ta,mu vle32.v v3,0(a0) vle32.v v2,0(a0),v0.t vmslt.vx v1,v3,a2 vmnot.m v1,v1 vmslt.vx v1,v3,a2,v0.t vmxor.mm v1,v1,v0 vmv1r.v v0,v1 vmsge.vv v2,v2,v2,v0.t vsm.v v2,0(a1) ret After this patch: f1: vsetvli a5,zero,e8,mf4,ta,ma vlm.v v0,0(a0) vsetivli zero,4,e32,m1,ta,mu vle32.v v3,0(a0) vle32.v v2,0(a0),v0.t vmslt.vx v1,v3,a2 vmnot.m v1,v1 vmslt.vx v1,v3,a2,v0.t vmxor.mm v0,v1,v0 vmsge.vv v2,v2,v2,v0.t vsm.v v2,0(a1) ret gcc/ChangeLog: * config/riscv/vector.md: Fix redundant vmv1r.v. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/binop_vx_constraint-150.c: Adapt assembly check. --- gcc/config/riscv/vector.md | 15 +++++++-------- .../riscv/rvv/base/binop_vx_constraint-150.c | 2 +- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index ebb014aecb1..f06d68be80f 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -4111,6 +4111,7 @@ { enum rtx_code code = GET_CODE (operands[3]); rtx undef = RVV_VUNDEF (mode); + rtx tmp = gen_reg_rtx (mode); if (code == GEU && rtx_equal_p (operands[5], const0_rtx)) { /* If vmsgeu with 0 immediate, expand it to vmset. */ @@ -4157,12 +4158,11 @@ - pseudoinstruction: vmsge{u}.vx vd, va, x - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd. */ emit_insn ( - gen_pred_cmp_scalar (operands[0], operands[1], operands[2], + gen_pred_cmp_scalar (tmp, operands[1], operands[2], operands[3], operands[4], operands[5], operands[6], operands[7], operands[8])); emit_insn (gen_pred_nand (operands[0], CONSTM1_RTX (mode), - undef, operands[0], operands[0], - operands[6], operands[8])); + undef, tmp, tmp, operands[6], operands[8])); } else { @@ -4171,13 +4171,12 @@ /* masked va >= x, vd == v0 - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt - expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt. */ - rtx reg = gen_reg_rtx (mode); emit_insn (gen_pred_cmp_scalar ( - reg, CONSTM1_RTX (mode), undef, operands[3], operands[4], + tmp, CONSTM1_RTX (mode), undef, operands[3], operands[4], operands[5], operands[6], operands[7], operands[8])); emit_insn ( gen_pred_andnot (operands[0], CONSTM1_RTX (mode), undef, - operands[1], reg, operands[6], operands[8])); + operands[1], tmp, operands[6], operands[8])); } else { @@ -4186,10 +4185,10 @@ - expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0. */ emit_insn (gen_pred_cmp_scalar ( - operands[0], operands[1], operands[2], operands[3], operands[4], + tmp, operands[1], operands[2], operands[3], operands[4], operands[5], operands[6], operands[7], operands[8])); emit_insn (gen_pred (XOR, mode, operands[0], - CONSTM1_RTX (mode), undef, operands[0], + CONSTM1_RTX (mode), undef, tmp, operands[1], operands[6], operands[8])); } } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-150.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-150.c index 55a222f47ea..e92a8115f09 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-150.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-150.c @@ -18,4 +18,4 @@ void f1 (void * in, void *out, int32_t x) /* { dg-final { scan-assembler-times {vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ /* { dg-final { scan-assembler-times {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ /* { dg-final { scan-assembler-times {vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ -/* { dg-final { scan-assembler-times {vmv} 1 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */