From patchwork Wed Mar 22 05:06:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 1759701 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PhGfk1Fcbz246f for ; Wed, 22 Mar 2023 16:06:54 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F1075385B50D for ; Wed, 22 Mar 2023 05:06:51 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg156.qq.com (smtpbg156.qq.com [15.184.82.18]) by sourceware.org (Postfix) with ESMTPS id 900C53858D38 for ; Wed, 22 Mar 2023 05:06:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 900C53858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp79t1679461589tcbdax40 Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 22 Mar 2023 13:06:28 +0800 (CST) X-QQ-SSF: 01400000000000E0N000000A0000000 X-QQ-FEAT: /rrU+puPB7SGB73/NpMLUkjdH7aLxttf91ksS6JWWsVWjxzWMVgbkbosjgNl4 iQxBHmT9IdLhBc0JAJdISWDa23Gw4V+UmDgFg/q3MnFfpDMOPhr+1LQ4tDgFALBJlWjhZp3 WTRHkkHHxocdvClb1K6RGcR4P9kE26oSN1zkcV382nbDRVW5PqlJo5ydBCGwA/Sk/DAxXHk pmKzpbpvQ/txNIZmw3lgj1sHIU11tuNuWaR6p+QEszWnZq81Iw0IKLdeXw9B17X4SxLWNt3 m+H/GdR+wH8pxZO8AqYnmND7da6mxq+hs/afaClSzQa1e5jVoNlUnt6La1jkoklMZV5gFui emehPTNJD/F1pVLKiUcj9ey3H1CPFFqFAhI7Ba2zayHpQCerfEG1A7M+CcB2i9pwLGwL4n1 6U728iCRUHI= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Fix PR109228 Date: Wed, 22 Mar 2023 13:06:23 +0800 Message-Id: <20230322050623.229416-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong This patch fix PR109228 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109228 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vlenb): Add __riscv_vlenb support. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlenb): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct vlenb_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vlenb-1.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 17 +++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 1 + .../riscv/riscv-vector-builtins-shapes.cc | 25 ++++++++++ .../riscv/riscv-vector-builtins-shapes.h | 1 + gcc/config/riscv/riscv-vector-builtins.cc | 7 +++ .../gcc.target/riscv/rvv/base/vlenb-1.c | 46 +++++++++++++++++++ 7 files changed, 98 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlenb-1.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 839eb66efb2..52467bbc961 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1658,6 +1658,21 @@ public: } }; +/* Implements vlenb. */ +class vlenb : public function_base +{ +public: + bool apply_vl_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + machine_mode mode = GET_MODE (e.target); + rtx vlenb = gen_int_mode (BYTES_PER_RISCV_VECTOR, mode); + emit_move_insn (e.target, vlenb); + return e.target; + } +}; + static CONSTEXPR const vsetvl vsetvl_obj; static CONSTEXPR const vsetvl vsetvlmax_obj; static CONSTEXPR const loadstore vle_obj; @@ -1868,6 +1883,7 @@ static CONSTEXPR const vset vset_obj; static CONSTEXPR const vget vget_obj; static CONSTEXPR const read_vl read_vl_obj; static CONSTEXPR const vleff vleff_obj; +static CONSTEXPR const vlenb vlenb_obj; /* Declare the function base NAME, pointing it to an instance of class _obj. */ @@ -2084,5 +2100,6 @@ BASE (vset) BASE (vget) BASE (read_vl) BASE (vleff) +BASE (vlenb) } // end namespace riscv_vector diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 14e8a55cd97..0196f80b69e 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -240,6 +240,7 @@ extern const function_base *const vset; extern const function_base *const vget; extern const function_base *const read_vl; extern const function_base *const vleff; +extern const function_base *const vlenb; } } // end namespace riscv_vector diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 198ccfd86b7..3f1513cb9fd 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -38,6 +38,7 @@ along with GCC; see the file COPYING3. If not see /* Internal helper functions for gimple fold use. */ DEF_RVV_FUNCTION (read_vl, read_vl, none_preds, p_none_void_ops) +DEF_RVV_FUNCTION (vlenb, vlenb, none_preds, ul_none_void_ops) /* 6. Configuration-Setting Instructions. */ diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index edb0d34b81c..0682f81400a 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -553,6 +553,30 @@ struct fault_load_def : public build_base } }; +/* vlenb_def class. */ +struct vlenb_def : public function_shape +{ + void build (function_builder &b, + const function_group_info &group) const override + { + auto_vec argument_types; + function_instance function_instance (group.base_name, *group.base, + *group.shape, group.ops_infos.types[0], + group.preds[0], &group.ops_infos); + b.add_unique_function (function_instance, (*group.shape), + long_unsigned_type_node, argument_types); + } + + char *get_name (function_builder &b, const function_instance &instance, + bool overloaded_p) const override + { + if (overloaded_p) + return nullptr; + b.append_base_name (instance.base_name); + return b.finish_name (); + } +}; + SHAPE(vsetvl, vsetvl) SHAPE(vsetvl, vsetvlmax) SHAPE(loadstore, loadstore) @@ -572,5 +596,6 @@ SHAPE(vset, vset) SHAPE(vget, vget) SHAPE(read_vl, read_vl) SHAPE(fault_load, fault_load) +SHAPE(vlenb, vlenb) } // end namespace riscv_vector diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.h b/gcc/config/riscv/riscv-vector-builtins-shapes.h index 30780845f7b..aee2f94b04c 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.h +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.h @@ -43,6 +43,7 @@ extern const function_shape *const vset; extern const function_shape *const vget; extern const function_shape *const read_vl; extern const function_shape *const fault_load; +extern const function_shape *const vlenb; } } // end namespace riscv_vector diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 0df3cd15119..bd16fe9db7d 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -2130,6 +2130,13 @@ static CONSTEXPR const rvv_op_info p_none_void_ops rvv_arg_type_info (RVV_BASE_size), /* Return type */ void_args /* Args */}; +/* A static operand information for unsigned long func () function registration. */ +static CONSTEXPR const rvv_op_info ul_none_void_ops + = {none_ops, /* Types */ + OP_TYPE_none, /* Suffix */ + rvv_arg_type_info (RVV_BASE_unsigned_long), /* Return type */ + void_args /* Args */}; + /* A list of all RVV base function types. */ static CONSTEXPR const function_type_info function_types[] = { #define DEF_RVV_TYPE_INDEX(VECTOR, MASK, SIGNED, UNSIGNED, EEW8_INDEX, EEW16_INDEX, \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlenb-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlenb-1.c new file mode 100644 index 00000000000..a02fe9e98c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlenb-1.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ + +#include "riscv_vector.h" + +void f0 (char *x, char * p1, char * p2, char * p3) { + vbool32_t bp1 = *(vbool32_t*)p1; + vbool32_t bp2 = *(vbool32_t*)p2; + vbool32_t bp3 = *(vbool32_t*)p3; + asm volatile ("":::"memory"); + *(vbool32_t *)(x + (__riscv_vlenb())) = bp2; + *(vbool32_t *)(x) = bp1; + *(vbool32_t *)(x + (__riscv_vlenb())*2) = bp3; +} + +void f1 (char *x, char * p1, char * p2, char * p3) { + vbool32_t bp1 = *(vbool32_t*)p1; + vbool32_t bp2 = *(vbool32_t*)p2; + vbool32_t bp3 = *(vbool32_t*)p3; + asm volatile ("":::"memory"); + *(vbool32_t *)(x + (__riscv_vlenb() / 2)) = bp2; + *(vbool32_t *)(x) = bp1; + *(vbool32_t *)(x + (__riscv_vlenb() / 2)*2) = bp3; +} + +void f2 (char *x, char * p1, char * p2, char * p3) { + vbool32_t bp1 = *(vbool32_t*)p1; + vbool32_t bp2 = *(vbool32_t*)p2; + vbool32_t bp3 = *(vbool32_t*)p3; + asm volatile ("":::"memory"); + *(vbool32_t *)(x + (__riscv_vlenb() / 4)) = bp2; + *(vbool32_t *)(x) = bp1; + *(vbool32_t *)(x + (__riscv_vlenb() / 4)*2) = bp3; +} + +void f3 (char *x, char * p1, char * p2, char * p3) { + vbool32_t bp1 = *(vbool32_t*)p1; + vbool32_t bp2 = *(vbool32_t*)p2; + vbool32_t bp3 = *(vbool32_t*)p3; + asm volatile ("":::"memory"); + *(vbool32_t *)(x + (__riscv_vlenb() / 4)) = bp2; + *(vbool32_t *)(x) = bp1; + *(vbool32_t *)(x + (__riscv_vlenb() / 4)*2) = bp3; +} + +/* { dg-final { scan-assembler-times {vsm\.v} 12 } } */