From patchwork Thu Mar 16 11:39:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejas Belagod X-Patchwork-Id: 1757858 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=ZTbrPhVC; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Pclgr3NP4z2470 for ; Thu, 16 Mar 2023 22:40:40 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 476DD3857B8E for ; Thu, 16 Mar 2023 11:40:37 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 476DD3857B8E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1678966837; bh=Y3wNGh86WUBpHrqiOq6ULjnLmmzptYQeL5AMp7g0Lkc=; h=To:CC:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=ZTbrPhVC/tsH3d4ndwCLDiqJfOwgxrhGxfvwBn6Nw4XUpkbze5P2VC4t5WShbH0k1 sF1jmJEYeAoH/l0OL3P0Et78372kEKJiyCstZNHGP/elj9bsFUVOJmKzypQhg42G48 KI78/iV7iac8+K7wfU9rR2mklmP/7aGI4vVsx0+A= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-vi1eur04on2043.outbound.protection.outlook.com [40.107.8.43]) by sourceware.org (Postfix) with ESMTPS id 013C43857C4F for ; Thu, 16 Mar 2023 11:40:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 013C43857C4F Received: from AS9P194CA0027.EURP194.PROD.OUTLOOK.COM (2603:10a6:20b:46d::22) by DBBPR08MB5915.eurprd08.prod.outlook.com (2603:10a6:10:20d::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.31; Thu, 16 Mar 2023 11:40:06 +0000 Received: from AM7EUR03FT054.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:46d:cafe::5c) by AS9P194CA0027.outlook.office365.com (2603:10a6:20b:46d::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.31 via Frontend Transport; Thu, 16 Mar 2023 11:40:06 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM7EUR03FT054.mail.protection.outlook.com (100.127.140.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6199.16 via Frontend Transport; Thu, 16 Mar 2023 11:40:06 +0000 Received: ("Tessian outbound b29c0599cbc9:v135"); Thu, 16 Mar 2023 11:40:05 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 389fe9ca54a8e6f7 X-CR-MTA-TID: 64aa7808 Received: from f7031e11db2b.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 7D2A4021-8886-49D9-83D0-84A6F476036E.1; Thu, 16 Mar 2023 11:39:58 +0000 Received: from EUR04-DB3-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id f7031e11db2b.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 16 Mar 2023 11:39:58 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=irwl8O45bAgAquIYW843NGaJGM5zQlDzUzQtgff9+b/gB6c+ps3SyJBrHO277q8uwVJAUxIQ+G4jy+TEYtLiuNpWL662M+lqrM48fX9PHwSZI5MLJ7qRTp6en/H5k/FQ7aU4GaB0KRp5S4cmFtEgwAx5OTvSkG4E9qRvbdlsJouUkl5SoXDP85j4ms6jbhZaNXpBFiqk7au5sYrFRbWwke90+ALCCouPhM0XEorwD42Wezc7MxRLWchbDhIDN7exAVMOWsfV3CLl/p1QAAl5hMhI23ECPJFzK1I4sydHq2/Pjsi+acdJ2Ta/SCPooCjxMFP8/gmknWLIyUiWrTBI2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Y3wNGh86WUBpHrqiOq6ULjnLmmzptYQeL5AMp7g0Lkc=; b=CqvGcS0TDGbVARcN6CK+7wSXLNrHBDosanHcFT/68pObXztzPT+QD0/zX403FpzLnZm0f5FSUAM8O6eOdKd5zUWui8EPM0uCtNdu1nwD5EO4bHzxe/RHW7v8hZsLpzeC0S+B3po5COg56Jj7bcwAe42HxMr6Q97N1sWsXbbulNbViGI202ufLnqoJVy21iPcm+tKa8/MK25NjYG+7GUSB6C+cyAhhxqsqyqrgxfnWVN/LnSgGMyrfDSztbRfloNsbUaC84EMXYCqs7jyLEOrwtlUs6gXotVVBFUk4UKjk6LlUXfM0GIi6r0zAN+C0IgRdApgOPxb4gl7lMrhxf0ERg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none Received: from AS9PR05CA0179.eurprd05.prod.outlook.com (2603:10a6:20b:496::35) by DU0PR08MB8374.eurprd08.prod.outlook.com (2603:10a6:10:409::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.31; Thu, 16 Mar 2023 11:39:49 +0000 Received: from AM7EUR03FT011.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:496:cafe::51) by AS9PR05CA0179.outlook.office365.com (2603:10a6:20b:496::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.31 via Frontend Transport; Thu, 16 Mar 2023 11:39:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AM7EUR03FT011.mail.protection.outlook.com (100.127.140.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6199.17 via Frontend Transport; Thu, 16 Mar 2023 11:39:49 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.17; Thu, 16 Mar 2023 11:39:48 +0000 Received: from e124570.cambridge.arm.com (10.2.79.30) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.17 via Frontend Transport; Thu, 16 Mar 2023 11:39:48 +0000 To: CC: Tejas Belagod , Subject: [PATCH] [PR96339] AArch64: Optimise svlast[ab] Date: Thu, 16 Mar 2023 11:39:27 +0000 Message-ID: <20230316113927.4967-1-tejas.belagod@arm.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT011:EE_|DU0PR08MB8374:EE_|AM7EUR03FT054:EE_|DBBPR08MB5915:EE_ X-MS-Office365-Filtering-Correlation-Id: 93fe786f-fac2-42cb-01a8-08db26133066 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: +6p1T30oGI4MrjN2zgZg4psTcNXnmdvpunBn5yhW4z3rhf3EuxWd0glVJVi+eSD1Vxb/OBdyxCdGY9GUbag929TX14JHqCeFcD6RnUP8a/MRc2o3jZSxjnybp9OC4WM2v+MkxT6SFEglf+e61zLOxnUJep0s+7ru9FH28ycBNNpCTOGER4Oqq5WZwYOU9Ryltu3jb2R64/sn1P8IWkOUGu92H/R78bTV4d2IUTB+AsYiQDwmDfyzUuHoN8hT32SmB5XCFCRqt1aAmEvnB5kUn1HbzL4HVNyBKzD2hlBLmz8Ec2iuqX/CsJCObyj25CjUOlZgMfn7q0YKue5dAp+zfWzm/93R7lnyWQLCAf3HwAyTgLikWMqWsUY3W0z940/hcA9Nj1e3P8XT5YYewNlg29fhQRnNUxnXx3ArvbjPHfHLYHsSnR72ImdJAZbe8TjvppJC6CJ8O3V4CDDdi/SokizknnUwlocotXGJ9IZlgzGJALAsz/yozRFonSeGSaFOW4UTyXMw+ou15aSNScYAFpOCsTRU/tbSeAVPMxj4dgwTcbMJ0SpOJVx/OE9awPTHRuqSn5LEUyhhdXpmdJuJnFwyvgxdyTLPgnQLxpDQY5SCJUqSLfCUHykYYPEJpsJ20PuEO1UuQ47ip/X1CqiGCaTAl18QvHK9tX81Meb+9R5ipk01Dtz1M87k2cJui9qIxOZ2+qFMehjKhoHpX7kZQG/C9IPnXbgh9oKupTGXi4o+Fe9afZrzPhz2lBExRrYMRGH08nLezz+xLS2kNL8vig== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230025)(4636009)(346002)(396003)(39860400002)(376002)(136003)(451199018)(36840700001)(40470700004)(46966006)(84970400001)(40460700003)(4326008)(41300700001)(8936002)(5660300002)(44832011)(2906002)(36756003)(86362001)(36860700001)(356005)(81166007)(82740400003)(30864003)(7696005)(478600001)(70586007)(8676002)(70206006)(6666004)(6916009)(40480700001)(82310400005)(47076005)(426003)(316002)(54906003)(83380400001)(1076003)(26005)(2616005)(186003)(336012)(36900700001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8374 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM7EUR03FT054.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 044b7548-ebe5-46c1-e89e-08db2613267b X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5h+r3t19TPeaGdmz3vX9OYIrUnW5oVKUGlirbY8PTZBpAn/tNRm7/6K2ypQz6MeqmAu5ilpNvtI+YD7H3A6Q9WkevRl/3Em7DbXcNAd4gqur9KF/EGYgK/LypFP0CUk3AuVYMWA3AMYCkj+fhckRWt1zP61CF0HB1CYBi1piwaNJFYxghZfIenvU8sF30I9fEfY0vsE+VpC8eCeHhCci7twweLW4JGAEs287fEj1pVnJmLvX8dVs6yUy3oDgRETL1Uopd6O/DRMZF7GzoThwYeyWNKHL1zBgLBesbNBdD1+JH3dDIlDIU8y3QjRh5gqf6QBge/get0ASds/Bl+R/gphjv9dM7AnkpjHVN5SmK2pnI8uz0l9/uVd36+m0uHD6+iDCVMzCRDDAmMVrvzb/q3AKU7oaddeZLeVne1Kp5AQm/Wwv5w03wOmAd6T12dkiKunbgiZFLssh4o1uUdjpFsaJWE6z/Z6DiV94JjaCN8//fz8F7vQ1GBgqgbY3Nmi1LRKu6nAtxAlSl0/iF0JjnEkkAHJz1odWVVYtV5pO20mLlui3vSmw1Z7qKM2RUPpUgIldNJ+ZFND28ohdxExC5Y5Yz69HWqhYN+Y/MFDon69cjWVko3EKbD8G5+2XLJlSL/RHr4wABjkh8goIqwwf8D4rJftHduqL2eM/6BifKzoukxYfqmJmxfRKQPCdxKJ93eHcvTjRE5nCX876BU/j0jQKksHntze8sklwG+0gAoc= X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230025)(4636009)(346002)(396003)(39860400002)(376002)(136003)(451199018)(36840700001)(46966006)(40470700004)(86362001)(36756003)(81166007)(82740400003)(36860700001)(478600001)(2906002)(41300700001)(5660300002)(8936002)(30864003)(44832011)(336012)(40480700001)(4326008)(82310400005)(40460700003)(70586007)(186003)(26005)(2616005)(426003)(54906003)(83380400001)(47076005)(1076003)(316002)(8676002)(6666004)(6916009)(7696005)(70206006)(84970400001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2023 11:40:06.0501 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 93fe786f-fac2-42cb-01a8-08db26133066 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT054.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB5915 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tejas Belagod via Gcc-patches From: Tejas Belagod Reply-To: Tejas Belagod Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Tejas Belagod This PR optimizes an SVE intrinsics sequence where svlasta (svptrue_pat_b8 (SV_VL1), x) a scalar is selected based on a constant predicate and a variable vector. This sequence is optimized to return the correspoding element of a NEON vector. For eg. svlasta (svptrue_pat_b8 (SV_VL1), x) returns umov w0, v0.b[1] Likewise, svlastb (svptrue_pat_b8 (SV_VL1), x) returns umov w0, v0.b[0] This optimization only works provided the constant predicate maps to a range that is within the bounds of a 128-bit NEON register. gcc/ChangeLog: PR target/96339 * config/aarch64/aarch64-sve-builtins-base.cc (svlast_impl::fold): Fold sve calls that have a constant input predicate vector. (svlast_impl::is_lasta): Query to check if intrinsic is svlasta. (svlast_impl::is_lastb): Query to check if intrinsic is svlastb. (svlast_impl::vect_all_same): Check if all vector elements are equal. gcc/testsuite/ChangeLog: PR target/96339 * gcc.target/aarch64/sve/acle/general-c/svlast.c: New. * gcc.target/aarch64/sve/acle/general-c/svlast128_run.c: New. * gcc.target/aarch64/sve/acle/general-c/svlast256_run.c: New. * gcc.target/aarch64/sve/pcs/return_4.c (caller_bf16): Fix asm to expect optimized code for function body. * gcc.target/aarch64/sve/pcs/return_4_128.c (caller_bf16): Likewise. * gcc.target/aarch64/sve/pcs/return_4_256.c (caller_bf16): Likewise. * gcc.target/aarch64/sve/pcs/return_4_512.c (caller_bf16): Likewise. * gcc.target/aarch64/sve/pcs/return_4_1024.c (caller_bf16): Likewise. * gcc.target/aarch64/sve/pcs/return_4_2048.c (caller_bf16): Likewise. * gcc.target/aarch64/sve/pcs/return_5.c (caller_bf16): Likewise. * gcc.target/aarch64/sve/pcs/return_5_128.c (caller_bf16): Likewise. * gcc.target/aarch64/sve/pcs/return_5_256.c (caller_bf16): Likewise. * gcc.target/aarch64/sve/pcs/return_5_512.c (caller_bf16): Likewise. * gcc.target/aarch64/sve/pcs/return_5_1024.c (caller_bf16): Likewise. * gcc.target/aarch64/sve/pcs/return_5_2048.c (caller_bf16): Likewise. --- .../aarch64/aarch64-sve-builtins-base.cc | 124 +++++++ .../aarch64/sve/acle/general-c/svlast.c | 63 ++++ .../sve/acle/general-c/svlast128_run.c | 313 +++++++++++++++++ .../sve/acle/general-c/svlast256_run.c | 314 ++++++++++++++++++ .../gcc.target/aarch64/sve/pcs/return_4.c | 2 - .../aarch64/sve/pcs/return_4_1024.c | 2 - .../gcc.target/aarch64/sve/pcs/return_4_128.c | 2 - .../aarch64/sve/pcs/return_4_2048.c | 2 - .../gcc.target/aarch64/sve/pcs/return_4_256.c | 2 - .../gcc.target/aarch64/sve/pcs/return_4_512.c | 2 - .../gcc.target/aarch64/sve/pcs/return_5.c | 2 - .../aarch64/sve/pcs/return_5_1024.c | 2 - .../gcc.target/aarch64/sve/pcs/return_5_128.c | 2 - .../aarch64/sve/pcs/return_5_2048.c | 2 - .../gcc.target/aarch64/sve/pcs/return_5_256.c | 2 - .../gcc.target/aarch64/sve/pcs/return_5_512.c | 2 - 16 files changed, 814 insertions(+), 24 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/svlast.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/svlast128_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/svlast256_run.c diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc index cd9cace3c9b..db2b4dcaac9 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc @@ -1056,6 +1056,130 @@ class svlast_impl : public quiet public: CONSTEXPR svlast_impl (int unspec) : m_unspec (unspec) {} + bool is_lasta () const { return m_unspec == UNSPEC_LASTA; } + bool is_lastb () const { return m_unspec == UNSPEC_LASTB; } + + bool vect_all_same (tree v , int step) const + { + int i; + int nelts = vector_cst_encoded_nelts (v); + int first_el = 0; + + for (i = first_el; i < nelts; i += step) + if (VECTOR_CST_ENCODED_ELT (v, i) != VECTOR_CST_ENCODED_ELT (v, first_el)) + return false; + + return true; + } + + /* Fold a svlast{a/b} call with constant predicate to a BIT_FIELD_REF. + BIT_FIELD_REF lowers to a NEON element extract, so we have to make sure + the index of the element being accessed is in the range of a NEON vector + width. */ + gimple *fold (gimple_folder & f) const override + { + tree pred = gimple_call_arg (f.call, 0); + tree val = gimple_call_arg (f.call, 1); + + if (TREE_CODE (pred) == VECTOR_CST) + { + HOST_WIDE_INT pos; + unsigned int const_vg; + int i = 0; + int step = f.type_suffix (0).element_bytes; + int step_1 = gcd (step, VECTOR_CST_NPATTERNS (pred)); + int npats = VECTOR_CST_NPATTERNS (pred); + unsigned HOST_WIDE_INT nelts = vector_cst_encoded_nelts (pred); + tree b = NULL_TREE; + bool const_vl = aarch64_sve_vg.is_constant (&const_vg); + + /* We can optimize 2 cases common to variable and fixed-length cases + without a linear search of the predicate vector: + 1. LASTA if predicate is all true, return element 0. + 2. LASTA if predicate all false, return element 0. */ + if (is_lasta () && vect_all_same (pred, step_1)) + { + b = build3 (BIT_FIELD_REF, TREE_TYPE (f.lhs), val, + bitsize_int (step * BITS_PER_UNIT), bitsize_int (0)); + return gimple_build_assign (f.lhs, b); + } + + /* Handle the all-false case for LASTB where SVE VL == 128b - + return the highest numbered element. */ + if (is_lastb () && known_eq (BYTES_PER_SVE_VECTOR, 16) + && vect_all_same (pred, step_1) + && integer_zerop (VECTOR_CST_ENCODED_ELT (pred, 0))) + { + b = build3 (BIT_FIELD_REF, TREE_TYPE (f.lhs), val, + bitsize_int (step * BITS_PER_UNIT), + bitsize_int ((16 - step) * BITS_PER_UNIT)); + + return gimple_build_assign (f.lhs, b); + } + + /* If VECTOR_CST_NELTS_PER_PATTERN (pred) == 2 and every multiple of + 'step_1' in + [VECTOR_CST_NPATTERNS .. VECTOR_CST_ENCODED_NELTS - 1] + is zero, then we can treat the vector as VECTOR_CST_NPATTERNS + elements followed by all inactive elements. */ + if (!const_vl && VECTOR_CST_NELTS_PER_PATTERN (pred) == 2) + for (i = npats; i < nelts; i += step_1) + { + /* If there are active elements in the repeated pattern of + a variable-length vector, then return NULL as there is no way + to be sure statically if this falls within the NEON range. */ + if (!integer_zerop (VECTOR_CST_ENCODED_ELT (pred, i))) + return NULL; + } + + /* If we're here, it means either: + 1. The vector is variable-length and there's no active element in the + repeated part of the pattern, or + 2. The vector is fixed-length. + Fall-through to a linear search. */ + + /* Restrict the scope of search to NPATS if vector is + variable-length. */ + if (!VECTOR_CST_NELTS (pred).is_constant (&nelts)) + nelts = npats; + + /* Fall through to finding the last active element linearly for + for all cases where the last active element is known to be + within a statically-determinable range. */ + i = MAX ((int)nelts - step, 0); + for (; i >= 0; i -= step) + if (!integer_zerop (VECTOR_CST_ELT (pred, i))) + break; + + if (is_lastb ()) + { + /* For LASTB, the element is the last active element. */ + pos = i; + } + else + { + /* For LASTA, the element is one after last active element. */ + pos = i + step; + + /* If last active element is + last element, wrap-around and return first NEON element. */ + if (known_ge (pos, BYTES_PER_SVE_VECTOR)) + pos = 0; + } + + /* Out of NEON range. */ + if (pos < 0 || pos > 15) + return NULL; + + b = build3 (BIT_FIELD_REF, TREE_TYPE (f.lhs), val, + bitsize_int (step * BITS_PER_UNIT), + bitsize_int (pos * BITS_PER_UNIT)); + + return gimple_build_assign (f.lhs, b); + } + return NULL; + } + rtx expand (function_expander &e) const override { diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/svlast.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/svlast.c new file mode 100644 index 00000000000..fdbe5e309af --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/svlast.c @@ -0,0 +1,63 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include +#include "arm_sve.h" + +#define NAME(name, size, pat, sign, ab) \ + name ## _ ## size ## _ ## pat ## _ ## sign ## _ ## ab + +#define NAMEF(name, size, pat, sign, ab) \ + name ## _ ## size ## _ ## pat ## _ ## sign ## _ ## ab ## _false + +#define SVTYPE(size, sign) \ + sv ## sign ## int ## size ## _t + +#define STYPE(size, sign) sign ## int ## size ##_t + +#define SVELAST_DEF(size, pat, sign, ab, su) \ + STYPE (size, sign) __attribute__((noinline)) \ + NAME (foo, size, pat, sign, ab) (SVTYPE (size, sign) x) \ + { \ + return svlast ## ab (svptrue_pat_b ## size (pat), x); \ + } \ + STYPE (size, sign) __attribute__((noinline)) \ + NAMEF (foo, size, pat, sign, ab) (SVTYPE (size, sign) x) \ + { \ + return svlast ## ab (svpfalse (), x); \ + } + +#define ALL_PATS(SIZE, SIGN, AB, SU) \ + SVELAST_DEF (SIZE, SV_VL1, SIGN, AB, SU) \ + SVELAST_DEF (SIZE, SV_VL2, SIGN, AB, SU) \ + SVELAST_DEF (SIZE, SV_VL3, SIGN, AB, SU) \ + SVELAST_DEF (SIZE, SV_VL4, SIGN, AB, SU) \ + SVELAST_DEF (SIZE, SV_VL5, SIGN, AB, SU) \ + SVELAST_DEF (SIZE, SV_VL6, SIGN, AB, SU) \ + SVELAST_DEF (SIZE, SV_VL7, SIGN, AB, SU) \ + SVELAST_DEF (SIZE, SV_VL8, SIGN, AB, SU) \ + SVELAST_DEF (SIZE, SV_VL16, SIGN, AB, SU) + +#define ALL_SIGN(SIZE, AB) \ + ALL_PATS (SIZE, , AB, s) \ + ALL_PATS (SIZE, u, AB, u) + +#define ALL_SIZE(AB) \ + ALL_SIGN (8, AB) \ + ALL_SIGN (16, AB) \ + ALL_SIGN (32, AB) \ + ALL_SIGN (64, AB) + +#define ALL_POS() \ + ALL_SIZE (a) \ + ALL_SIZE (b) + + +ALL_POS() + +/* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.b} 52 } } */ +/* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.h} 50 } } */ +/* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tfmov\tw0, s0} 24 } } */ +/* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmov\tx0, d0} 32 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/svlast128_run.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/svlast128_run.c new file mode 100644 index 00000000000..5e1e9303d7b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/svlast128_run.c @@ -0,0 +1,313 @@ +/* { dg-do run { target aarch64_sve128_hw } } */ +/* { dg-options "-O3 -msve-vector-bits=128 -std=gnu99" } */ + +#include "svlast.c" + +int +main (void) +{ + int8_t res_8_SV_VL1__a = 1; + int8_t res_8_SV_VL2__a = 2; + int8_t res_8_SV_VL3__a = 3; + int8_t res_8_SV_VL4__a = 4; + int8_t res_8_SV_VL5__a = 5; + int8_t res_8_SV_VL6__a = 6; + int8_t res_8_SV_VL7__a = 7; + int8_t res_8_SV_VL8__a = 8; + int8_t res_8_SV_VL16__a = 0; + uint8_t res_8_SV_VL1_u_a = 1; + uint8_t res_8_SV_VL2_u_a = 2; + uint8_t res_8_SV_VL3_u_a = 3; + uint8_t res_8_SV_VL4_u_a = 4; + uint8_t res_8_SV_VL5_u_a = 5; + uint8_t res_8_SV_VL6_u_a = 6; + uint8_t res_8_SV_VL7_u_a = 7; + uint8_t res_8_SV_VL8_u_a = 8; + uint8_t res_8_SV_VL16_u_a = 0; + int16_t res_16_SV_VL1__a = 1; + int16_t res_16_SV_VL2__a = 2; + int16_t res_16_SV_VL3__a = 3; + int16_t res_16_SV_VL4__a = 4; + int16_t res_16_SV_VL5__a = 5; + int16_t res_16_SV_VL6__a = 6; + int16_t res_16_SV_VL7__a = 7; + int16_t res_16_SV_VL8__a = 0; + int16_t res_16_SV_VL16__a = 0; + uint16_t res_16_SV_VL1_u_a = 1; + uint16_t res_16_SV_VL2_u_a = 2; + uint16_t res_16_SV_VL3_u_a = 3; + uint16_t res_16_SV_VL4_u_a = 4; + uint16_t res_16_SV_VL5_u_a = 5; + uint16_t res_16_SV_VL6_u_a = 6; + uint16_t res_16_SV_VL7_u_a = 7; + uint16_t res_16_SV_VL8_u_a = 0; + uint16_t res_16_SV_VL16_u_a = 0; + int32_t res_32_SV_VL1__a = 1; + int32_t res_32_SV_VL2__a = 2; + int32_t res_32_SV_VL3__a = 3; + int32_t res_32_SV_VL4__a = 0; + int32_t res_32_SV_VL5__a = 0; + int32_t res_32_SV_VL6__a = 0; + int32_t res_32_SV_VL7__a = 0; + int32_t res_32_SV_VL8__a = 0; + int32_t res_32_SV_VL16__a = 0; + uint32_t res_32_SV_VL1_u_a = 1; + uint32_t res_32_SV_VL2_u_a = 2; + uint32_t res_32_SV_VL3_u_a = 3; + uint32_t res_32_SV_VL4_u_a = 0; + uint32_t res_32_SV_VL5_u_a = 0; + uint32_t res_32_SV_VL6_u_a = 0; + uint32_t res_32_SV_VL7_u_a = 0; + uint32_t res_32_SV_VL8_u_a = 0; + uint32_t res_32_SV_VL16_u_a = 0; + int64_t res_64_SV_VL1__a = 1; + int64_t res_64_SV_VL2__a = 0; + int64_t res_64_SV_VL3__a = 0; + int64_t res_64_SV_VL4__a = 0; + int64_t res_64_SV_VL5__a = 0; + int64_t res_64_SV_VL6__a = 0; + int64_t res_64_SV_VL7__a = 0; + int64_t res_64_SV_VL8__a = 0; + int64_t res_64_SV_VL16__a = 0; + uint64_t res_64_SV_VL1_u_a = 1; + uint64_t res_64_SV_VL2_u_a = 0; + uint64_t res_64_SV_VL3_u_a = 0; + uint64_t res_64_SV_VL4_u_a = 0; + uint64_t res_64_SV_VL5_u_a = 0; + uint64_t res_64_SV_VL6_u_a = 0; + uint64_t res_64_SV_VL7_u_a = 0; + uint64_t res_64_SV_VL8_u_a = 0; + uint64_t res_64_SV_VL16_u_a = 0; + int8_t res_8_SV_VL1__b = 0; + int8_t res_8_SV_VL2__b = 1; + int8_t res_8_SV_VL3__b = 2; + int8_t res_8_SV_VL4__b = 3; + int8_t res_8_SV_VL5__b = 4; + int8_t res_8_SV_VL6__b = 5; + int8_t res_8_SV_VL7__b = 6; + int8_t res_8_SV_VL8__b = 7; + int8_t res_8_SV_VL16__b = 15; + uint8_t res_8_SV_VL1_u_b = 0; + uint8_t res_8_SV_VL2_u_b = 1; + uint8_t res_8_SV_VL3_u_b = 2; + uint8_t res_8_SV_VL4_u_b = 3; + uint8_t res_8_SV_VL5_u_b = 4; + uint8_t res_8_SV_VL6_u_b = 5; + uint8_t res_8_SV_VL7_u_b = 6; + uint8_t res_8_SV_VL8_u_b = 7; + uint8_t res_8_SV_VL16_u_b = 15; + int16_t res_16_SV_VL1__b = 0; + int16_t res_16_SV_VL2__b = 1; + int16_t res_16_SV_VL3__b = 2; + int16_t res_16_SV_VL4__b = 3; + int16_t res_16_SV_VL5__b = 4; + int16_t res_16_SV_VL6__b = 5; + int16_t res_16_SV_VL7__b = 6; + int16_t res_16_SV_VL8__b = 7; + int16_t res_16_SV_VL16__b = 7; + uint16_t res_16_SV_VL1_u_b = 0; + uint16_t res_16_SV_VL2_u_b = 1; + uint16_t res_16_SV_VL3_u_b = 2; + uint16_t res_16_SV_VL4_u_b = 3; + uint16_t res_16_SV_VL5_u_b = 4; + uint16_t res_16_SV_VL6_u_b = 5; + uint16_t res_16_SV_VL7_u_b = 6; + uint16_t res_16_SV_VL8_u_b = 7; + uint16_t res_16_SV_VL16_u_b = 7; + int32_t res_32_SV_VL1__b = 0; + int32_t res_32_SV_VL2__b = 1; + int32_t res_32_SV_VL3__b = 2; + int32_t res_32_SV_VL4__b = 3; + int32_t res_32_SV_VL5__b = 3; + int32_t res_32_SV_VL6__b = 3; + int32_t res_32_SV_VL7__b = 3; + int32_t res_32_SV_VL8__b = 3; + int32_t res_32_SV_VL16__b = 3; + uint32_t res_32_SV_VL1_u_b = 0; + uint32_t res_32_SV_VL2_u_b = 1; + uint32_t res_32_SV_VL3_u_b = 2; + uint32_t res_32_SV_VL4_u_b = 3; + uint32_t res_32_SV_VL5_u_b = 3; + uint32_t res_32_SV_VL6_u_b = 3; + uint32_t res_32_SV_VL7_u_b = 3; + uint32_t res_32_SV_VL8_u_b = 3; + uint32_t res_32_SV_VL16_u_b = 3; + int64_t res_64_SV_VL1__b = 0; + int64_t res_64_SV_VL2__b = 1; + int64_t res_64_SV_VL3__b = 1; + int64_t res_64_SV_VL4__b = 1; + int64_t res_64_SV_VL5__b = 1; + int64_t res_64_SV_VL6__b = 1; + int64_t res_64_SV_VL7__b = 1; + int64_t res_64_SV_VL8__b = 1; + int64_t res_64_SV_VL16__b = 1; + uint64_t res_64_SV_VL1_u_b = 0; + uint64_t res_64_SV_VL2_u_b = 1; + uint64_t res_64_SV_VL3_u_b = 1; + uint64_t res_64_SV_VL4_u_b = 1; + uint64_t res_64_SV_VL5_u_b = 1; + uint64_t res_64_SV_VL6_u_b = 1; + uint64_t res_64_SV_VL7_u_b = 1; + uint64_t res_64_SV_VL8_u_b = 1; + uint64_t res_64_SV_VL16_u_b = 1; + + int8_t res_8_SV_VL1__a_false = 0; + int8_t res_8_SV_VL2__a_false = 0; + int8_t res_8_SV_VL3__a_false = 0; + int8_t res_8_SV_VL4__a_false = 0; + int8_t res_8_SV_VL5__a_false = 0; + int8_t res_8_SV_VL6__a_false = 0; + int8_t res_8_SV_VL7__a_false = 0; + int8_t res_8_SV_VL8__a_false = 0; + int8_t res_8_SV_VL16__a_false = 0; + uint8_t res_8_SV_VL1_u_a_false = 0; + uint8_t res_8_SV_VL2_u_a_false = 0; + uint8_t res_8_SV_VL3_u_a_false = 0; + uint8_t res_8_SV_VL4_u_a_false = 0; + uint8_t res_8_SV_VL5_u_a_false = 0; + uint8_t res_8_SV_VL6_u_a_false = 0; + uint8_t res_8_SV_VL7_u_a_false = 0; + uint8_t res_8_SV_VL8_u_a_false = 0; + uint8_t res_8_SV_VL16_u_a_false = 0; + int16_t res_16_SV_VL1__a_false = 0; + int16_t res_16_SV_VL2__a_false = 0; + int16_t res_16_SV_VL3__a_false = 0; + int16_t res_16_SV_VL4__a_false = 0; + int16_t res_16_SV_VL5__a_false = 0; + int16_t res_16_SV_VL6__a_false = 0; + int16_t res_16_SV_VL7__a_false = 0; + int16_t res_16_SV_VL8__a_false = 0; + int16_t res_16_SV_VL16__a_false = 0; + uint16_t res_16_SV_VL1_u_a_false = 0; + uint16_t res_16_SV_VL2_u_a_false = 0; + uint16_t res_16_SV_VL3_u_a_false = 0; + uint16_t res_16_SV_VL4_u_a_false = 0; + uint16_t res_16_SV_VL5_u_a_false = 0; + uint16_t res_16_SV_VL6_u_a_false = 0; + uint16_t res_16_SV_VL7_u_a_false = 0; + uint16_t res_16_SV_VL8_u_a_false = 0; + uint16_t res_16_SV_VL16_u_a_false = 0; + int32_t res_32_SV_VL1__a_false = 0; + int32_t res_32_SV_VL2__a_false = 0; + int32_t res_32_SV_VL3__a_false = 0; + int32_t res_32_SV_VL4__a_false = 0; + int32_t res_32_SV_VL5__a_false = 0; + int32_t res_32_SV_VL6__a_false = 0; + int32_t res_32_SV_VL7__a_false = 0; + int32_t res_32_SV_VL8__a_false = 0; + int32_t res_32_SV_VL16__a_false = 0; + uint32_t res_32_SV_VL1_u_a_false = 0; + uint32_t res_32_SV_VL2_u_a_false = 0; + uint32_t res_32_SV_VL3_u_a_false = 0; + uint32_t res_32_SV_VL4_u_a_false = 0; + uint32_t res_32_SV_VL5_u_a_false = 0; + uint32_t res_32_SV_VL6_u_a_false = 0; + uint32_t res_32_SV_VL7_u_a_false = 0; + uint32_t res_32_SV_VL8_u_a_false = 0; + uint32_t res_32_SV_VL16_u_a_false = 0; + int64_t res_64_SV_VL1__a_false = 0; + int64_t res_64_SV_VL2__a_false = 0; + int64_t res_64_SV_VL3__a_false = 0; + int64_t res_64_SV_VL4__a_false = 0; + int64_t res_64_SV_VL5__a_false = 0; + int64_t res_64_SV_VL6__a_false = 0; + int64_t res_64_SV_VL7__a_false = 0; + int64_t res_64_SV_VL8__a_false = 0; + int64_t res_64_SV_VL16__a_false = 0; + uint64_t res_64_SV_VL1_u_a_false = 0; + uint64_t res_64_SV_VL2_u_a_false = 0; + uint64_t res_64_SV_VL3_u_a_false = 0; + uint64_t res_64_SV_VL4_u_a_false = 0; + uint64_t res_64_SV_VL5_u_a_false = 0; + uint64_t res_64_SV_VL6_u_a_false = 0; + uint64_t res_64_SV_VL7_u_a_false = 0; + uint64_t res_64_SV_VL8_u_a_false = 0; + uint64_t res_64_SV_VL16_u_a_false = 0; + int8_t res_8_SV_VL1__b_false = 15; + int8_t res_8_SV_VL2__b_false = 15; + int8_t res_8_SV_VL3__b_false = 15; + int8_t res_8_SV_VL4__b_false = 15; + int8_t res_8_SV_VL5__b_false = 15; + int8_t res_8_SV_VL6__b_false = 15; + int8_t res_8_SV_VL7__b_false = 15; + int8_t res_8_SV_VL8__b_false = 15; + int8_t res_8_SV_VL16__b_false = 15; + uint8_t res_8_SV_VL1_u_b_false = 15; + uint8_t res_8_SV_VL2_u_b_false = 15; + uint8_t res_8_SV_VL3_u_b_false = 15; + uint8_t res_8_SV_VL4_u_b_false = 15; + uint8_t res_8_SV_VL5_u_b_false = 15; + uint8_t res_8_SV_VL6_u_b_false = 15; + uint8_t res_8_SV_VL7_u_b_false = 15; + uint8_t res_8_SV_VL8_u_b_false = 15; + uint8_t res_8_SV_VL16_u_b_false = 15; + int16_t res_16_SV_VL1__b_false = 7; + int16_t res_16_SV_VL2__b_false = 7; + int16_t res_16_SV_VL3__b_false = 7; + int16_t res_16_SV_VL4__b_false = 7; + int16_t res_16_SV_VL5__b_false = 7; + int16_t res_16_SV_VL6__b_false = 7; + int16_t res_16_SV_VL7__b_false = 7; + int16_t res_16_SV_VL8__b_false = 7; + int16_t res_16_SV_VL16__b_false = 7; + uint16_t res_16_SV_VL1_u_b_false = 7; + uint16_t res_16_SV_VL2_u_b_false = 7; + uint16_t res_16_SV_VL3_u_b_false = 7; + uint16_t res_16_SV_VL4_u_b_false = 7; + uint16_t res_16_SV_VL5_u_b_false = 7; + uint16_t res_16_SV_VL6_u_b_false = 7; + uint16_t res_16_SV_VL7_u_b_false = 7; + uint16_t res_16_SV_VL8_u_b_false = 7; + uint16_t res_16_SV_VL16_u_b_false = 7; + int32_t res_32_SV_VL1__b_false = 3; + int32_t res_32_SV_VL2__b_false = 3; + int32_t res_32_SV_VL3__b_false = 3; + int32_t res_32_SV_VL4__b_false = 3; + int32_t res_32_SV_VL5__b_false = 3; + int32_t res_32_SV_VL6__b_false = 3; + int32_t res_32_SV_VL7__b_false = 3; + int32_t res_32_SV_VL8__b_false = 3; + int32_t res_32_SV_VL16__b_false = 3; + uint32_t res_32_SV_VL1_u_b_false = 3; + uint32_t res_32_SV_VL2_u_b_false = 3; + uint32_t res_32_SV_VL3_u_b_false = 3; + uint32_t res_32_SV_VL4_u_b_false = 3; + uint32_t res_32_SV_VL5_u_b_false = 3; + uint32_t res_32_SV_VL6_u_b_false = 3; + uint32_t res_32_SV_VL7_u_b_false = 3; + uint32_t res_32_SV_VL8_u_b_false = 3; + uint32_t res_32_SV_VL16_u_b_false = 3; + int64_t res_64_SV_VL1__b_false = 1; + int64_t res_64_SV_VL2__b_false = 1; + int64_t res_64_SV_VL3__b_false = 1; + int64_t res_64_SV_VL4__b_false = 1; + int64_t res_64_SV_VL5__b_false = 1; + int64_t res_64_SV_VL6__b_false = 1; + int64_t res_64_SV_VL7__b_false = 1; + int64_t res_64_SV_VL8__b_false = 1; + int64_t res_64_SV_VL16__b_false = 1; + uint64_t res_64_SV_VL1_u_b_false = 1; + uint64_t res_64_SV_VL2_u_b_false = 1; + uint64_t res_64_SV_VL3_u_b_false = 1; + uint64_t res_64_SV_VL4_u_b_false = 1; + uint64_t res_64_SV_VL5_u_b_false = 1; + uint64_t res_64_SV_VL6_u_b_false = 1; + uint64_t res_64_SV_VL7_u_b_false = 1; + uint64_t res_64_SV_VL8_u_b_false = 1; + uint64_t res_64_SV_VL16_u_b_false = 1; + +#undef SVELAST_DEF +#define SVELAST_DEF(size, pat, sign, ab, su) \ + if (NAME (foo, size, pat, sign, ab) \ + (svindex_ ## su ## size (0, 1)) != \ + NAME (res, size, pat, sign, ab)) \ + __builtin_abort (); \ + if (NAMEF (foo, size, pat, sign, ab) \ + (svindex_ ## su ## size (0, 1)) != \ + NAMEF (res, size, pat, sign, ab)) \ + __builtin_abort (); + + ALL_POS () + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/svlast256_run.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/svlast256_run.c new file mode 100644 index 00000000000..f6ba7ea7d89 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/svlast256_run.c @@ -0,0 +1,314 @@ +/* { dg-do run { target aarch64_sve256_hw } } */ +/* { dg-options "-O3 -msve-vector-bits=256 -std=gnu99" } */ + +#include "svlast.c" + +int +main (void) +{ + int8_t res_8_SV_VL1__a = 1; + int8_t res_8_SV_VL2__a = 2; + int8_t res_8_SV_VL3__a = 3; + int8_t res_8_SV_VL4__a = 4; + int8_t res_8_SV_VL5__a = 5; + int8_t res_8_SV_VL6__a = 6; + int8_t res_8_SV_VL7__a = 7; + int8_t res_8_SV_VL8__a = 8; + int8_t res_8_SV_VL16__a = 16; + uint8_t res_8_SV_VL1_u_a = 1; + uint8_t res_8_SV_VL2_u_a = 2; + uint8_t res_8_SV_VL3_u_a = 3; + uint8_t res_8_SV_VL4_u_a = 4; + uint8_t res_8_SV_VL5_u_a = 5; + uint8_t res_8_SV_VL6_u_a = 6; + uint8_t res_8_SV_VL7_u_a = 7; + uint8_t res_8_SV_VL8_u_a = 8; + uint8_t res_8_SV_VL16_u_a = 16; + int16_t res_16_SV_VL1__a = 1; + int16_t res_16_SV_VL2__a = 2; + int16_t res_16_SV_VL3__a = 3; + int16_t res_16_SV_VL4__a = 4; + int16_t res_16_SV_VL5__a = 5; + int16_t res_16_SV_VL6__a = 6; + int16_t res_16_SV_VL7__a = 7; + int16_t res_16_SV_VL8__a = 8; + int16_t res_16_SV_VL16__a = 0; + uint16_t res_16_SV_VL1_u_a = 1; + uint16_t res_16_SV_VL2_u_a = 2; + uint16_t res_16_SV_VL3_u_a = 3; + uint16_t res_16_SV_VL4_u_a = 4; + uint16_t res_16_SV_VL5_u_a = 5; + uint16_t res_16_SV_VL6_u_a = 6; + uint16_t res_16_SV_VL7_u_a = 7; + uint16_t res_16_SV_VL8_u_a = 8; + uint16_t res_16_SV_VL16_u_a = 0; + int32_t res_32_SV_VL1__a = 1; + int32_t res_32_SV_VL2__a = 2; + int32_t res_32_SV_VL3__a = 3; + int32_t res_32_SV_VL4__a = 4; + int32_t res_32_SV_VL5__a = 5; + int32_t res_32_SV_VL6__a = 6; + int32_t res_32_SV_VL7__a = 7; + int32_t res_32_SV_VL8__a = 0; + int32_t res_32_SV_VL16__a = 0; + uint32_t res_32_SV_VL1_u_a = 1; + uint32_t res_32_SV_VL2_u_a = 2; + uint32_t res_32_SV_VL3_u_a = 3; + uint32_t res_32_SV_VL4_u_a = 4; + uint32_t res_32_SV_VL5_u_a = 5; + uint32_t res_32_SV_VL6_u_a = 6; + uint32_t res_32_SV_VL7_u_a = 7; + uint32_t res_32_SV_VL8_u_a = 0; + uint32_t res_32_SV_VL16_u_a = 0; + int64_t res_64_SV_VL1__a = 1; + int64_t res_64_SV_VL2__a = 2; + int64_t res_64_SV_VL3__a = 3; + int64_t res_64_SV_VL4__a = 0; + int64_t res_64_SV_VL5__a = 0; + int64_t res_64_SV_VL6__a = 0; + int64_t res_64_SV_VL7__a = 0; + int64_t res_64_SV_VL8__a = 0; + int64_t res_64_SV_VL16__a = 0; + uint64_t res_64_SV_VL1_u_a = 1; + uint64_t res_64_SV_VL2_u_a = 2; + uint64_t res_64_SV_VL3_u_a = 3; + uint64_t res_64_SV_VL4_u_a = 0; + uint64_t res_64_SV_VL5_u_a = 0; + uint64_t res_64_SV_VL6_u_a = 0; + uint64_t res_64_SV_VL7_u_a = 0; + uint64_t res_64_SV_VL8_u_a = 0; + uint64_t res_64_SV_VL16_u_a = 0; + int8_t res_8_SV_VL1__b = 0; + int8_t res_8_SV_VL2__b = 1; + int8_t res_8_SV_VL3__b = 2; + int8_t res_8_SV_VL4__b = 3; + int8_t res_8_SV_VL5__b = 4; + int8_t res_8_SV_VL6__b = 5; + int8_t res_8_SV_VL7__b = 6; + int8_t res_8_SV_VL8__b = 7; + int8_t res_8_SV_VL16__b = 15; + uint8_t res_8_SV_VL1_u_b = 0; + uint8_t res_8_SV_VL2_u_b = 1; + uint8_t res_8_SV_VL3_u_b = 2; + uint8_t res_8_SV_VL4_u_b = 3; + uint8_t res_8_SV_VL5_u_b = 4; + uint8_t res_8_SV_VL6_u_b = 5; + uint8_t res_8_SV_VL7_u_b = 6; + uint8_t res_8_SV_VL8_u_b = 7; + uint8_t res_8_SV_VL16_u_b = 15; + int16_t res_16_SV_VL1__b = 0; + int16_t res_16_SV_VL2__b = 1; + int16_t res_16_SV_VL3__b = 2; + int16_t res_16_SV_VL4__b = 3; + int16_t res_16_SV_VL5__b = 4; + int16_t res_16_SV_VL6__b = 5; + int16_t res_16_SV_VL7__b = 6; + int16_t res_16_SV_VL8__b = 7; + int16_t res_16_SV_VL16__b = 15; + uint16_t res_16_SV_VL1_u_b = 0; + uint16_t res_16_SV_VL2_u_b = 1; + uint16_t res_16_SV_VL3_u_b = 2; + uint16_t res_16_SV_VL4_u_b = 3; + uint16_t res_16_SV_VL5_u_b = 4; + uint16_t res_16_SV_VL6_u_b = 5; + uint16_t res_16_SV_VL7_u_b = 6; + uint16_t res_16_SV_VL8_u_b = 7; + uint16_t res_16_SV_VL16_u_b = 15; + int32_t res_32_SV_VL1__b = 0; + int32_t res_32_SV_VL2__b = 1; + int32_t res_32_SV_VL3__b = 2; + int32_t res_32_SV_VL4__b = 3; + int32_t res_32_SV_VL5__b = 4; + int32_t res_32_SV_VL6__b = 5; + int32_t res_32_SV_VL7__b = 6; + int32_t res_32_SV_VL8__b = 7; + int32_t res_32_SV_VL16__b = 7; + uint32_t res_32_SV_VL1_u_b = 0; + uint32_t res_32_SV_VL2_u_b = 1; + uint32_t res_32_SV_VL3_u_b = 2; + uint32_t res_32_SV_VL4_u_b = 3; + uint32_t res_32_SV_VL5_u_b = 4; + uint32_t res_32_SV_VL6_u_b = 5; + uint32_t res_32_SV_VL7_u_b = 6; + uint32_t res_32_SV_VL8_u_b = 7; + uint32_t res_32_SV_VL16_u_b = 7; + int64_t res_64_SV_VL1__b = 0; + int64_t res_64_SV_VL2__b = 1; + int64_t res_64_SV_VL3__b = 2; + int64_t res_64_SV_VL4__b = 3; + int64_t res_64_SV_VL5__b = 3; + int64_t res_64_SV_VL6__b = 3; + int64_t res_64_SV_VL7__b = 3; + int64_t res_64_SV_VL8__b = 3; + int64_t res_64_SV_VL16__b = 3; + uint64_t res_64_SV_VL1_u_b = 0; + uint64_t res_64_SV_VL2_u_b = 1; + uint64_t res_64_SV_VL3_u_b = 2; + uint64_t res_64_SV_VL4_u_b = 3; + uint64_t res_64_SV_VL5_u_b = 3; + uint64_t res_64_SV_VL6_u_b = 3; + uint64_t res_64_SV_VL7_u_b = 3; + uint64_t res_64_SV_VL8_u_b = 3; + uint64_t res_64_SV_VL16_u_b = 3; + + int8_t res_8_SV_VL1__a_false = 0; + int8_t res_8_SV_VL2__a_false = 0; + int8_t res_8_SV_VL3__a_false = 0; + int8_t res_8_SV_VL4__a_false = 0; + int8_t res_8_SV_VL5__a_false = 0; + int8_t res_8_SV_VL6__a_false = 0; + int8_t res_8_SV_VL7__a_false = 0; + int8_t res_8_SV_VL8__a_false = 0; + int8_t res_8_SV_VL16__a_false = 0; + uint8_t res_8_SV_VL1_u_a_false = 0; + uint8_t res_8_SV_VL2_u_a_false = 0; + uint8_t res_8_SV_VL3_u_a_false = 0; + uint8_t res_8_SV_VL4_u_a_false = 0; + uint8_t res_8_SV_VL5_u_a_false = 0; + uint8_t res_8_SV_VL6_u_a_false = 0; + uint8_t res_8_SV_VL7_u_a_false = 0; + uint8_t res_8_SV_VL8_u_a_false = 0; + uint8_t res_8_SV_VL16_u_a_false = 0; + int16_t res_16_SV_VL1__a_false = 0; + int16_t res_16_SV_VL2__a_false = 0; + int16_t res_16_SV_VL3__a_false = 0; + int16_t res_16_SV_VL4__a_false = 0; + int16_t res_16_SV_VL5__a_false = 0; + int16_t res_16_SV_VL6__a_false = 0; + int16_t res_16_SV_VL7__a_false = 0; + int16_t res_16_SV_VL8__a_false = 0; + int16_t res_16_SV_VL16__a_false = 0; + uint16_t res_16_SV_VL1_u_a_false = 0; + uint16_t res_16_SV_VL2_u_a_false = 0; + uint16_t res_16_SV_VL3_u_a_false = 0; + uint16_t res_16_SV_VL4_u_a_false = 0; + uint16_t res_16_SV_VL5_u_a_false = 0; + uint16_t res_16_SV_VL6_u_a_false = 0; + uint16_t res_16_SV_VL7_u_a_false = 0; + uint16_t res_16_SV_VL8_u_a_false = 0; + uint16_t res_16_SV_VL16_u_a_false = 0; + int32_t res_32_SV_VL1__a_false = 0; + int32_t res_32_SV_VL2__a_false = 0; + int32_t res_32_SV_VL3__a_false = 0; + int32_t res_32_SV_VL4__a_false = 0; + int32_t res_32_SV_VL5__a_false = 0; + int32_t res_32_SV_VL6__a_false = 0; + int32_t res_32_SV_VL7__a_false = 0; + int32_t res_32_SV_VL8__a_false = 0; + int32_t res_32_SV_VL16__a_false = 0; + uint32_t res_32_SV_VL1_u_a_false = 0; + uint32_t res_32_SV_VL2_u_a_false = 0; + uint32_t res_32_SV_VL3_u_a_false = 0; + uint32_t res_32_SV_VL4_u_a_false = 0; + uint32_t res_32_SV_VL5_u_a_false = 0; + uint32_t res_32_SV_VL6_u_a_false = 0; + uint32_t res_32_SV_VL7_u_a_false = 0; + uint32_t res_32_SV_VL8_u_a_false = 0; + uint32_t res_32_SV_VL16_u_a_false = 0; + int64_t res_64_SV_VL1__a_false = 0; + int64_t res_64_SV_VL2__a_false = 0; + int64_t res_64_SV_VL3__a_false = 0; + int64_t res_64_SV_VL4__a_false = 0; + int64_t res_64_SV_VL5__a_false = 0; + int64_t res_64_SV_VL6__a_false = 0; + int64_t res_64_SV_VL7__a_false = 0; + int64_t res_64_SV_VL8__a_false = 0; + int64_t res_64_SV_VL16__a_false = 0; + uint64_t res_64_SV_VL1_u_a_false = 0; + uint64_t res_64_SV_VL2_u_a_false = 0; + uint64_t res_64_SV_VL3_u_a_false = 0; + uint64_t res_64_SV_VL4_u_a_false = 0; + uint64_t res_64_SV_VL5_u_a_false = 0; + uint64_t res_64_SV_VL6_u_a_false = 0; + uint64_t res_64_SV_VL7_u_a_false = 0; + uint64_t res_64_SV_VL8_u_a_false = 0; + uint64_t res_64_SV_VL16_u_a_false = 0; + int8_t res_8_SV_VL1__b_false = 31; + int8_t res_8_SV_VL2__b_false = 31; + int8_t res_8_SV_VL3__b_false = 31; + int8_t res_8_SV_VL4__b_false = 31; + int8_t res_8_SV_VL5__b_false = 31; + int8_t res_8_SV_VL6__b_false = 31; + int8_t res_8_SV_VL7__b_false = 31; + int8_t res_8_SV_VL8__b_false = 31; + int8_t res_8_SV_VL16__b_false = 31; + uint8_t res_8_SV_VL1_u_b_false = 31; + uint8_t res_8_SV_VL2_u_b_false = 31; + uint8_t res_8_SV_VL3_u_b_false = 31; + uint8_t res_8_SV_VL4_u_b_false = 31; + uint8_t res_8_SV_VL5_u_b_false = 31; + uint8_t res_8_SV_VL6_u_b_false = 31; + uint8_t res_8_SV_VL7_u_b_false = 31; + uint8_t res_8_SV_VL8_u_b_false = 31; + uint8_t res_8_SV_VL16_u_b_false = 31; + int16_t res_16_SV_VL1__b_false = 15; + int16_t res_16_SV_VL2__b_false = 15; + int16_t res_16_SV_VL3__b_false = 15; + int16_t res_16_SV_VL4__b_false = 15; + int16_t res_16_SV_VL5__b_false = 15; + int16_t res_16_SV_VL6__b_false = 15; + int16_t res_16_SV_VL7__b_false = 15; + int16_t res_16_SV_VL8__b_false = 15; + int16_t res_16_SV_VL16__b_false = 15; + uint16_t res_16_SV_VL1_u_b_false = 15; + uint16_t res_16_SV_VL2_u_b_false = 15; + uint16_t res_16_SV_VL3_u_b_false = 15; + uint16_t res_16_SV_VL4_u_b_false = 15; + uint16_t res_16_SV_VL5_u_b_false = 15; + uint16_t res_16_SV_VL6_u_b_false = 15; + uint16_t res_16_SV_VL7_u_b_false = 15; + uint16_t res_16_SV_VL8_u_b_false = 15; + uint16_t res_16_SV_VL16_u_b_false = 15; + int32_t res_32_SV_VL1__b_false = 7; + int32_t res_32_SV_VL2__b_false = 7; + int32_t res_32_SV_VL3__b_false = 7; + int32_t res_32_SV_VL4__b_false = 7; + int32_t res_32_SV_VL5__b_false = 7; + int32_t res_32_SV_VL6__b_false = 7; + int32_t res_32_SV_VL7__b_false = 7; + int32_t res_32_SV_VL8__b_false = 7; + int32_t res_32_SV_VL16__b_false = 7; + uint32_t res_32_SV_VL1_u_b_false = 7; + uint32_t res_32_SV_VL2_u_b_false = 7; + uint32_t res_32_SV_VL3_u_b_false = 7; + uint32_t res_32_SV_VL4_u_b_false = 7; + uint32_t res_32_SV_VL5_u_b_false = 7; + uint32_t res_32_SV_VL6_u_b_false = 7; + uint32_t res_32_SV_VL7_u_b_false = 7; + uint32_t res_32_SV_VL8_u_b_false = 7; + uint32_t res_32_SV_VL16_u_b_false = 7; + int64_t res_64_SV_VL1__b_false = 3; + int64_t res_64_SV_VL2__b_false = 3; + int64_t res_64_SV_VL3__b_false = 3; + int64_t res_64_SV_VL4__b_false = 3; + int64_t res_64_SV_VL5__b_false = 3; + int64_t res_64_SV_VL6__b_false = 3; + int64_t res_64_SV_VL7__b_false = 3; + int64_t res_64_SV_VL8__b_false = 3; + int64_t res_64_SV_VL16__b_false = 3; + uint64_t res_64_SV_VL1_u_b_false = 3; + uint64_t res_64_SV_VL2_u_b_false = 3; + uint64_t res_64_SV_VL3_u_b_false = 3; + uint64_t res_64_SV_VL4_u_b_false = 3; + uint64_t res_64_SV_VL5_u_b_false = 3; + uint64_t res_64_SV_VL6_u_b_false = 3; + uint64_t res_64_SV_VL7_u_b_false = 3; + uint64_t res_64_SV_VL8_u_b_false = 3; + uint64_t res_64_SV_VL16_u_b_false = 3; + + +#undef SVELAST_DEF +#define SVELAST_DEF(size, pat, sign, ab, su) \ + if (NAME (foo, size, pat, sign, ab) \ + (svindex_ ## su ## size (0 ,1)) != \ + NAME (res, size, pat, sign, ab)) \ + __builtin_abort (); \ + if (NAMEF (foo, size, pat, sign, ab) \ + (svindex_ ## su ## size (0 ,1)) != \ + NAMEF (res, size, pat, sign, ab)) \ + __builtin_abort (); + + ALL_POS () + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4.c index 1e38371842f..91fdd3c202e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4.c @@ -186,8 +186,6 @@ CALLER (f16, __SVFloat16_t) ** caller_bf16: ** ... ** bl callee_bf16 -** ptrue (p[0-7])\.b, all -** lasta h0, \1, z0\.h ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_1024.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_1024.c index 491c35af221..7d824caae1b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_1024.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_1024.c @@ -186,8 +186,6 @@ CALLER (f16, __SVFloat16_t) ** caller_bf16: ** ... ** bl callee_bf16 -** ptrue (p[0-7])\.b, vl128 -** lasta h0, \1, z0\.h ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_128.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_128.c index eebb913273a..e0aa3a5fa68 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_128.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_128.c @@ -186,8 +186,6 @@ CALLER (f16, __SVFloat16_t) ** caller_bf16: ** ... ** bl callee_bf16 -** ptrue (p[0-7])\.b, vl16 -** lasta h0, \1, z0\.h ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_2048.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_2048.c index 73c3b2ec045..3238015d9eb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_2048.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_2048.c @@ -186,8 +186,6 @@ CALLER (f16, __SVFloat16_t) ** caller_bf16: ** ... ** bl callee_bf16 -** ptrue (p[0-7])\.b, vl256 -** lasta h0, \1, z0\.h ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_256.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_256.c index 29744c81402..50861098934 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_256.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_256.c @@ -186,8 +186,6 @@ CALLER (f16, __SVFloat16_t) ** caller_bf16: ** ... ** bl callee_bf16 -** ptrue (p[0-7])\.b, vl32 -** lasta h0, \1, z0\.h ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_512.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_512.c index cf25c31bcbf..300dacce955 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_512.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_512.c @@ -186,8 +186,6 @@ CALLER (f16, __SVFloat16_t) ** caller_bf16: ** ... ** bl callee_bf16 -** ptrue (p[0-7])\.b, vl64 -** lasta h0, \1, z0\.h ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5.c index 9ad3e227654..0a840a38384 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5.c @@ -186,8 +186,6 @@ CALLER (f16, svfloat16_t) ** caller_bf16: ** ... ** bl callee_bf16 -** ptrue (p[0-7])\.b, all -** lasta h0, \1, z0\.h ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_1024.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_1024.c index d573e5fc69c..18cefbff1e6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_1024.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_1024.c @@ -186,8 +186,6 @@ CALLER (f16, svfloat16_t) ** caller_bf16: ** ... ** bl callee_bf16 -** ptrue (p[0-7])\.b, vl128 -** lasta h0, \1, z0\.h ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_128.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_128.c index 200b0eb8242..c622ed55674 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_128.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_128.c @@ -186,8 +186,6 @@ CALLER (f16, svfloat16_t) ** caller_bf16: ** ... ** bl callee_bf16 -** ptrue (p[0-7])\.b, vl16 -** lasta h0, \1, z0\.h ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_2048.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_2048.c index f6f8858fd47..3286280687d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_2048.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_2048.c @@ -186,8 +186,6 @@ CALLER (f16, svfloat16_t) ** caller_bf16: ** ... ** bl callee_bf16 -** ptrue (p[0-7])\.b, vl256 -** lasta h0, \1, z0\.h ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_256.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_256.c index e62f59cc885..3c6afa2fdf1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_256.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_256.c @@ -186,8 +186,6 @@ CALLER (f16, svfloat16_t) ** caller_bf16: ** ... ** bl callee_bf16 -** ptrue (p[0-7])\.b, vl32 -** lasta h0, \1, z0\.h ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_512.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_512.c index 483558cb576..bb7d3ebf9d4 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_512.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_512.c @@ -186,8 +186,6 @@ CALLER (f16, svfloat16_t) ** caller_bf16: ** ... ** bl callee_bf16 -** ptrue (p[0-7])\.b, vl64 -** lasta h0, \1, z0\.h ** ldp x29, x30, \[sp\], 16 ** ret */