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Tue, 24 Jan 2023 10:43:39 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=rogerq@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id E1012B81106; Tue, 24 Jan 2023 09:43:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CD377C4339C; Tue, 24 Jan 2023 09:43:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1674553417; bh=5E7BingTPgsKogAWZyt00lz1B3dUbAI5UgdfwQcxpSs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=q3Mlcf97Qs+qjfTL+Ht46jdiu02ojBH/S5+SA+S/iukzR9Rz8Vcr/mrlQmEGxoI1a qtYTppTuu8hI7RgLThkAIzMjyphvwufmZil/32SivObrwROLJyNQYMc5HkNWPuXILe T6DgWjmiJw+hWLg2fSAu0R9a3jP9TyadSIg3s3i3MZOaSXIDV231ocIfIuMlgXmnwA hPRc5PjvrCIFX5iSqBFzeGBd4zuCgBZPkizzF4atPiTO43QBJGOevw+GI3MzLMyXYl 0eydb9HzqimF+t6QucJ6T9niNeoSNkwhzhrrdMQ84U3bUu/oasjclhQPMJqPhf/tBC XJ4dn7nWUqkUg== From: Roger Quadros To: trini@konsulko.com Cc: vigneshr@ti.com, nm@ti.com, praneeth@ti.com, u-boot@lists.denx.de, Roger Quadros Subject: [u-boot PATCH v2 1/3] arm: dts: k3-am64: sync with Linux DT files Date: Tue, 24 Jan 2023 11:43:25 +0200 Message-Id: <20230124094327.46394-2-rogerq@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124094327.46394-1-rogerq@kernel.org> References: <20230124094327.46394-1-rogerq@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Sync AM64 DT files with Linux v6.2-rc4 Signed-off-by: Roger Quadros Reviewed-by: Tom Rini --- arch/arm/dts/k3-am64-main.dtsi | 551 +++++++++++++++++++++++++++++++-- arch/arm/dts/k3-am64-mcu.dtsi | 16 +- arch/arm/dts/k3-am64.dtsi | 4 + arch/arm/dts/k3-am642-evm.dts | 117 ++++--- arch/arm/dts/k3-am642-sk.dts | 225 ++++++++++---- arch/arm/dts/k3-am642.dtsi | 2 +- 6 files changed, 787 insertions(+), 128 deletions(-) diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi index 57b0f53ac96..5e8036f32d7 100644 --- a/arch/arm/dts/k3-am64-main.dtsi +++ b/arch/arm/dts/k3-am64-main.dtsi @@ -59,7 +59,10 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01840000 0x00 0xC0000>; /* GICR */ + <0x00 0x01840000 0x00 0xC0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ /* * vcpumntirq: * virtual CPU interface maintenance interrupt @@ -171,7 +174,7 @@ compatible = "ti,k2g-sci"; ti,host-id = <12>; mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_main 12>, + mboxes = <&secure_proxy_main 12>, <&secure_proxy_main 13>; reg-names = "debug_messages"; reg = <0x00 0x44043000 0x00 0xfe0>; @@ -217,6 +220,12 @@ reg = <0x4044 0x8>; #phy-cells = <1>; }; + + epwm_tbclk: clock@4140 { + compatible = "ti,am64-epwm-tbclk", "syscon"; + reg = <0x4130 0x4>; + #clock-cells = <1>; + }; }; main_uart0: serial@2800000 { @@ -228,6 +237,7 @@ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -239,6 +249,7 @@ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 152 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -250,6 +261,7 @@ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 153 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart3: serial@2830000 { @@ -261,6 +273,7 @@ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 154 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart4: serial@2840000 { @@ -272,6 +285,7 @@ power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 155 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart5: serial@2850000 { @@ -283,6 +297,7 @@ power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 156 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart6: serial@2860000 { @@ -294,6 +309,7 @@ power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 158 0>; clock-names = "fclk"; + status = "disabled"; }; main_i2c0: i2c@20000000 { @@ -305,6 +321,7 @@ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 102 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c1: i2c@20010000 { @@ -316,6 +333,7 @@ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 103 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c2: i2c@20020000 { @@ -327,6 +345,7 @@ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 104 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c3: i2c@20030000 { @@ -338,6 +357,7 @@ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 2>; clock-names = "fck"; + status = "disabled"; }; main_spi0: spi@20100000 { @@ -350,6 +370,7 @@ clocks = <&k3_clks 141 0>; dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; dma-names = "tx0", "rx0"; + status = "disabled"; }; main_spi1: spi@20110000 { @@ -360,6 +381,7 @@ #size-cells = <0>; power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 142 0>; + status = "disabled"; }; main_spi2: spi@20120000 { @@ -370,6 +392,7 @@ #size-cells = <0>; power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 143 0>; + status = "disabled"; }; main_spi3: spi@20130000 { @@ -380,6 +403,7 @@ #size-cells = <0>; power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 144 0>; + status = "disabled"; }; main_spi4: spi@20140000 { @@ -390,6 +414,7 @@ #size-cells = <0>; power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 145 0>; + status = "disabled"; }; main_gpio_intr: interrupt-controller@a00000 { @@ -447,13 +472,11 @@ clock-names = "clk_ahb", "clk_xin"; mmc-ddr-1_8v; mmc-hs200-1_8v; - mmc-hs400-1_8v; ti,trm-icp = <0x2>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x6>; ti,otap-del-sel-hs200 = <0x7>; - ti,otap-del-sel-hs400 = <0x4>; }; sdhci1: mmc@fa00000 { @@ -529,6 +552,7 @@ clocks = <&k3_clks 13 0>; clock-names = "fck"; bus_freq = <1000000>; + status = "disabled"; }; cpts@3d000 { @@ -543,7 +567,7 @@ }; }; - cpts@39000000 { + main_cpts0: cpts@39000000 { compatible = "ti,j721e-cpts"; reg = <0x0 0x39000000 0x0 0x400>; reg-names = "cpts"; @@ -558,6 +582,14 @@ ti,cpts-ext-ts-inputs = <8>; }; + timesync_router: pinctrl@a40000 { + compatible = "pinctrl-single"; + reg = <0x0 0xa40000 0x0 0x800>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x000107ff>; + }; + usbss0: cdns-usb@f900000{ compatible = "ti,am64-usb"; reg = <0x00 0xf900000 0x00 0x100>; @@ -597,7 +629,7 @@ assigned-clocks = <&k3_clks 0 0>; assigned-clock-parents = <&k3_clks 0 3>; assigned-clock-rates = <60000000>; - clock-names = "adc_tsc_fck"; + clock-names = "fck"; adc { #io-channel-cells = <1>; @@ -840,6 +872,7 @@ ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; + status = "disabled"; }; pcie0_ep: pcie-ep@f102000 { @@ -858,23 +891,505 @@ clocks = <&k3_clks 114 0>; clock-names = "fck"; max-functions = /bits/ 8 <1>; + status = "disabled"; + }; + + epwm0: pwm@23000000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23000000 0x0 0x100>; + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm1: pwm@23010000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23010000 0x0 0x100>; + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm2: pwm@23020000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23020000 0x0 0x100>; + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm3: pwm@23030000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23030000 0x0 0x100>; + power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm4: pwm@23040000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23040000 0x0 0x100>; + power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm5: pwm@23050000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23050000 0x0 0x100>; + power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm6: pwm@23060000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23060000 0x0 0x100>; + power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm7: pwm@23070000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23070000 0x0 0x100>; + power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm8: pwm@23080000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23080000 0x0 0x100>; + power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + ecap0: pwm@23100000 { + compatible = "ti,am64-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x0 0x23100000 0x0 0x60>; + power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 51 0>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap1: pwm@23110000 { + compatible = "ti,am64-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x0 0x23110000 0x0 0x60>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 52 0>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap2: pwm@23120000 { + compatible = "ti,am64-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x0 0x23120000 0x0 0x60>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 53 0>; + clock-names = "fck"; + status = "disabled"; }; main_rti0: watchdog@e000000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0xe000000 0x00 0x100>; - clocks = <&k3_clks 125 0>; - power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 125 0>; - assigned-clock-parents = <&k3_clks 125 2>; + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0xe000000 0x00 0x100>; + clocks = <&k3_clks 125 0>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 125 0>; + assigned-clock-parents = <&k3_clks 125 2>; }; main_rti1: watchdog@e010000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0xe010000 0x00 0x100>; - clocks = <&k3_clks 126 0>; - power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 126 0>; - assigned-clock-parents = <&k3_clks 126 2>; + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0xe010000 0x00 0x100>; + clocks = <&k3_clks 126 0>; + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 126 0>; + assigned-clock-parents = <&k3_clks 126 2>; + }; + + icssg0: icssg@30000000 { + compatible = "ti,am642-icssg"; + reg = <0x00 0x30000000 0x00 0x80000>; + power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x30000000 0x80000>; + + icssg0_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x10000>; + reg-names = "dram0", "dram1", "shrdram2"; + }; + + icssg0_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x200>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + icssg0_coreclk_mux: coreclk-mux@3c { + reg = <0x3c>; + #clock-cells = <0>; + clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ + <&k3_clks 81 20>; /* icssg0_iclk */ + assigned-clocks = <&icssg0_coreclk_mux>; + assigned-clock-parents = <&k3_clks 81 20>; + }; + + icssg0_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */ + <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */ + assigned-clocks = <&icssg0_iepclk_mux>; + assigned-clock-parents = <&icssg0_coreclk_mux>; + }; + }; + }; + + icssg0_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x100>; + }; + + icssg0_mii_g_rt: mii-g-rt@33000 { + compatible = "ti,pruss-mii-g", "syscon"; + reg = <0x33000 0x1000>; + }; + + icssg0_intc: interrupt-controller@20000 { + compatible = "ti,icssg-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + }; + + pru0_0: pru@34000 { + compatible = "ti,am642-pru"; + reg = <0x34000 0x3000>, + <0x22000 0x100>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am64x-pru0_0-fw"; + }; + + rtu0_0: rtu@4000 { + compatible = "ti,am642-rtu"; + reg = <0x4000 0x2000>, + <0x23000 0x100>, + <0x23400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am64x-rtu0_0-fw"; + }; + + tx_pru0_0: txpru@a000 { + compatible = "ti,am642-tx-pru"; + reg = <0xa000 0x1800>, + <0x25000 0x100>, + <0x25400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am64x-txpru0_0-fw"; + }; + + pru0_1: pru@38000 { + compatible = "ti,am642-pru"; + reg = <0x38000 0x3000>, + <0x24000 0x100>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am64x-pru0_1-fw"; + }; + + rtu0_1: rtu@6000 { + compatible = "ti,am642-rtu"; + reg = <0x6000 0x2000>, + <0x23800 0x100>, + <0x23c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am64x-rtu0_1-fw"; + }; + + tx_pru0_1: txpru@c000 { + compatible = "ti,am642-tx-pru"; + reg = <0xc000 0x1800>, + <0x25800 0x100>, + <0x25c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am64x-txpru0_1-fw"; + }; + + icssg0_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 62 3>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + status = "disabled"; + }; + }; + + icssg1: icssg@30080000 { + compatible = "ti,am642-icssg"; + reg = <0x00 0x30080000 0x00 0x80000>; + power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x30080000 0x80000>; + + icssg1_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x10000>; + reg-names = "dram0", "dram1", "shrdram2"; + }; + + icssg1_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x200>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + icssg1_coreclk_mux: coreclk-mux@3c { + reg = <0x3c>; + #clock-cells = <0>; + clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ + <&k3_clks 82 20>; /* icssg1_iclk */ + assigned-clocks = <&icssg1_coreclk_mux>; + assigned-clock-parents = <&k3_clks 82 20>; + }; + + icssg1_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */ + <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */ + assigned-clocks = <&icssg1_iepclk_mux>; + assigned-clock-parents = <&icssg1_coreclk_mux>; + }; + }; + }; + + icssg1_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x100>; + }; + + icssg1_mii_g_rt: mii-g-rt@33000 { + compatible = "ti,pruss-mii-g", "syscon"; + reg = <0x33000 0x1000>; + }; + + icssg1_intc: interrupt-controller@20000 { + compatible = "ti,icssg-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + }; + + pru1_0: pru@34000 { + compatible = "ti,am642-pru"; + reg = <0x34000 0x4000>, + <0x22000 0x100>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am64x-pru1_0-fw"; + }; + + rtu1_0: rtu@4000 { + compatible = "ti,am642-rtu"; + reg = <0x4000 0x2000>, + <0x23000 0x100>, + <0x23400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am64x-rtu1_0-fw"; + }; + + tx_pru1_0: txpru@a000 { + compatible = "ti,am642-tx-pru"; + reg = <0xa000 0x1800>, + <0x25000 0x100>, + <0x25400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am64x-txpru1_0-fw"; + }; + + pru1_1: pru@38000 { + compatible = "ti,am642-pru"; + reg = <0x38000 0x4000>, + <0x24000 0x100>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am64x-pru1_1-fw"; + }; + + rtu1_1: rtu@6000 { + compatible = "ti,am642-rtu"; + reg = <0x6000 0x2000>, + <0x23800 0x100>, + <0x23c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am64x-rtu1_1-fw"; + }; + + tx_pru1_1: txpru@c000 { + compatible = "ti,am642-tx-pru"; + reg = <0xc000 0x1800>, + <0x25800 0x100>, + <0x25c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am64x-txpru1_1-fw"; + }; + + icssg1_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 82 0>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + }; + + main_mcan0: can@20701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 98 5>, <&k3_clks 98 0>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan1: can@20711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20711000 0x00 0x200>, + <0x00 0x20718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + crypto: crypto@40900000 { + compatible = "ti,am64-sa2ul"; + reg = <0x00 0x40900000 0x00 0x1200>; + power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; + dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>, + <&main_pktdma 0x4003 0>; + dma-names = "tx", "rx1", "rx2"; + + rng: rng@40910000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x00 0x40910000 0x00 0x7d>; + interrupts = ; + status = "disabled"; /* Used by OP-TEE */ + }; + }; + + gpmc0: memory-controller@3b000000 { + compatible = "ti,am64-gpmc"; + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 80 0>; + clock-names = "fck"; + reg = <0x00 0x3b000000 0x00 0x400>, + <0x00 0x50000000 0x00 0x8000000>; + reg-names = "cfg", "data"; + interrupts = ; + gpmc,num-cs = <3>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + elm0: ecc@25010000 { + compatible = "ti,am64-elm"; + reg = <0x00 0x25010000 0x00 0x2000>; + interrupts = ; + power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 54 0>; + clock-names = "fck"; + status = "disabled"; }; }; diff --git a/arch/arm/dts/k3-am64-mcu.dtsi b/arch/arm/dts/k3-am64-mcu.dtsi index 59cc58f7d0c..38ddf0b3b8a 100644 --- a/arch/arm/dts/k3-am64-mcu.dtsi +++ b/arch/arm/dts/k3-am64-mcu.dtsi @@ -10,22 +10,22 @@ compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; interrupts = ; - clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 0>; clock-names = "fclk"; + status = "disabled"; }; mcu_uart1: serial@4a10000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a10000 0x00 0x100>; interrupts = ; - clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 160 0>; clock-names = "fclk"; + status = "disabled"; }; mcu_i2c0: i2c@4900000 { @@ -37,6 +37,7 @@ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 106 2>; clock-names = "fck"; + status = "disabled"; }; mcu_i2c1: i2c@4910000 { @@ -48,6 +49,7 @@ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 107 2>; clock-names = "fck"; + status = "disabled"; }; mcu_spi0: spi@4b00000 { @@ -58,6 +60,7 @@ #size-cells = <0>; power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 147 0>; + status = "disabled"; }; mcu_spi1: spi@4b10000 { @@ -68,6 +71,7 @@ #size-cells = <0>; power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 148 0>; + status = "disabled"; }; mcu_gpio_intr: interrupt-controller@4210000 { @@ -97,4 +101,12 @@ clocks = <&k3_clks 79 0>; clock-names = "gpio"; }; + + mcu_pmx0: pinctrl@4084000 { + compatible = "pinctrl-single"; + reg = <0x00 0x4084000 0x00 0x84>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; }; diff --git a/arch/arm/dts/k3-am64.dtsi b/arch/arm/dts/k3-am64.dtsi index 053e7f42e99..c858725133a 100644 --- a/arch/arm/dts/k3-am64.dtsi +++ b/arch/arm/dts/k3-am64.dtsi @@ -30,6 +30,8 @@ serial8 = &main_uart6; ethernet0 = &cpsw_port1; ethernet1 = &cpsw_port2; + mmc0 = &sdhci0; + mmc1 = &sdhci1; }; chosen { }; @@ -80,6 +82,7 @@ <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */ <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA2_UL0 */ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */ @@ -88,6 +91,7 @@ <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */ <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts index 03071222118..39feea78a08 100644 --- a/arch/arm/dts/k3-am642-evm.dts +++ b/arch/arm/dts/k3-am642-evm.dts @@ -13,7 +13,7 @@ #include "k3-am642.dtsi" / { - compatible = "ti,am642-evm", "ti,am642"; + compatible = "ti,am642-evm", "ti,am642"; model = "Texas Instruments AM642 EVM"; chosen { @@ -184,6 +184,20 @@ }; }; }; + + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; + }; }; &main_pmx0 { @@ -288,9 +302,30 @@ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ >; }; + + main_ecap0_pins_default: main-ecap0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ + >; + }; + + main_mcan0_pins_default: main-mcan0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ + AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ + >; + }; + + main_mcan1_pins_default: main-mcan1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ + AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ + >; + }; }; &main_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; @@ -300,35 +335,8 @@ status = "reserved"; }; -&main_uart2 { - status = "disabled"; -}; - -&main_uart3 { - status = "disabled"; -}; - -&main_uart4 { - status = "disabled"; -}; - -&main_uart5 { - status = "disabled"; -}; - -&main_uart6 { - status = "disabled"; -}; - -&mcu_uart0 { - status = "disabled"; -}; - -&mcu_uart1 { - status = "disabled"; -}; - &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; @@ -371,23 +379,8 @@ status = "reserved"; }; -&mcu_i2c0 { - status = "disabled"; -}; - -&mcu_i2c1 { - status = "disabled"; -}; - -&mcu_spi0 { - status = "disabled"; -}; - -&mcu_spi1 { - status = "disabled"; -}; - &main_spi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; ti,pindir-d0-out-d1-in; @@ -432,8 +425,7 @@ &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&mdio1_pins_default - &rgmii1_pins_default + pinctrl-0 = <&rgmii1_pins_default &rgmii2_pins_default>; }; @@ -448,6 +440,10 @@ }; &cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_pins_default>; + cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; @@ -464,7 +460,7 @@ pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -475,8 +471,6 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; - #address-cells = <1>; - #size-cells = <1>; }; }; @@ -562,6 +556,7 @@ }; &pcie0_rc { + status = "okay"; reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; @@ -572,5 +567,25 @@ phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; num-lanes = <1>; - status = "disabled"; +}; + +&ecap0 { + status = "okay"; + /* PWM is available on Pin 1 of header J12 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap0_pins_default>; +}; + +&main_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&main_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan1_pins_default>; + phys = <&transceiver2>; }; diff --git a/arch/arm/dts/k3-am642-sk.dts b/arch/arm/dts/k3-am642-sk.dts index d3aa2901e6f..2e2d40da360 100644 --- a/arch/arm/dts/k3-am642-sk.dts +++ b/arch/arm/dts/k3-am642-sk.dts @@ -9,10 +9,11 @@ #include #include #include +#include #include "k3-am642.dtsi" / { - compatible = "ti,am642-sk", "ti,am642"; + compatible = "ti,am642-sk", "ti,am642"; model = "Texas Instruments AM642 SK"; chosen { @@ -125,6 +126,99 @@ vin-supply = <&vcc_3v3_sys>; gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; }; + + com8_ls_en: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "com8_ls_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + pinctrl-0 = <&main_com8_ls_en_pins_default>; + pinctrl-names = "default"; + gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>; + }; + + wlan_en: regulator-2 { + /* output of SN74AVC4T245RSVR */ + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + pinctrl-0 = <&main_wlan_en_pins_default>; + pinctrl-names = "default"; + vin-supply = <&com8_ls_en>; + gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>; + }; + + led-controller { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + gpios = <&exp2 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <3>; + gpios = <&exp2 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-3 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <4>; + gpios = <&exp2 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-4 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <5>; + gpios = <&exp2 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-5 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <6>; + gpios = <&exp2 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-6 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <7>; + gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-7 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <8>; + linux,default-trigger = "heartbeat"; + gpios = <&exp2 7 GPIO_ACTIVE_HIGH>; + }; + }; }; &main_pmx0 { @@ -141,6 +235,15 @@ >; }; + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ + AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ + AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ + AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ + >; + }; + main_usb0_pins_default: main-usb0-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ @@ -210,14 +313,35 @@ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ >; }; -}; -&mcu_uart0 { - status = "disabled"; + main_ecap0_pins_default: main-ecap0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ + >; + }; + main_wlan_en_pins_default: main-wlan-en-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */ + >; + }; + + main_com8_ls_en_pins_default: main-com8-ls-en-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */ + >; + }; + + main_wlan_pins_default: main-wlan-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ + >; + }; }; -&mcu_uart1 { - status = "disabled"; +&main_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; }; &main_uart1 { @@ -225,35 +349,8 @@ status = "reserved"; }; -&main_uart2 { - status = "disabled"; -}; - -&main_uart3 { - status = "disabled"; -}; - -&main_uart4 { - status = "disabled"; -}; - -&main_uart5 { - status = "disabled"; -}; - -&main_uart6 { - status = "disabled"; -}; - -&mcu_i2c0 { - status = "disabled"; -}; - -&mcu_i2c1 { - status = "disabled"; -}; - &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; @@ -268,18 +365,14 @@ "VPP_LDO_EN", "RPI_PS_3V3_En", "RPI_PS_5V0_En", "RPI_HAT_DETECT"; }; -}; - -&main_i2c3 { - status = "disabled"; -}; - -&mcu_spi0 { - status = "disabled"; -}; -&mcu_spi1 { - status = "disabled"; + exp2: gpio@60 { + compatible = "ti,tpic2810"; + reg = <0x60>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8"; + }; }; /* mcu_gpio0 is reserved for mcu firmware usage */ @@ -287,6 +380,26 @@ status = "reserved"; }; +&sdhci0 { + vmmc-supply = <&wlan_en>; + bus-width = <4>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + ti,driver-strength-ohm = <50>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + pinctrl-0 = <&main_wlan_pins_default>; + pinctrl-names = "default"; + interrupt-parent = <&main_gpio0>; + interrupts = <46 IRQ_TYPE_EDGE_FALLING>; + }; +}; + &sdhci1 { /* SD/MMC */ vmmc-supply = <&vdd_mmc1>; @@ -326,8 +439,7 @@ &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&mdio1_pins_default - &rgmii1_pins_default + pinctrl-0 = <&rgmii1_pins_default &rgmii2_pins_default>; }; @@ -342,6 +454,10 @@ }; &cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_pins_default>; + cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; @@ -363,7 +479,7 @@ pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -374,8 +490,6 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; - #address-cells = <1>; - #size-cells = <1>; }; }; @@ -446,10 +560,9 @@ <&main_r5fss1_core1_memory_region>; }; -&pcie0_rc { - status = "disabled"; -}; - -&pcie0_ep { - status = "disabled"; +&ecap0 { + status = "okay"; + /* PWM is available on Pin 1 of header J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap0_pins_default>; }; diff --git a/arch/arm/dts/k3-am642.dtsi b/arch/arm/dts/k3-am642.dtsi index e2b397c8840..8a76f4821b1 100644 --- a/arch/arm/dts/k3-am642.dtsi +++ b/arch/arm/dts/k3-am642.dtsi @@ -60,6 +60,6 @@ cache-level = <2>; cache-size = <0x40000>; cache-line-size = <64>; - cache-sets = <512>; + cache-sets = <256>; }; }; From patchwork Tue Jan 24 09:43:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 1731057 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Tue, 24 Jan 2023 09:43:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1CFCBC433EF; Tue, 24 Jan 2023 09:43:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1674553419; bh=I4Sz1hCtzLwXEISHV2xcmUlWFw8IpNkvFsVE2MdjJoI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B1o29SzpS+d+v76YJCsPQImEbTSetDk+AWHouxjxWv2EPMa/q4JBexMu3c7EXM7of Bu9ZQkde9C4+AnDtBAfnEAvb2i5SqHQ7W6p1o7MRHKQWXo5VsFvYcI6UrT1xaf1pbv aNryHWgy1B5JILPTEp8uvVQaIDcCN9oi6lbUf5KOK0k9HcSBeiUQsnaijvaL5Zs7NO JouljDA0xr/dnaWJ8OWXhubKYKY//aLdJJ8dbiJ4Ix98/Era98cesy5hy2jOZaaS6n oI/CCfxWG9E22iYXVLUpBIHrutPED7N4Q8Od3DPQG8Tgd0qujo2Cct6HLiwQ6Ed5X3 VB8BOF9h+XrlA== From: Roger Quadros To: trini@konsulko.com Cc: vigneshr@ti.com, nm@ti.com, praneeth@ti.com, u-boot@lists.denx.de, Roger Quadros Subject: [u-boot PATCH v2 2/3] arm: dts: k3-am6: Fix "EEPROM not available" error Date: Tue, 24 Jan 2023 11:43:26 +0200 Message-Id: <20230124094327.46394-3-rogerq@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124094327.46394-1-rogerq@kernel.org> References: <20230124094327.46394-1-rogerq@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean We need to enable i2c0 so u-boot can read from EEPROM. Signed-off-by: Roger Quadros Reviewed-by: Tom Rini --- arch/arm/dts/k3-am642-evm-u-boot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi index 055215cff8d..fa7750d634f 100644 --- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi @@ -44,6 +44,7 @@ }; &main_i2c0 { + status = "okay"; u-boot,dm-spl; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; From patchwork Tue Jan 24 09:43:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 1731058 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=Wcmrj1V/; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4P1MWZ1p8pz23hB for ; Tue, 24 Jan 2023 20:44:42 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 817A4855AF; Tue, 24 Jan 2023 10:44:28 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="Wcmrj1V/"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 41A0085616; Tue, 24 Jan 2023 10:43:56 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id AF72D855FC for ; Tue, 24 Jan 2023 10:43:43 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=rogerq@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 55AAF60ACE; Tue, 24 Jan 2023 09:43:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 33ED2C4339B; Tue, 24 Jan 2023 09:43:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1674553421; bh=gDDOcrwwCnMmtlvPA0qpsqJ1G8Tn28mk7qydXkThBx4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Wcmrj1V/gr7DTOzLDqyDZKdUWZwArau//sXdT2FZqNs1Y7ADb4GQ8sO20D3eR0tFj ZMOtAWksEwLexsYkVcBhtdi5yY3vCCq0zTJgy9KWDba6MfYBuKhz7vYXupYSxcRSfp roE74ceBWmbiLjND5KWKUmtSb6dxzXXTdmdkSR66c8PEiDYs8T5S400OxkgNC52eQm y6QbJKkEdmYX9bIRrPmTFEcAXDH0g6s/1uano5HIo2+OtK9dLjAar7X1vZE0Y6bVcz qJMHr47aTf2kvf7n2Y/8r+HbbZRFld3svEnuoCHhvmqGX5y7bGEP16qdlZESQsAGjE 7WFvoitlI7d4A== From: Roger Quadros To: trini@konsulko.com Cc: vigneshr@ti.com, nm@ti.com, praneeth@ti.com, u-boot@lists.denx.de, Roger Quadros Subject: [u-boot PATCH v2 3/3] arm: dts: k3-am64: Fix CPSW3G ethernet Date: Tue, 24 Jan 2023 11:43:27 +0200 Message-Id: <20230124094327.46394-4-rogerq@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124094327.46394-1-rogerq@kernel.org> References: <20230124094327.46394-1-rogerq@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean As MDIO driver does not support Driver Model, the pinctrl settings in the MDIO node will not be applied resulting in PHY not being detected. To workaround this we add the MDIO pinctrl in the CPSW3G node in the -u-boot.dtsi file. Add the missing MDIO and RGMII pinctrl nodes in k3-am642-r5-evm.dts Signed-off-by: Roger Quadros Reviewed-by: Tom Rini --- arch/arm/dts/k3-am642-evm-u-boot.dtsi | 3 ++ arch/arm/dts/k3-am642-r5-evm.dts | 41 +++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi index fa7750d634f..9b6c7e85cb4 100644 --- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi @@ -113,6 +113,9 @@ <0x0 0x43000200 0x0 0x8>; reg-names = "cpsw_nuss", "mac_efuse"; /delete-property/ ranges; + pinctrl-0 = <&mdio1_pins_default /* HACK: as MDIO driver is not DM enabled */ + &rgmii1_pins_default + &rgmii2_pins_default>; cpsw-phy-sel@04044 { compatible = "ti,am64-phy-gmii-sel"; diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts index 92a6bfdc011..7493362ac65 100644 --- a/arch/arm/dts/k3-am642-r5-evm.dts +++ b/arch/arm/dts/k3-am642-r5-evm.dts @@ -167,6 +167,47 @@ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ >; }; + + mdio1_pins_default: mdio1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ + AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ + >; + }; + + rgmii1_pins_default: rgmii1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ + AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ + AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ + AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ + AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ + AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ + AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ + AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ + AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ + AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ + AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ + AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ + >; + }; + + rgmii2_pins_default: rgmii2-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ + AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; }; &dmsc {