From patchwork Tue Mar 13 19:54:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 885446 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=cogentembedded.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=cogentembedded-com.20150623.gappssmtp.com header.i=@cogentembedded-com.20150623.gappssmtp.com header.b="K2m3PaCN"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4015D82gTZz9sTC for ; Wed, 14 Mar 2018 06:54:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751534AbeCMTyr (ORCPT ); Tue, 13 Mar 2018 15:54:47 -0400 Received: from mail-lf0-f68.google.com ([209.85.215.68]:40074 "EHLO mail-lf0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751714AbeCMTyq (ORCPT ); Tue, 13 Mar 2018 15:54:46 -0400 Received: by mail-lf0-f68.google.com with SMTP id u21-v6so1251906lfc.7 for ; Tue, 13 Mar 2018 12:54:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:subject:to:cc:references:organization:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=YRz/eWmBYyg4rCoMSNTIpcWcDQHs6Cefa+TWNILub/s=; b=K2m3PaCN68dku3B00z2JfHG2AeIeFi4B1H/RKfY6eU+od+On715Y/4BYeJfG91Bk5G siHeYD8fJgw4j3pd9my3zWZlAwB6vqccBwCRAQR5kq4eFX/f00Ojmm4W5ehZ6a8dYcGu lSdrzMG6wQN983x9Sb6f9ClQk6WD9dbnfwCdOflErqQBdnmFQlvyzSWVY/D+Lt2UewHA 0zeVE3Gf8/Lp44RNZGb0FAVm4KP3GsA+3eZa9JgZJhYLWleGaug6TRamZZvZxozc8sP3 Hmw0cuARFaBg5nRDjp6CM3hJ0mfrPxBj8XlA65rEYdOfJZuKHTrCoq2LokMhYowGjzTA +ffQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:subject:to:cc:references:organization :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=YRz/eWmBYyg4rCoMSNTIpcWcDQHs6Cefa+TWNILub/s=; b=FVQkppxI3ORUDmxBCXrNQmiXIdVR+cuX3pvJmuadJHb1dws8ioN6lEeeLrUs74+X4h TSjbGq43PHcwrb3Diuuo3PVA2lbUNNa90EBK5bQf5G551M85PGd+HeHDSPgy0mY5cylw 0CEeq3l/Z1NEIEKaUp+JaW9L8uAMxdj/n35tbDGH05i3hzyJx7wcqgxJnUJmZcJa/112 3l5M5QiDm5nXr/z/UqwSODEPlkMiz4DuXdC5LmFoWBma82dAfO0KG9y5PjKFKJcbsJLw NJY2ebx9BueRghtm6gxnmAvRHjaLAl+55wclLLC2XmqyBzF8q/jmLb3iEWUUYQjMz9VW lJaw== X-Gm-Message-State: AElRT7GbRT3jQeDjR+RflTsNbJGrmZHiOZIZZ+syPfZzTmIdcfPW0NZJ ywcXby+i+8ivrDicrm6lvoFUXg== X-Google-Smtp-Source: AG47ELupDzQ0eC1KyRJmbf7j91NvU0U3OqnYSvy1EUBxzYQFv8noRP/NcsOxJFIDT5CzM/gnNvvTrw== X-Received: by 10.46.66.83 with SMTP id p80mr1419122lja.3.1520970884851; Tue, 13 Mar 2018 12:54:44 -0700 (PDT) Received: from wasted.cogentembedded.com ([31.173.82.41]) by smtp.gmail.com with ESMTPSA id f9sm203053ljf.29.2018.03.13.12.54.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Mar 2018 12:54:43 -0700 (PDT) From: Sergei Shtylyov Subject: [PATCH] pinctrl: sh-pfc: r8a77970: add EtherAVB pin groups To: Linus Walleij , Geert Uytterhoeven , linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org Cc: Laurent Pinchart , Vladimir Barinov References: <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com> Organization: Cogent Embedded Message-ID: Date: Tue, 13 Mar 2018 22:54:42 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com> Content-Language: en-MW Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the EtherAVB pin groups to the R8A77970 PFC driver. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- The patch is against the 'sh-pfc' branch of Geert's 'renesas-drivers.git' repo. drivers/pinctrl/sh-pfc/pfc-r8a77970.c | 98 ++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c =================================================================== --- renesas-drivers.orig/drivers/pinctrl/sh-pfc/pfc-r8a77970.c +++ renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c @@ -728,6 +728,82 @@ static const struct sh_pfc_pin pinmux_pi PINMUX_GPIO_GP_ALL(), }; +/* - AVB0 ------------------------------------------------------------------- */ +static const unsigned int avb0_link_pins[] = { + /* AVB0_LINK */ + RCAR_GP_PIN(1, 18), +}; +static const unsigned int avb0_link_mux[] = { + AVB0_LINK_MARK, +}; +static const unsigned int avb0_magic_pins[] = { + /* AVB0_MAGIC */ + RCAR_GP_PIN(1, 16), +}; +static const unsigned int avb0_magic_mux[] = { + AVB0_MAGIC_MARK, +}; +static const unsigned int avb0_phy_int_pins[] = { + /* AVB0_PHY_INT */ + RCAR_GP_PIN(1, 17), +}; +static const unsigned int avb0_phy_int_mux[] = { + AVB0_PHY_INT_MARK, +}; +static const unsigned int avb0_mdio_pins[] = { + /* AVB0_MDC, AVB0_MDIO */ + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), +}; +static const unsigned int avb0_mdio_mux[] = { + AVB0_MDC_MARK, AVB0_MDIO_MARK, +}; +static const unsigned int avb0_rgmii_pins[] = { + /* + * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3, + * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3 + */ + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), +}; +static const unsigned int avb0_rgmii_mux[] = { + AVB0_TX_CTL_MARK, AVB0_TXC_MARK, + AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK, + AVB0_RX_CTL_MARK, AVB0_RXC_MARK, + AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK, +}; +static const unsigned int avb0_txcrefclk_pins[] = { + /* AVB0_TXCREFCLK */ + RCAR_GP_PIN(1, 13), +}; +static const unsigned int avb0_txcrefclk_mux[] = { + AVB0_TXCREFCLK_MARK, +}; +static const unsigned int avb0_avtp_pps_pins[] = { + /* AVB0_AVTP_PPS */ + RCAR_GP_PIN(2, 6), +}; +static const unsigned int avb0_avtp_pps_mux[] = { + AVB0_AVTP_PPS_MARK, +}; +static const unsigned int avb0_avtp_capture_pins[] = { + /* AVB0_AVTP_CAPTURE */ + RCAR_GP_PIN(1, 20), +}; +static const unsigned int avb0_avtp_capture_mux[] = { + AVB0_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb0_avtp_match_pins[] = { + /* AVB0_AVTP_MATCH */ + RCAR_GP_PIN(1, 19), +}; +static const unsigned int avb0_avtp_match_mux[] = { + AVB0_AVTP_MATCH_MARK, +}; + /* - CANFD Clock ------------------------------------------------------------ */ static const unsigned int canfd_clk_a_pins[] = { /* CANFD_CLK */ @@ -1599,6 +1675,15 @@ static const unsigned int vin1_clk_mux[] }; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(avb0_link), + SH_PFC_PIN_GROUP(avb0_magic), + SH_PFC_PIN_GROUP(avb0_phy_int), + SH_PFC_PIN_GROUP(avb0_mdio), + SH_PFC_PIN_GROUP(avb0_rgmii), + SH_PFC_PIN_GROUP(avb0_txcrefclk), + SH_PFC_PIN_GROUP(avb0_avtp_pps), + SH_PFC_PIN_GROUP(avb0_avtp_capture), + SH_PFC_PIN_GROUP(avb0_avtp_match), SH_PFC_PIN_GROUP(canfd_clk_a), SH_PFC_PIN_GROUP(canfd_clk_b), SH_PFC_PIN_GROUP(canfd0_data_a), @@ -1709,6 +1794,18 @@ static const struct sh_pfc_pin_group pin SH_PFC_PIN_GROUP(vin1_clk), }; +static const char * const avb0_groups[] = { + "avb0_link", + "avb0_magic", + "avb0_phy_int", + "avb0_mdio", + "avb0_rgmii", + "avb0_txcrefclk", + "avb0_avtp_pps", + "avb0_avtp_capture", + "avb0_avtp_match", +}; + static const char * const canfd_clk_groups[] = { "canfd_clk_a", "canfd_clk_b", @@ -1914,6 +2011,7 @@ static const char * const vin1_groups[] }; static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(avb0), SH_PFC_FUNCTION(canfd_clk), SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1),