From patchwork Wed Jan 4 18:05:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1721470 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=MZyaK10k; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4NnHb872KVz23ff for ; Thu, 5 Jan 2023 05:05:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239978AbjADSFy (ORCPT ); Wed, 4 Jan 2023 13:05:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239903AbjADSFu (ORCPT ); Wed, 4 Jan 2023 13:05:50 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7EC5108A; Wed, 4 Jan 2023 10:05:49 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 43A906179B; Wed, 4 Jan 2023 18:05:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CF8A6C43396; Wed, 4 Jan 2023 18:05:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672855548; bh=SpxUfboVfaSWtvMSqW0B+NZAeloH/U4lZdg9RHU4N3c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MZyaK10kBqxH/xTpI6ZGaW6VYehCAWKr4pIlLC7OEE5Psip32Y1FhtVa0esLwfIWY Ucp6yTs8EtQAPPX4mLo3Z0ezzgA37F2YHznb+fLhEx2N2Vsiozsi1dpb98R05e6Ji3 4lWe9XtR83YxVnriLYZOjZoD2Sp03q5B3sQZFdiYvC0KSoh0qTalDm+0MMI1dNhr8z Mu2JoS+NnX8D5IS6VbhLD60LXXuhyR3tndeHWHxA+zpNdiLGT55SteqzINdxY19xN0 huKDkhxNkaJr+cINkBg+nXZEYk/SkmnOnyfa/Aav1Ilklsd5dRp5MyPBymK33013/p t9ImPPAILndaA== From: Conor Dooley To: palmer@dabbelt.com Cc: conor@kernel.org, Conor Dooley , Ley Foon Tan , Sudeep Holla , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Alex Shi , Yanteng Si , Lorenzo Pieralisi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org Subject: [PATCH v1 1/2] dt-bindings: arm: move cpu-capacity to a shared loation Date: Wed, 4 Jan 2023 18:05:13 +0000 Message-Id: <20230104180513.1379453-2-conor@kernel.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230104180513.1379453-1-conor@kernel.org> References: <20230104180513.1379453-1-conor@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4078; i=conor.dooley@microchip.com; h=from:subject; bh=EHhLKTpL8b24ylcqPJCu6roLTdkZjz8WegHWiaxDAkY=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMlb91+c0cf+KyCreJNWx16FJ+++CThmLNT2+X5p868tcjfN H29431HKwiDGwSArpsiSeLuvRWr9H5cdzj1vYeawMoEMYeDiFICJ/O5n+O/29NHEsKfOfOqBdjd+b/ /64NeTzX2i7xX/C1jdWFCg47COkWGp9LYpxfppoocYSyYqhum2eh2Y86/V/sqUG2sjGEKfsDMCAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley RISC-V uses the same generic topology code as arm64 & while there currently exists no binding for cpu-capacity on RISC-V, the code paths can be hit if the property is present. Move the documentation of cpu-capacity to a shared location, ahead of defining a binding for capacity-dmips-mhz on RISC-V. Update some references to this document in the process. Signed-off-by: Conor Dooley Reviewed-by: Ley Foon Tan Acked-by: Rob Herring Reviewed-by: Yanteng Si --- I wasn't sure what to do with reference [1], but since the property will be the same on RISC-V, I left it as is. --- Documentation/devicetree/bindings/arm/cpus.yaml | 2 +- .../devicetree/bindings/{arm => cpu}/cpu-capacity.txt | 4 ++-- Documentation/scheduler/sched-capacity.rst | 2 +- Documentation/translations/zh_CN/scheduler/sched-capacity.rst | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) rename Documentation/devicetree/bindings/{arm => cpu}/cpu-capacity.txt (98%) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 01b5a9c689a2..a7586295a6f5 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -257,7 +257,7 @@ properties: capacity-dmips-mhz: description: - u32 value representing CPU capacity (see ./cpu-capacity.txt) in + u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. diff --git a/Documentation/devicetree/bindings/arm/cpu-capacity.txt b/Documentation/devicetree/bindings/cpu/cpu-capacity.txt similarity index 98% rename from Documentation/devicetree/bindings/arm/cpu-capacity.txt rename to Documentation/devicetree/bindings/cpu/cpu-capacity.txt index cc5e190390b7..f28e1adad428 100644 --- a/Documentation/devicetree/bindings/arm/cpu-capacity.txt +++ b/Documentation/devicetree/bindings/cpu/cpu-capacity.txt @@ -1,12 +1,12 @@ ========================================== -ARM CPUs capacity bindings +CPU capacity bindings ========================================== ========================================== 1 - Introduction ========================================== -ARM systems may be configured to have cpus with different power/performance +Some systems may be configured to have cpus with different power/performance characteristics within the same chip. In this case, additional information has to be made available to the kernel for it to be aware of such differences and take decisions accordingly. diff --git a/Documentation/scheduler/sched-capacity.rst b/Documentation/scheduler/sched-capacity.rst index 805f85f330b5..8e2b8538bc2b 100644 --- a/Documentation/scheduler/sched-capacity.rst +++ b/Documentation/scheduler/sched-capacity.rst @@ -260,7 +260,7 @@ for that purpose. The arm and arm64 architectures directly map this to the arch_topology driver CPU scaling data, which is derived from the capacity-dmips-mhz CPU binding; see -Documentation/devicetree/bindings/arm/cpu-capacity.txt. +Documentation/devicetree/bindings/cpu/cpu-capacity.txt. 3.2 Frequency invariance ------------------------ diff --git a/Documentation/translations/zh_CN/scheduler/sched-capacity.rst b/Documentation/translations/zh_CN/scheduler/sched-capacity.rst index 3a52053c29dc..e07ffdd391d3 100644 --- a/Documentation/translations/zh_CN/scheduler/sched-capacity.rst +++ b/Documentation/translations/zh_CN/scheduler/sched-capacity.rst @@ -233,7 +233,7 @@ CFS调度类基于实体负载跟踪机制（Per-Entity Load Tracking, PELT） arm和arm64架构直接把这个信息映射到arch_topology驱动的CPU scaling数据中（译注：参考 arch_topology.h的percpu变量cpu_scale），它是从capacity-dmips-mhz CPU binding中衍生计算 -出来的。参见Documentation/devicetree/bindings/arm/cpu-capacity.txt。 +出来的。参见Documentation/devicetree/bindings/cpu/cpu-capacity.txt。 3.2 频率不变性 -------------- From patchwork Wed Jan 4 18:05:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1721471 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=VN0/UaFF; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4NnHb93B1Wz23f5 for ; Thu, 5 Jan 2023 05:05:57 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239935AbjADSFz (ORCPT ); Wed, 4 Jan 2023 13:05:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239950AbjADSFx (ORCPT ); Wed, 4 Jan 2023 13:05:53 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E41FC10B41; Wed, 4 Jan 2023 10:05:52 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 807DF617CF; Wed, 4 Jan 2023 18:05:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1AEE2C433EF; Wed, 4 Jan 2023 18:05:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672855551; bh=7hi84JBUzFJsCseSml62aqokn8J6yG6QNrOsogIOB7E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VN0/UaFFVZqOMHF3674yqncE3YyRqpXDi5c4Zhr48kmPb5BzW1m0UyuTiRIPHTwJg 6ohuZFHYCy0Uz7JEkrOAPmJp6q3t2prjNBbnCCfNlUrPifBiZX/pgi8euV7gQdOoHP u2v2FU+cSLVuTKpaCiiBL0znJ/bqgcFgJPj811JgYfwkqFLv0/noGd2P054fbFSkum 27soQ27+YV2HwVuhOTPDmw4Uyao4A8MUh0qiDqJFteLKnA99okpwEfjT/aMBXpvWka G0/T0SrhpxzhLwOVaXNTAqDb8xn/dI3ZL3EJewf+ZPwTJfM1E7q1aRvADplGsGgBvl /27kkR1aysMtw== From: Conor Dooley To: palmer@dabbelt.com Cc: conor@kernel.org, Conor Dooley , Ley Foon Tan , Sudeep Holla , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Alex Shi , Yanteng Si , Lorenzo Pieralisi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org Subject: [PATCH v1 2/2] dt-bindings: riscv: add a capacity-dmips-mhz cpu property Date: Wed, 4 Jan 2023 18:05:14 +0000 Message-Id: <20230104180513.1379453-3-conor@kernel.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230104180513.1379453-1-conor@kernel.org> References: <20230104180513.1379453-1-conor@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1179; i=conor.dooley@microchip.com; h=from:subject; bh=o07jjdwBTatvOwh4zgdAJ4rsKJozF7vor3izbX7Vg94=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMlb91/MCL97v/HRZP+ZQQoTbpy8ObPJZKryPqsFBjsulS4U ZU1Y21HKwiDGwSArpsiSeLuvRWr9H5cdzj1vYeawMoEMYeDiFICJ3H/D8FdGeDLTxqseKd6GMz+vn2 dw6/qlJwmcR85k5/KW588P13jA8Fc6rkupS13k7O3cN8f+q/6375qlbHJd6PmVowdZAyzu/uECAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Since commit 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.") RISC-V has used the generic arch topology code, which provides for disparate CPU capacities. We never defined a binding to acquire this information from the DT though, so document the one already used by the generic arch topology code: "capacity-dmips-mhz". Signed-off-by: Conor Dooley Reviewed-by: Ley Foon Tan Acked-by: Rob Herring --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c6720764e765..2480c2460759 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -114,6 +114,12 @@ properties: List of phandles to idle state nodes supported by this hart (see ./idle-states.yaml). + capacity-dmips-mhz: + description: + u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in + DMIPS/MHz, relative to highest capacity-dmips-mhz + in the system. + required: - riscv,isa - interrupt-controller