From patchwork Sat Dec 10 10:30:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 1714384 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=4I3+0nHh; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NTkgp3v7nz2404 for ; Sat, 10 Dec 2022 21:31:00 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0JWJzXuen7JVhsYPkhtwGq9OgVY24lnqZdQgLzAR6S0=; b=4I3+0nHh4xnhgP mTrlPTaoTvaHRNcF6f5PmgOTGfc0TnvOT6Ze+1tDXXlAsZrHMQMU+VqXCwt0y+zUzxSr5dQQ4PA70 oA39Cy1ghPFKmHznpsMR2c3vRBStaSCFNtQ5AE2vQUTOGHqmTDWj7OpxSpVgJey3AgBpaOfSg/6uV T6XQ8GE2DActycModwmJks6+SP/Odn0i8KNhp/bpl8XDJcfcMdyUO1UBie0I+7Vrox/YhV9pVPOUo wSM4fkteZ901HyRl495RekpVv38YnWHzU5gun3ifV5TSxm90RUAKjnG/8uIKyXAsZvfmy2Kymi3mN bKYH9EbsF8UvrcvRIwaQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p3x7w-00GKUY-OX; Sat, 10 Dec 2022 10:30:40 +0000 Received: from relmlor2.renesas.com ([210.160.252.172] helo=relmlie6.idc.renesas.com) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p3x7q-00GKQA-S3 for opensbi@lists.infradead.org; Sat, 10 Dec 2022 10:30:37 +0000 X-IronPort-AV: E=Sophos;i="5.96,232,1665414000"; d="scan'208";a="145700469" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 10 Dec 2022 19:30:30 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id D4BDA421B362; Sat, 10 Dec 2022 19:30:27 +0900 (JST) From: Lad Prabhakar To: Anup Patel , Atish Patra , opensbi@lists.infradead.org Cc: Bin Meng , Yu Chien Peter Lin , Andrew Jones , Biju Das , Chris Paterson , Prabhakar , Lad Prabhakar Subject: [PATCH v5 1/5] lib: utils: serial: Add Renesas SCIF driver Date: Sat, 10 Dec 2022 10:30:07 +0000 Message-Id: <20221210103011.7814-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221210_023035_035282_232A3A9F X-CRM114-Status: GOOD ( 14.26 ) X-Spam-Score: 0.0 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Add Renesas SCIF driver. Based on a patch in the BSP by Takeki Hamada Link: https://github.com/renesas-rz/rz_opensbi/commits/work/OpenSBI-PMA Signed-off-by: Lad Prabhakar --- v4->v5 * No change Content analysis details: (0.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Add Renesas SCIF driver. Based on a patch in the BSP by Takeki Hamada Link: https://github.com/renesas-rz/rz_opensbi/commits/work/OpenSBI-PMA Signed-off-by: Lad Prabhakar Reviewed-by: Anup Patel --- v4->v5 * No change v3->v4 * Dropped returning from void func * Dropped unnecessary volatile variable v2->v3 * Fixed review comments pointed by Bin RFC->v2 * Fixed comments pointed by Xiang W --- include/sbi_utils/serial/renesas-scif.h | 11 +++ lib/utils/serial/Kconfig | 4 + lib/utils/serial/objects.mk | 1 + lib/utils/serial/renesas_scif.c | 116 ++++++++++++++++++++++++ 4 files changed, 132 insertions(+) create mode 100644 include/sbi_utils/serial/renesas-scif.h create mode 100644 lib/utils/serial/renesas_scif.c diff --git a/include/sbi_utils/serial/renesas-scif.h b/include/sbi_utils/serial/renesas-scif.h new file mode 100644 index 0000000..0002a1a --- /dev/null +++ b/include/sbi_utils/serial/renesas-scif.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (C) 2022 Renesas Electronics Corporation + */ + +#ifndef __SERIAL_RENESAS_SCIF_H__ +#define __SERIAL_RENESAS_SCIF_H__ + +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate); + +#endif /* __SERIAL_RENESAS_SCIF_H__ */ diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig index da549a7..f6ed803 100644 --- a/lib/utils/serial/Kconfig +++ b/lib/utils/serial/Kconfig @@ -59,6 +59,10 @@ config SERIAL_GAISLER bool "Gaisler UART support" default n +config SERIAL_RENESAS_SCIF + bool "Renesas SCIF support" + default n + config SERIAL_SHAKTI bool "Shakti UART support" default n diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk index 98f3f9a..6520424 100644 --- a/lib/utils/serial/objects.mk +++ b/lib/utils/serial/objects.mk @@ -36,6 +36,7 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_XILINX_UARTLITE) += serial/fdt_serial_xlnx_ libsbiutils-objs-$(CONFIG_SERIAL_CADENCE) += serial/cadence-uart.o libsbiutils-objs-$(CONFIG_SERIAL_GAISLER) += serial/gaisler-uart.o +libsbiutils-objs-$(CONFIG_SERIAL_RENESAS_SCIF) += serial/renesas_scif.o libsbiutils-objs-$(CONFIG_SERIAL_SHAKTI) += serial/shakti-uart.o libsbiutils-objs-$(CONFIG_SERIAL_SIFIVE) += serial/sifive-uart.o libsbiutils-objs-$(CONFIG_SERIAL_LITEX) += serial/litex-uart.o diff --git a/lib/utils/serial/renesas_scif.c b/lib/utils/serial/renesas_scif.c new file mode 100644 index 0000000..cbe9db4 --- /dev/null +++ b/lib/utils/serial/renesas_scif.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Copyright (C) 2022 Renesas Electronics Corporation + */ + +#include +#include +#include +#include + +/* clang-format off */ + +#define SCIF_REG_SMR 0x0 +#define SCIF_REG_BRR 0x2 +#define SCIF_REG_SCR 0x4 +#define SCIF_REG_FTDR 0x6 +#define SCIF_REG_FSR 0x8 +#define SCIF_REG_FCR 0xc +#define SCIF_REG_LSR 0x12 +#define SCIF_REG_SEMR 0x14 + +#define SCIF_FCR_RFRST 0x2 /* Reset assert receive-FIFO (bit[1]) */ +#define SCIF_FCR_TFRST 0x4 /* Reset assert transmit-FIFO(bit[2]) */ + +#define SCIF_FCR_RST_ASSRT_RFTF (SCIF_FCR_RFRST | SCIF_FCR_TFRST) /* Reset assert tx-FIFO & rx-FIFO */ +#define SCIF_FCR_RST_NGATE_RFTF 0x0 /* Reset negate tx-FIFO & rx-FIFO */ + +#define SCIF_SCR_RE 0x10 /* Enable receive (bit[4]) */ +#define SCIF_SCR_TE 0x20 /* Enable transmit(bit[5]) */ +#define SCIF_SCR_RCV_TRN_EN (SCIF_SCR_RE | SCIF_SCR_TE) /* Enable receive & transmit */ +#define SCIF_SCR_RCV_TRN_DIS 0x0 /* Disable receive & transmit */ + +#define SCIF_FSR_ER 0x80 /* Receive error flag */ +#define SCIF_FSR_TEND 0x40 /* Transmit End Flag */ +#define SCIF_FSR_TDFE 0x20 /* Transmit FIFO Data Empty Flag */ +#define SCIF_FSR_BRK 0x10 /* Detect break flag */ +#define SCIF_FSR_DR 0x1 /* Receive data ready flag */ + +#define SCIF_FSR_TXD_CHK (SCIF_FSR_TEND | SCIF_FSR_TDFE) + +#define SCIF_SEMR_MDDRS 0x10 /* MDDR access enable */ + +#define SCIF_REG_8BIT(reg) ((reg == SCIF_REG_BRR) || \ + (reg == SCIF_REG_FTDR) || \ + (reg == SCIF_REG_SEMR)) + +#define SCBRR_VALUE(clk, baudrate) ((clk) / (32 * (baudrate)) - 1) + +/* clang-format on */ + +static volatile char *scif_base; + +static u32 get_reg(u32 offset) +{ + if (SCIF_REG_8BIT(offset)) + return readb(scif_base + offset); + + return readw(scif_base + offset); +} + +static void set_reg(u32 offset, u32 val) +{ + if (SCIF_REG_8BIT(offset)) + writeb(val, scif_base + offset); + else + writew(val, scif_base + offset); +} + +static void renesas_scif_putc(char ch) +{ + uint16_t reg; + + while (!(SCIF_FSR_TXD_CHK & get_reg(SCIF_REG_FSR))) + ; + + set_reg(SCIF_REG_FTDR, ch); + reg = get_reg(SCIF_REG_FSR); + reg &= ~SCIF_FSR_TXD_CHK; + set_reg(SCIF_REG_FSR, reg); +} + +static struct sbi_console_device renesas_scif_console = { + .name = "renesas_scif", + .console_putc = renesas_scif_putc, +}; + +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate) +{ + uint16_t data16; + + scif_base = (volatile char *)base; + + set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_DIS); + set_reg(SCIF_REG_FCR, SCIF_FCR_RST_ASSRT_RFTF); + + data16 = get_reg(SCIF_REG_FSR); /* Dummy read */ + set_reg(SCIF_REG_FSR, 0x0); /* Clear all error bit */ + + data16 = get_reg(SCIF_REG_LSR); /* Dummy read */ + set_reg(SCIF_REG_LSR, 0x0); /* Clear ORER bit */ + + set_reg(SCIF_REG_SCR, 0x0); + + set_reg(SCIF_REG_SMR, 0x0); + + data16 = get_reg(SCIF_REG_SEMR); + set_reg(SCIF_REG_SEMR, data16 & (~SCIF_SEMR_MDDRS)); + set_reg(SCIF_REG_BRR, SCBRR_VALUE(in_freq, baudrate)); + + set_reg(SCIF_REG_FCR, SCIF_FCR_RST_NGATE_RFTF); + set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_EN); + + sbi_console_set_device(&renesas_scif_console); + + return 0; +} From patchwork Sat Dec 10 10:30:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 1714386 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: legolas.ozlabs.org; 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Sat, 10 Dec 2022 19:30:31 +0900 (JST) From: Lad Prabhakar To: Anup Patel , Atish Patra , opensbi@lists.infradead.org Cc: Bin Meng , Yu Chien Peter Lin , Andrew Jones , Biju Das , Chris Paterson , Prabhakar , Lad Prabhakar Subject: [PATCH v5 2/5] lib: utils: serial: Add FDT driver for Renesas SCIF Date: Sat, 10 Dec 2022 10:30:08 +0000 Message-Id: <20221210103011.7814-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221210_023037_847938_F4B42D54 X-CRM114-Status: GOOD ( 12.72 ) X-Spam-Score: 0.0 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Add FDT driver for Renesas SCIF. dts example: soc: soc { .... scif0: serial@1004b800 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004b800 0 0x400>; interrupts = <412 IRQ_TYPE_LEVEL_HIGH>, <414 IRQ_TYPE_LEVEL_HIG [...] Content analysis details: (0.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Add FDT driver for Renesas SCIF. dts example: soc: soc { .... scif0: serial@1004b800 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004b800 0 0x400>; interrupts = <412 IRQ_TYPE_LEVEL_HIGH>, <414 IRQ_TYPE_LEVEL_HIGH>, <415 IRQ_TYPE_LEVEL_HIGH>, <413 IRQ_TYPE_LEVEL_HIGH>, <416 IRQ_TYPE_LEVEL_HIGH>, <416 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; clock-names = "fck"; power-domains = <&cpg>; resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; status = "disabled"; }; .... }; Signed-off-by: Lad Prabhakar Reviewed-by: Anup Patel --- v4->v5 * No change v3->v4 * Included RB tag v2->v3 * No change RFC->v2 * Dropped DEFAULT_RENESAS_SCIF_REG_SHIFT and DEFAULT_RENESAS_SCIF_REG_IO_WIDTH macros. DT binding [0]. [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/serial/renesas,scif.yaml?h=next-20221111#n80 --- include/sbi_utils/fdt/fdt_helper.h | 3 +++ lib/utils/fdt/fdt_helper.c | 11 ++++++++ lib/utils/serial/Kconfig | 5 ++++ lib/utils/serial/fdt_serial_renesas_scif.c | 31 ++++++++++++++++++++++ lib/utils/serial/objects.mk | 3 +++ 5 files changed, 53 insertions(+) create mode 100644 lib/utils/serial/fdt_serial_renesas_scif.c diff --git a/include/sbi_utils/fdt/fdt_helper.h b/include/sbi_utils/fdt/fdt_helper.h index c39f77a..09f3095 100644 --- a/include/sbi_utils/fdt/fdt_helper.h +++ b/include/sbi_utils/fdt/fdt_helper.h @@ -59,6 +59,9 @@ int fdt_parse_timebase_frequency(void *fdt, unsigned long *freq); int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset, struct platform_uart_data *uart); +int fdt_parse_renesas_scif_node(void *fdt, int nodeoffset, + struct platform_uart_data *uart); + int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset, struct platform_uart_data *uart); diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c index d4b38dc..48bc2fe 100644 --- a/lib/utils/fdt/fdt_helper.c +++ b/lib/utils/fdt/fdt_helper.c @@ -23,6 +23,9 @@ #define DEFAULT_UART_REG_IO_WIDTH 1 #define DEFAULT_UART_REG_OFFSET 0 +#define DEFAULT_RENESAS_SCIF_FREQ 100000000 +#define DEFAULT_RENESAS_SCIF_BAUD 115200 + #define DEFAULT_SIFIVE_UART_FREQ 0 #define DEFAULT_SIFIVE_UART_BAUD 115200 @@ -355,6 +358,14 @@ int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset, DEFAULT_UART_BAUD); } +int fdt_parse_renesas_scif_node(void *fdt, int nodeoffset, + struct platform_uart_data *uart) +{ + return fdt_parse_uart_node_common(fdt, nodeoffset, uart, + DEFAULT_RENESAS_SCIF_FREQ, + DEFAULT_RENESAS_SCIF_BAUD); +} + int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset, struct platform_uart_data *uart) { diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig index f6ed803..e3589ca 100644 --- a/lib/utils/serial/Kconfig +++ b/lib/utils/serial/Kconfig @@ -24,6 +24,11 @@ config FDT_SERIAL_HTIF select SYS_HTIF default n +config FDT_SERIAL_RENESAS_SCIF + bool "Renesas SCIF FDT driver" + select SERIAL_RENESAS_SCIF + default n + config FDT_SERIAL_SHAKTI bool "Shakti UART FDT driver" select SERIAL_SHAKTI diff --git a/lib/utils/serial/fdt_serial_renesas_scif.c b/lib/utils/serial/fdt_serial_renesas_scif.c new file mode 100644 index 0000000..c331ca1 --- /dev/null +++ b/lib/utils/serial/fdt_serial_renesas_scif.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Copyright (C) 2022 Renesas Electronics Corporation + */ + +#include +#include +#include + +static int serial_renesas_scif_init(void *fdt, int nodeoff, + const struct fdt_match *match) +{ + struct platform_uart_data uart = { 0 }; + int ret; + + ret = fdt_parse_renesas_scif_node(fdt, nodeoff, &uart); + if (ret) + return ret; + + return renesas_scif_init(uart.addr, uart.freq, uart.baud); +} + +static const struct fdt_match serial_renesas_scif_match[] = { + { .compatible = "renesas,scif-r9a07g043" }, + { /* sentinel */ } +}; + +struct fdt_serial fdt_serial_renesas_scif = { + .match_table = serial_renesas_scif_match, + .init = serial_renesas_scif_init +}; diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk index 6520424..1e6bd2e 100644 --- a/lib/utils/serial/objects.mk +++ b/lib/utils/serial/objects.mk @@ -19,6 +19,9 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_GAISLER) += serial/fdt_serial_gaisler.o carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_HTIF) += fdt_serial_htif libsbiutils-objs-$(CONFIG_FDT_SERIAL_HTIF) += serial/fdt_serial_htif.o +carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_RENESAS_SCIF) += fdt_serial_renesas_scif +libsbiutils-objs-$(CONFIG_FDT_SERIAL_RENESAS_SCIF) += serial/fdt_serial_renesas_scif.o + carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_SHAKTI) += fdt_serial_shakti libsbiutils-objs-$(CONFIG_FDT_SERIAL_SHAKTI) += serial/fdt_serial_shakti.o From patchwork Sat Dec 10 10:30:09 2022 Content-Type: text/plain; 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Sat, 10 Dec 2022 10:30:44 +0000 Received: from relmlor1.renesas.com ([210.160.252.171] helo=relmlie5.idc.renesas.com) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p3x7u-00GKRJ-D4 for opensbi@lists.infradead.org; Sat, 10 Dec 2022 10:30:39 +0000 X-IronPort-AV: E=Sophos;i="5.96,232,1665414000"; d="scan'208";a="142891946" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 10 Dec 2022 19:30:37 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id BE501421B362; Sat, 10 Dec 2022 19:30:34 +0900 (JST) From: Lad Prabhakar To: Anup Patel , Atish Patra , opensbi@lists.infradead.org Cc: Bin Meng , Yu Chien Peter Lin , Andrew Jones , Biju Das , Chris Paterson , Prabhakar , Lad Prabhakar Subject: [PATCH v5 3/5] lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100 Date: Sat, 10 Dec 2022 10:30:09 +0000 Message-Id: <20221210103011.7814-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221210_023038_640606_A28D1C0D X-CRM114-Status: UNSURE ( 8.86 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.0 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Add compatible string for Andestech NCEPLIC100 found on Renesas RZ/Five SoC which is equipped with AX45MP AndesCore. While at it drop the comma after the sentinel as it does not make sense to have a comma after a sentinel, as any new elements must be added before the sentinel. Content analysis details: (0.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Add compatible string for Andestech NCEPLIC100 found on Renesas RZ/Five SoC which is equipped with AX45MP AndesCore. While at it drop the comma after the sentinel as it does not make sense to have a comma after a sentinel, as any new elements must be added before the sentinel. dts example (Single-core AX45MP): soc: soc { .... plic: interrupt-controller@12c00000 { compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; #interrupt-cells = <2>; #address-cells = <0>; riscv,ndev = <511>; interrupt-controller; reg = <0x0 0x12c00000 0 0x400000>; clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; power-domains = <&cpg>; resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; }; .... }; Signed-off-by: Lad Prabhakar Reviewed-by: Anup Patel Reviewed-by: Bin Meng --- v4->v5 * No change v3->v4 * Sorted compatible string list v2->v3 * Included RB tags RFC->v2 * No change DT binding [0] [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml?h=next-20221111#n56 --- lib/utils/irqchip/fdt_irqchip_plic.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c index fe08836..8e90fa7 100644 --- a/lib/utils/irqchip/fdt_irqchip_plic.c +++ b/lib/utils/irqchip/fdt_irqchip_plic.c @@ -159,11 +159,12 @@ void thead_plic_restore(void) } static const struct fdt_match irqchip_plic_match[] = { + { .compatible = "andestech,nceplic100" }, { .compatible = "riscv,plic0" }, { .compatible = "sifive,plic-1.0.0" }, { .compatible = "thead,c900-plic", .data = thead_plic_plat_init }, - { }, + { /* sentinel */ } }; struct fdt_irqchip fdt_irqchip_plic = { From patchwork Sat Dec 10 10:30:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 1714388 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=J++HH7Bv; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NTkgv2jZqz23ns for ; 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Sat, 10 Dec 2022 10:30:52 +0000 Received: from relmlor1.renesas.com ([210.160.252.171] helo=relmlie5.idc.renesas.com) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p3x7x-00GKVA-Sb for opensbi@lists.infradead.org; Sat, 10 Dec 2022 10:30:43 +0000 X-IronPort-AV: E=Sophos;i="5.96,232,1665414000"; d="scan'208";a="142891951" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 10 Dec 2022 19:30:41 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 3635E421B67B; Sat, 10 Dec 2022 19:30:37 +0900 (JST) From: Lad Prabhakar To: Anup Patel , Atish Patra , opensbi@lists.infradead.org Cc: Bin Meng , Yu Chien Peter Lin , Andrew Jones , Biju Das , Chris Paterson , Prabhakar , Lad Prabhakar Subject: [PATCH v5 4/5] platform: generic: Add Renesas RZ/Five initial support Date: Sat, 10 Dec 2022 10:30:10 +0000 Message-Id: <20221210103011.7814-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221210_023042_102269_AC8624C9 X-CRM114-Status: GOOD ( 11.68 ) X-Spam-Score: 0.0 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: This commit provides basic support for the Renesas RZ/Five (R9A07G043F) SoC. The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP) 1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include: - Gigabit Ethernet 2ch - CAN interface (CAN-FD) 2ch - US [...] Content analysis details: (0.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org This commit provides basic support for the Renesas RZ/Five (R9A07G043F) SoC. The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP) 1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include: - Gigabit Ethernet 2ch - CAN interface (CAN-FD) 2ch - USB 2.0 interface 2ch - SD interface 2ch - AD converter 2ch Useful links: ------------- Links: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet Links: http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/ Signed-off-by: Lad Prabhakar Reviewed-by: Anup Patel --- v4->v5 * No change v3->v4 * Replaced "renesas,r9a07g043" -> "renesas,r9a07g043f01" * Included RB tag v2->v3 * New patch --- platform/generic/Kconfig | 4 ++++ platform/generic/configs/defconfig | 2 ++ platform/generic/renesas/rzfive/objects.mk | 8 ++++++++ platform/generic/renesas/rzfive/rzfive.c | 17 +++++++++++++++++ 4 files changed, 31 insertions(+) create mode 100644 platform/generic/renesas/rzfive/objects.mk create mode 100644 platform/generic/renesas/rzfive/rzfive.c diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig index 4b5d2cd..62c7a2d 100644 --- a/platform/generic/Kconfig +++ b/platform/generic/Kconfig @@ -32,6 +32,10 @@ config PLATFORM_ANDES_AE350 bool "Andes AE350 support" default n +config PLATFORM_RENESAS_RZFIVE + bool "Renesas RZ/Five support" + default n + config PLATFORM_SIFIVE_FU540 bool "SiFive FU540 support" default n diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig index 2eaeeb7..47fca95 100644 --- a/platform/generic/configs/defconfig +++ b/platform/generic/configs/defconfig @@ -1,5 +1,6 @@ CONFIG_PLATFORM_ALLWINNER_D1=y CONFIG_PLATFORM_ANDES_AE350=y +CONFIG_PLATFORM_RENESAS_RZFIVE=y CONFIG_PLATFORM_SIFIVE_FU540=y CONFIG_PLATFORM_SIFIVE_FU740=y CONFIG_FDT_GPIO=y @@ -24,6 +25,7 @@ CONFIG_FDT_SERIAL=y CONFIG_FDT_SERIAL_CADENCE=y CONFIG_FDT_SERIAL_GAISLER=y CONFIG_FDT_SERIAL_HTIF=y +CONFIG_FDT_SERIAL_RENESAS_SCIF=y CONFIG_FDT_SERIAL_SHAKTI=y CONFIG_FDT_SERIAL_SIFIVE=y CONFIG_FDT_SERIAL_LITEX=y diff --git a/platform/generic/renesas/rzfive/objects.mk b/platform/generic/renesas/rzfive/objects.mk new file mode 100644 index 0000000..2e7e37f --- /dev/null +++ b/platform/generic/renesas/rzfive/objects.mk @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: BSD-2-Clause +# +# Copyright (C) 2022 Renesas Electronics Corp. +# + +carray-platform_override_modules-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas_rzfive +platform-objs-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas/rzfive/rzfive.o diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c new file mode 100644 index 0000000..ca182e3 --- /dev/null +++ b/platform/generic/renesas/rzfive/rzfive.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Renesas Electronics Corp. + * + */ + +#include +#include + +static const struct fdt_match renesas_rzfive_match[] = { + { .compatible = "renesas,r9a07g043f01" }, + { /* sentinel */ } +}; + +const struct platform_override renesas_rzfive = { + .match_table = renesas_rzfive_match, +}; From patchwork Sat Dec 10 10:30:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 1714389 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=K/IKmGRl; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NTkh13TrWz23ns for ; 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Sat, 10 Dec 2022 10:30:58 +0000 Received: from relmlor1.renesas.com ([210.160.252.171] helo=relmlie5.idc.renesas.com) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p3x80-00GKVA-Tn for opensbi@lists.infradead.org; Sat, 10 Dec 2022 10:30:48 +0000 X-IronPort-AV: E=Sophos;i="5.96,232,1665414000"; d="scan'208";a="142891959" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 10 Dec 2022 19:30:44 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id A3CEB421B362; Sat, 10 Dec 2022 19:30:41 +0900 (JST) From: Lad Prabhakar To: Anup Patel , Atish Patra , opensbi@lists.infradead.org Cc: Bin Meng , Yu Chien Peter Lin , Andrew Jones , Biju Das , Chris Paterson , Prabhakar , Lad Prabhakar Subject: [PATCH v5 5/5] docs: platform: Add documentation for Renesas RZ/Five SoC Date: Sat, 10 Dec 2022 10:30:11 +0000 Message-Id: <20221210103011.7814-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221210_023045_342197_6CA14EBA X-CRM114-Status: GOOD ( 14.09 ) X-Spam-Score: 0.0 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: This patch adds documentation to build Renesas RZ/Five (R9A07G043F) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Anup Patel --- v4->v5 * Updated generic.md to include RZ/Five SoC * Included RB tag Content analysis details: (0.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org This patch adds documentation to build Renesas RZ/Five (R9A07G043F) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Anup Patel --- v4->v5 * Updated generic.md to include RZ/Five SoC * Included RB tag v3->v4 * Added complete list of IP blocks v2->v3 * Updated doc with new build command RFC->v2 * Updated doc --- docs/platform/generic.md | 2 + docs/platform/platform.md | 5 + docs/platform/renesas-rzfive.md | 160 ++++++++++++++++++++++++++++++++ 3 files changed, 167 insertions(+) create mode 100644 docs/platform/renesas-rzfive.md diff --git a/docs/platform/generic.md b/docs/platform/generic.md index e8a3296..8e4cf2d 100644 --- a/docs/platform/generic.md +++ b/docs/platform/generic.md @@ -47,6 +47,7 @@ RISC-V Platforms Using Generic Platform * **Andes AE350 Platform** (*[andes-ae350.md]*) * **QEMU RISC-V Virt Machine** (*[qemu_virt.md]*) +* **Renesas RZ/Five SoC** (*[renesas-rzfive.md]*) * **Shakti C-class SoC Platform** (*[shakti_cclass.md]*) * **SiFive HiFive Unleashed** (*[sifive_fu540.md]*) * **Spike** (*[spike.md]*) @@ -54,6 +55,7 @@ RISC-V Platforms Using Generic Platform [andes-ae350.md]: andse-ae350.md [qemu_virt.md]: qemu_virt.md +[renesas-rzfive.md]: renesas-rzfive.md [shakti_cclass.md]: shakti_cclass.md [sifive_fu540.md]: sifive_fu540.md [spike.md]: spike.md diff --git a/docs/platform/platform.md b/docs/platform/platform.md index f291931..4504d87 100644 --- a/docs/platform/platform.md +++ b/docs/platform/platform.md @@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual and hardware platforms: processor based SOCs. More details on this platform can be found in the file *[shakti_cclass.md]*. +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five (R9A07G043F) SoC + used on the Renesas RZ/Five SMARC EVK board. More details on this platform can + be found in the file *[renesas-rzfive.md]*. + The code for these supported platforms can be used as example to implement support for other platforms. The *platform/template* directory also provides template files for implementing support for a new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments to facilitate the implementation. [spike.md]: spike.md [fpga-openpiton.md]: fpga-openpiton.md [shakti_cclass.md]: shakti_cclass.md +[renesas-rzfive.md]: renesas-rzfive.md diff --git a/docs/platform/renesas-rzfive.md b/docs/platform/renesas-rzfive.md new file mode 100644 index 0000000..a73c53f --- /dev/null +++ b/docs/platform/renesas-rzfive.md @@ -0,0 +1,160 @@ +Renesas RZ/Five SoC (R9A07G043F) Platform +========================================= +The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP) +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include: +- Memory controller for DDR4-1600 / DDR3L-1333 with 16 bits +- System RAM (RAM of 128 Kbytes (ECC)) +- SPI Multi I/O Bus Controller 1ch +- SD Card Host Interface/Multimedia Card Interface (SD/MMC) 2ch +- Serial Sound Interface (SSI) 4ch +- Sampling Rate Converter (SRC) 1ch +- USB2.0 host/function interface 2ch (ch0: Host-Function ch1: Host only) +- Gigabit Ethernet Interface (GbE) 2ch +- Controller Area Network Interface (CAN) 2ch (CAN-FD ISO 11898-1 (CD2014) compliant) +- Multi-function Timer Pulse Unit 3 (MTU3a) 9 ch (16 bits × 8 channels, 32 bits × 1 channel) +- Port Output Enable 3 (POE3) +- Watchdog Timer (WDT) 1ch +- General Timer (GTM) 3ch (32bits) +- I2C Bus Interface (I2C) 4ch +- Serial Communication Interface with FIFO (SCIFA) 5ch +- Serial Communication Interface (SCI) 2ch +- Renesas Serial Peripheral Interface (RSPI) 3ch +- A/D Converter (ADC) 2ch +making it ideal for applications such as entry-class social infrastructure +gateway control and industrial gateway control. More details can be found at +below link [0]. + +[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet + +To build platform specific library and firmwares, provide the +*PLATFORM=generic* parameter to the top level make command. + +Platform Options +---------------- + +The Renesas RZ/Five platform does not have any platform-specific options. + +Building Renesas RZ/Five Platform +--------------------------------- + +``` +make PLATFORM=generic +``` + +DTS Example: (RZ/Five AX45MP) +----------------------------- + +``` + compatible = "renesas,r9a07g043f01", "renesas,r9a07g043"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <12000000>; + + cpu0: cpu@0 { + compatible = "andestech,ax45mp", "riscv"; + device_type = "cpu"; + reg = <0x0>; + status = "okay"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + ranges; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = <412 IRQ_TYPE_LEVEL_HIGH>, + <414 IRQ_TYPE_LEVEL_HIGH>, + <415 IRQ_TYPE_LEVEL_HIGH>, + <413 IRQ_TYPE_LEVEL_HIGH>, + <416 IRQ_TYPE_LEVEL_HIGH>, + <416 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g043-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g043-sysc"; + reg = <0 0x11020000 0 0x10000>; + status = "disabled"; + }; + + pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a07g043-pinctrl"; + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + gpio-ranges = <&pinctrl 0 0 152>; + clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_GPIO_RSTN>, + <&cpg R9A07G043_GPIO_PORT_RESETN>, + <&cpg R9A07G043_GPIO_SPARE_RESETN>; + }; + + plmt0: plmt0@110c0000 { + compatible = "andestech,plmt0", "riscv,plmt0"; + reg = <0x0 0x110c0000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 7>; + }; + + plic: interrupt-controller@12c00000 { + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; + #interrupt-cells = <2>; + #address-cells = <0>; + riscv,ndev = <511>; + interrupt-controller; + reg = <0x0 0x12c00000 0x0 0x400000>; + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; + }; + + plicsw: interrupt-controller@13000000 { + compatible = "andestech,plicsw"; + reg = <0x0 0x13000000 0x0 0x400000>; + interrupts-extended = <&cpu0_intc 3>; + interrupt-controller; + #address-cells = <2>; + #interrupt-cells = <2>; + }; + }; +```