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bh=pcnH56OFvsk8Kx32CUCXEoG8dP5vyL/U3G/PtFMD5tw=; b=bydFAusihR/ejwBLAyaYU1SWN9hQJe+T69i+BPhmIUmphZdFF5D5gCqsw6XWJUhd5k C1jxQnA8knWiP8KvsluTyDngcmcvnTuE6D/vv8+K+i615wkbH+M3B/aIgwggeG6KEhGF 4261QCn/JW/JDms36exWDhW1oL9GB2DyLBcDbb32a8oLSA8/qwfJZKt7yImdocvg5RNa S6iExz66RXV46dj8lJVHX3c9PJUdyhkQxyF7zffE0Wx4RlV7CNlDkHyNSCL3zoR5a1ux Oa8w1HAVcArAnd+5POGgFJ5YbbEsQKK5IeaNQBm0xtWs7ecearfgJwxiYLKPIfsz++iy 276g== X-Gm-Message-State: ACgBeo3w69xcQ2CNhNFY8jFlQJqQ81893pZZ1DInIm8KvHSwkpL2QVae yfhV4lrUUfEzeHlSQL2hKHo= X-Google-Smtp-Source: AA6agR4S2GIZgbr0L9iLT3P11D/Zum9Kjk3OwaJLCTRpLQyMnPQMdg+ZVAkdWc5bfJ5U1R2cGdrfpg== X-Received: by 2002:a17:902:e402:b0:176:e82f:3f4 with SMTP id m2-20020a170902e40200b00176e82f03f4mr30255821ple.107.1663050206804; Mon, 12 Sep 2022 23:23:26 -0700 (PDT) Received: from localhost.localdomain ([180.217.131.242]) by smtp.gmail.com with ESMTPSA id c128-20020a624e86000000b0054094544ae7sm6846330pfb.60.2022.09.12.23.23.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 23:23:26 -0700 (PDT) From: Jim Liu X-Google-Original-From: Jim Liu To: trini@konsulko.com, JJLIU0@nuvoton.com, YSCHU@nuvoton.com, KWLIU@nuvoton.com Cc: u-boot@lists.denx.de Subject: [PATCH v1] pinctrl: nuvoton: fix set persist error Date: Tue, 13 Sep 2022 14:23:15 +0800 Message-Id: <20220913062315.5972-1-JJLIU0@nuvoton.com> X-Mailer: git-send-email 2.17.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean CA9C is cortex A9 watchdog reset control bit. if device set persist mode, it shouldn't set this bit. Signed-off-by: Jim Liu --- drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index f6e20415e2..31678f5537 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -1388,10 +1388,10 @@ static int npcm7xx_gpio_reset_persist(struct udevice *dev, unsigned int banknum, dev_dbg(dev, "set gpio persist, bank %d, enable %d\n", banknum, enable); if (enable) { - regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num) | CA9C_RESET, 0); - regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num) | CA9C_RESET, 0); - regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num) | CA9C_RESET, 0); - regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num) | CA9C_RESET, 0); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num), 0); } else { regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);