From patchwork Sat Sep 10 19:56:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 1676403 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=baikalelectronics.ru header.i=@baikalelectronics.ru header.a=rsa-sha256 header.s=mail header.b=k2AVBGLO; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4MQ3YD5c66z1ypB for ; Sun, 11 Sep 2022 05:57:20 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229811AbiIJT5S (ORCPT ); Sat, 10 Sep 2022 15:57:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229842AbiIJT5O (ORCPT ); Sat, 10 Sep 2022 15:57:14 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B68C143637; Sat, 10 Sep 2022 12:57:03 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 6B6DDDA5; Sat, 10 Sep 2022 23:00:52 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 6B6DDDA5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662840052; bh=cB0N8dfWEL/C71MywOBEwKVvRrfKc3aPyovJSHro/iE=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=k2AVBGLOrHMiTU3eQrrdpeZmvMyZJmtapvhvRyguU5JyuoULxvGsvDGCFz7O12g8q ZSrNbt0Lx7uva2kb/oLFFwft574nnrR3wTGu5NETVXufblHr4RUJXRk1XcYkObiiLX rssHcDfSWAnuGxZEJcAM31/TvrMfwtmjMt7WjLPA= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sat, 10 Sep 2022 22:57:01 +0300 From: Serge Semin To: Rob Herring , Krzysztof Kozlowski , Michal Simek , Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , Krzysztof Kozlowski , Manish Narani CC: Serge Semin , Serge Semin , Alexey Malahov , Michail Ivanov , Pavel Parkhomenko , Punnaiah Choudary Kalluri , Dinh Nguyen , James Morse , Robert Richter , Rob Herring , , , , , Krzysztof Kozlowski Subject: [PATCH v2 01/15] dt-bindings: memory: snps: Replace opencoded numbers with macros Date: Sat, 10 Sep 2022 22:56:45 +0300 Message-ID: <20220910195659.11843-2-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220910195659.11843-1-Sergey.Semin@baikalelectronics.ru> References: <20220910195659.11843-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Xilinx ZynqMP DDRC-based example contains the opencoded numerical literals in the IRQ lines definition. It doesn't seem justified since the corresponding platform has well defined ARM GIC interface. Let's replace the numbers with the corresponding macros then. Signed-off-by: Serge Semin Acked-by: Rob Herring --- Changelog v2: - This is a new patch created on v2 based on the @Krzysztof' request not to have the opencoded numbers in the bindings example. (@Krzysztof) --- .../bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml index 9212dfe6e956..fb571d3d665d 100644 --- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml @@ -47,10 +47,13 @@ additionalProperties: false examples: - | + #include + memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0xfd070000 0x30000>; + interrupt-parent = <&gic>; - interrupts = <0 112 4>; + interrupts = ; }; ... From patchwork Sat Sep 10 19:56:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 1676405 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=baikalelectronics.ru header.i=@baikalelectronics.ru header.a=rsa-sha256 header.s=mail header.b=jFNNMjAM; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4MQ3Yw5f9Kz1yhR for ; Sun, 11 Sep 2022 05:57:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230130AbiIJT5w (ORCPT ); Sat, 10 Sep 2022 15:57:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229989AbiIJT5X (ORCPT ); Sat, 10 Sep 2022 15:57:23 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 90A5245F7F; Sat, 10 Sep 2022 12:57:06 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 26BFFDA8; Sat, 10 Sep 2022 23:00:53 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 26BFFDA8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662840053; bh=C1cHVya5vTRX4BQybgGAblj68eUfTg6JA+yP2FgH028=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=jFNNMjAMSit/oQmQ5gkfa1u0hXBIhLI/13fYl3wrKOEDQgeh6/fXXPA2oDFd2ES9y GHdpsp7WtcaZ3jlrktQwnOCDs+bq46Z0lXP7Eb3ZJyC942JMg0eqC8e5TDBA6RB+Fx KEin80j9t7fyxHBXMbeMeUr2c5Sqb3UHxczRufS4= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sat, 10 Sep 2022 22:57:02 +0300 From: Serge Semin To: Rob Herring , Krzysztof Kozlowski , Michal Simek , Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , Krzysztof Kozlowski , Manish Narani CC: Serge Semin , Serge Semin , Alexey Malahov , Michail Ivanov , Pavel Parkhomenko , Punnaiah Choudary Kalluri , Dinh Nguyen , James Morse , Robert Richter , Rob Herring , , , , , Krzysztof Kozlowski Subject: [PATCH v2 02/15] dt-bindings: memory: snps: Extend schema with IRQs/resets/clocks props Date: Sat, 10 Sep 2022 22:56:46 +0300 Message-ID: <20220910195659.11843-3-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220910195659.11843-1-Sergey.Semin@baikalelectronics.ru> References: <20220910195659.11843-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org First of all the DW uMCTL2 DDRC IP-core supports the individual IRQ lines for each standard event: ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection, Scrubber-Done signal, DFI Parity/CRC Error. It's possible that the platform engineers merge them up in the IRQ controller level. So let's add both configuration support to the DT-schema. Secondly the DW uMCTL2 DDRC IP-core can have clock sources like APB reference clock, AXI-ports clock, main DDRC core reference clock and Scrubber low-power clock. In addition to that each clock domain can have a dedicated reset signal. Let's add the properties for at least the denoted clock sources and the corresponding reset controls. Note the IRQs and the phandles order is deliberately not fixed since some of the sources may be absent depending on the IP-core synthesize parameters and the particular platform setups. Signed-off-by: Serge Semin Reviewed-by: Rob Herring --- Changelog v2: - Replace "snps,ddrc-3.80a" compatible string with "snps,dw-umctl2-ddrc" in the example. - Move unrelated changes in to the dedicated patches. (@Krzysztof) - Use the IRQ macros in the example. (@Krzysztof) --- .../snps,dw-umctl2-ddrc.yaml | 61 ++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml index fb571d3d665d..e68c4306025a 100644 --- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml @@ -33,11 +33,55 @@ properties: const: xlnx,zynqmp-ddrc-2.40a interrupts: - maxItems: 1 + description: + DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":" + ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection, + Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the + signals merged before they reach the IRQ controller or have some of them + absent in case if the corresponding feature is unavailable/disabled. + minItems: 1 + maxItems: 5 + + interrupt-names: + minItems: 1 + maxItems: 5 + oneOf: + - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ + items: + - const: ecc + - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs + items: + enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ] reg: maxItems: 1 + clocks: + description: + A standard set of the clock sources contains CSRs bus clock, AXI-ports + reference clock, DDRC core clock, Scrubber standalone clock + (synchronous to the DDRC clock). + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + items: + enum: [ pclk, aclk, core, sbr ] + + resets: + description: + Each clock domain can have separate reset signal. + minItems: 1 + maxItems: 4 + + reset-names: + minItems: 1 + maxItems: 4 + items: + enum: [ prst, arst, core, sbr ] + required: - compatible - reg @@ -55,5 +99,20 @@ examples: interrupt-parent = <&gic>; interrupts = ; + interrupt-names = "ecc"; + }; + - | + #include + + memory-controller@3d400000 { + compatible = "snps,dw-umctl2-ddrc"; + reg = <0x3d400000 0x400000>; + + interrupts = <147 IRQ_TYPE_LEVEL_HIGH>, <148 IRQ_TYPE_LEVEL_HIGH>, + <149 IRQ_TYPE_LEVEL_HIGH>, <150 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ecc_ce", "ecc_ue", "ecc_sbr", "dfi_e"; + + clocks = <&pclk>, <&aclk>, <&core_clk>, <&sbr_clk>; + clock-names = "pclk", "aclk", "core", "sbr"; }; ... From patchwork Sat Sep 10 19:56:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 1676402 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=baikalelectronics.ru header.i=@baikalelectronics.ru header.a=rsa-sha256 header.s=mail header.b=LC9mCobY; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4MQ3Y82F38z1yhR for ; Sun, 11 Sep 2022 05:57:16 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229821AbiIJT5O (ORCPT ); Sat, 10 Sep 2022 15:57:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229754AbiIJT5K (ORCPT ); Sat, 10 Sep 2022 15:57:10 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id AD78444572; Sat, 10 Sep 2022 12:57:07 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id C66FEDB3; Sat, 10 Sep 2022 23:00:53 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com C66FEDB3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662840053; bh=wlww8ZkjN/aoPB0dmZO8MZRLajmRztrSeR5eCVXT2u0=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=LC9mCobYlQIwLTkLwmogQssLrOrtPz09GVZWYYtgcQfZWpDa8gl8nEwcex4ANb6VL 8hkpj5hdSLnmnpS1Dq4xj8nXwpLmo/6Se52uTMwEKierd7BSXrXwAMG13ae3d9keLS 2w6rQCDF1a8ZjLBtWNEINuWS8ZJA9+ZBppiLBoM4= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sat, 10 Sep 2022 22:57:02 +0300 From: Serge Semin To: Rob Herring , Krzysztof Kozlowski , Michal Simek , Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , Krzysztof Kozlowski , Manish Narani CC: Serge Semin , Serge Semin , Alexey Malahov , Michail Ivanov , Pavel Parkhomenko , Punnaiah Choudary Kalluri , Dinh Nguyen , James Morse , Robert Richter , Rob Herring , , , , , Krzysztof Kozlowski Subject: [PATCH v2 03/15] dt-bindings: memory: snps: Convert the schema to being generic Date: Sat, 10 Sep 2022 22:56:47 +0300 Message-ID: <20220910195659.11843-4-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220910195659.11843-1-Sergey.Semin@baikalelectronics.ru> References: <20220910195659.11843-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org At the current state the DW uMCTL2 DDRC DT-schema can't be used as the common one for all the IP-core-based devices due to the compatible string property constraining the list of the supported device names. In order to fix that we suggest to update the compatible property constraints so one would permit having any value aside with the generic device names. At the same time the generic DT-schema selection must be restricted to the denoted generic devices only so not to permit the generic fallback compatibles. Finally since the generic schema will be referenced from the vendor-specific DT-bindings with possibly non-standard properties defined it must permit having additional properties specified. Signed-off-by: Serge Semin --- Note alternatively we could drop the "additionalProperties" keyword modification since currently there is no actual device available with the properties not listed in the generic DT-schema. Changelog v2: - This is a new patch created on v2 cycle of the patchset. (@Krzysztof) --- .../memory-controllers/snps,dw-umctl2-ddrc.yaml | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml index e68c4306025a..a3394b4600ef 100644 --- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml @@ -21,9 +21,21 @@ description: | controller. It has an optional SEC/DEC ECC support in 64- and 32-bits bus width configurations. +# Please create a separate DT-schema for your DW uMCTL2 DDR controller +# and make sure it's assigned with the vendor-specific compatible string. +select: + properties: + compatible: + enum: + - snps,ddrc-3.80a + - snps,dw-umctl2-ddrc + - xlnx,zynqmp-ddrc-2.40a + required: + - compatible + properties: compatible: - oneOf: + anyOf: - deprecated: true description: Synopsys DW uMCTL2 DDR controller v3.80a const: snps,ddrc-3.80a @@ -31,6 +43,7 @@ properties: const: snps,dw-umctl2-ddrc - description: Xilinx ZynqMP DDR controller v2.40a const: xlnx,zynqmp-ddrc-2.40a + - {} interrupts: description: @@ -87,7 +100,7 @@ required: - reg - interrupts -additionalProperties: false +additionalProperties: true examples: - | From patchwork Sat Sep 10 19:56:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 1676406 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=baikalelectronics.ru header.i=@baikalelectronics.ru header.a=rsa-sha256 header.s=mail header.b=ohL4bbFf; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4MQ3Z25fc9z1ypB for ; Sun, 11 Sep 2022 05:58:02 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230177AbiIJT6A (ORCPT ); Sat, 10 Sep 2022 15:58:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229997AbiIJT5Z (ORCPT ); Sat, 10 Sep 2022 15:57:25 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9646246D85; Sat, 10 Sep 2022 12:57:09 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 8EB55DB9; Sat, 10 Sep 2022 23:00:54 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 8EB55DB9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662840054; bh=b4v569UoUsQ14XJS9pLHTnZU6ML40N2gkX2cC2Onuis=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=ohL4bbFfKZj9B8vlFuDylXu+bhcY5eEmakOX9SZbSkuPYFgePixCQo4WDwziKI5qq 8JvnwtbnJRnRCbAexIVZ+mNdq1gQn6lRPvrMZsGYeol25e2U/kNNNAiaZhBG2lXn95 YGXPyfiWiPaT3bqUUFmBihQSGOQMG499E6XquHDw= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sat, 10 Sep 2022 22:57:03 +0300 From: Serge Semin To: Rob Herring , Krzysztof Kozlowski , Michal Simek , Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , Krzysztof Kozlowski , Serge Semin CC: Serge Semin , Alexey Malahov , Michail Ivanov , Pavel Parkhomenko , Punnaiah Choudary Kalluri , Manish Narani , Dinh Nguyen , James Morse , Robert Richter , Rob Herring , , , , Subject: [PATCH v2 04/15] dt-bindings: memory: Add Baikal-T1 DDRC DT-schema Date: Sat, 10 Sep 2022 22:56:48 +0300 Message-ID: <20220910195659.11843-5-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220910195659.11843-1-Sergey.Semin@baikalelectronics.ru> References: <20220910195659.11843-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There are individual IRQs for each ECC and DFI events. The dedicated scrubber clock source is absent since it's fully synchronous to the core clock. In addition to that the DFI-DDR PHY CSRs can be accessed via a separate registers space. Signed-off-by: Serge Semin Reviewed-by: Rob Herring --- Changelog v2: - Keep the alphabetically ordered compatible strings list. (@Krzysztof) - Fix grammar nitpicks in the patch log. (@Krzysztof) - Drop the PHY CSR region. (@Rob) - Move the device bindings to the separate DT-schema. --- .../memory-controllers/baikal,bt1-ddrc.yaml | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml new file mode 100644 index 000000000000..a778acdd6928 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-ddrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 DDR Controller + +maintainers: + - Serge Semin + +description: + Baikal-T1 DDRC is based on the DW uMCTL2 DDRC IP-core v2.51a with DDR2 + and DDR3 protocol capability, 32-bit data bus + 8-bit ECC + up to 2 + SDRAM ranks. There are individual IRQs for each ECC and DFI events. + The dedicated scrubber clock source is absent since it's fully + synchronous to the core clock. + +allOf: + - $ref: /schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml# + +properties: + compatible: + const: baikal,bt1-ddrc + + reg: + maxItems: 1 + + interrupts: + maxItems: 4 + + interrupt-names: + items: + - const: dfi_e + - const: ecc_ce + - const: ecc_ue + - const: ecc_sbr + + clocks: + maxItems: 3 + + clock-names: + items: + - const: pclk + - const: aclk + - const: core + + resets: + maxItems: 2 + + reset-names: + items: + - const: arst + - const: core + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + memory-controller@1f042000 { + compatible = "baikal,bt1-ddrc"; + reg = <0x1f042000 0x1000>; + + interrupts = , + , + , + ; + interrupt-names = "dfi_e", "ecc_ce", "ecc_ue", "ecc_sbr"; + + clocks = <&ccu_sys CCU_SYS_APB_CLK>, + <&ccu_axi CCU_AXI_DDR_CLK>, + <&ccu_pll CCU_DDR_PLL>; + clock-names = "pclk", "aclk", "core"; + + resets = <&ccu_axi CCU_AXI_DDR_RST>, + <&ccu_sys CCU_SYS_DDR_INIT_RST>; + reset-names = "arst", "core"; + }; +...