From patchwork Wed Aug 31 15:18:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1672369 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=exLzzgDU; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MHns56Qhyz1yh5 for ; Thu, 1 Sep 2022 01:19:21 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DA889849D4; Wed, 31 Aug 2022 17:19:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="exLzzgDU"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A9DC7849B4; Wed, 31 Aug 2022 17:19:07 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3020A849CC for ; Wed, 31 Aug 2022 17:19:01 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661959141; x=1693495141; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cpFzTTK2ugNh8CqZ8aqdmxfnshV2r+jsU5ooIHA8AvE=; b=exLzzgDUplkmB6VM3gadxEDtoL4dOk32whDGH7F44tRoMI/0cgXvOpAG EcspxfOp4bMGGC2qonh1fzSRrhfGHotxTPiUim12Vm3ais2xtgDvrxt43 7wOP5obalym1HkIqeWgF1H2sjGNN1utAb9fJ4Ru7WoemnGpRrk7yrPwzS fre55pFB8ABe9F/Lb0ERvTDIl1m+LGjwuUZtT+soVsZWCxq0kcDv+8YGT lsghVzcdGtEF11cXr/xJwXdMAbg1MaBsY9CRhrZMGm7iaK/YWMfTpoNL2 dCAXTDOiA0UuBgAjnM1fefjIBYlG6n1ATErfiy5pWfUxWAM6Hk2U+y1rU w==; X-IronPort-AV: E=McAfee;i="6500,9779,10456"; a="357188611" X-IronPort-AV: E=Sophos;i="5.93,278,1654585200"; d="scan'208";a="357188611" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 08:18:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,278,1654585200"; d="scan'208";a="673392941" Received: from pglmail07.png.intel.com ([10.221.193.207]) by fmsmga008.fm.intel.com with ESMTP; 31 Aug 2022 08:18:54 -0700 Received: from localhost (pgli0117.png.intel.com [10.221.240.80]) by pglmail07.png.intel.com (Postfix) with ESMTP id F35F532E3; Wed, 31 Aug 2022 23:18:53 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id F26B03D21; Wed, 31 Aug 2022 23:18:53 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Sieu Mun Tang , Jit Loon Lim , Chee Hong Ang Subject: [PATCH 1/3] arch: arm: mach-socfpga: Add a backup copy of .data section for SoC64 SPL Date: Wed, 31 Aug 2022 23:18:50 +0800 Message-Id: <20220831151852.7494-2-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220831151852.7494-1-jit.loon.lim@intel.com> References: <20220831151852.7494-1-jit.loon.lim@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Chee Hong Ang Add a new .data section for preserving the original state of the .data section of SoC64 SPL. This new .data section is required to make SPL reentrant after warm reset. Signed-off-by: Chee Hong Ang Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/u-boot-spl-soc64.lds | 93 ++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 arch/arm/mach-socfpga/u-boot-spl-soc64.lds diff --git a/arch/arm/mach-socfpga/u-boot-spl-soc64.lds b/arch/arm/mach-socfpga/u-boot-spl-soc64.lds new file mode 100644 index 0000000000..05c441c088 --- /dev/null +++ b/arch/arm/mach-socfpga/u-boot-spl-soc64.lds @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2018 + * Intel Corporation + * + * (C) Copyright 2013 + * David Feng + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + * + * SPDX-License-Identifier: GPL-2.0 + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(_start) +SECTIONS +{ + .text : { + . = ALIGN(8); + *(.__image_copy_start) + CPUDIR/start.o (.text*) + *(.text*) + } >.sram + + .rodata : { + . = ALIGN(8); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } >.sram + + .data : { + . = ALIGN(8); + /* Run time .data section starting at this location */ + __data_start = .; + *(.data*) + /* Run time .data section ending at this location */ + __data_end = .; + } >.sram + + . = ALIGN(8); + /* Preserve original .data section starting at this location */ + __preserve_data_start = .; + . = __preserve_data_start + (__data_end - __data_start); + /* Preserve original .data section ending at this location */ + __preserve_data_end = .; + + . = ALIGN(8); + .u_boot_list . : { + KEEP(*(SORT(.u_boot_list*))); + } >.sram + + .image_copy_end : { + . = ALIGN(8); + *(.__image_copy_end) + } >.sram + + .end : { + . = ALIGN(8); + *(.__end) + } >.sram + + _image_binary_end = .; + + .bss_start (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.__bss_start)); + } >.sdram + + .bss (NOLOAD) : { + *(.bss*) + . = ALIGN(8); + } >.sdram + + .bss_end (NOLOAD) : { + KEEP(*(.__bss_end)); + } >.sdram + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} From patchwork Wed Aug 31 15:18:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1672371 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=QvdSvxjP; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MHnsX1KSkz1yh5 for ; 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Signed-off-by: Chee Hong Ang Signed-off-by: Jit Loon Lim --- configs/socfpga_agilex_defconfig | 1 + configs/socfpga_stratix10_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index e2d869610c..59dcb8da8f 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_COUNTER_FREQUENCY=400000000 CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x1000 diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 07e9f20a41..98d01f1428 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_COUNTER_FREQUENCY=400000000 CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x1000 From patchwork Wed Aug 31 15:18:52 2022 Content-Type: text/plain; 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31 Aug 2022 08:18:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,278,1654585200"; d="scan'208";a="589066489" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga006.jf.intel.com with ESMTP; 31 Aug 2022 08:18:55 -0700 Received: from localhost (pgli0117.png.intel.com [10.221.240.80]) by pglmail07.png.intel.com (Postfix) with ESMTP id E484B32E7; Wed, 31 Aug 2022 23:18:54 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id E37953D21; Wed, 31 Aug 2022 23:18:54 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Sieu Mun Tang , Jit Loon Lim , Chee Hong Ang Subject: [PATCH 3/3] arch: arm: mach-socfpga: Reload SoC64 SPL state after warm reset Date: Wed, 31 Aug 2022 23:18:52 +0800 Message-Id: <20220831151852.7494-4-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220831151852.7494-1-jit.loon.lim@intel.com> References: <20220831151852.7494-1-jit.loon.lim@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Chee Hong Ang When the system boot from cold reset, SPL will copy its .data section into this backup section to keep an original copy of .data section. When the system has been warm reset, SPL will reload the original .data section from this backup section to restore the original state of SPL. This is required to make sure SPL still run in fresh state after warm reset. Signed-off-by: Chee Hong Ang Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/lowlevel_init_soc64.S | 37 +++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S index 875927cc4d..07adf62ea8 100644 --- a/arch/arm/mach-socfpga/lowlevel_init_soc64.S +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -71,6 +71,43 @@ lowlevel_in_el1: #endif /* CONFIG_ARMV8_MULTIENTRY */ 2: + +#ifdef CONFIG_SPL_BUILD + branch_if_slave x0, 3f + + /* Check rstmgr.stat for warm reset status */ + ldr x1, =SOCFPGA_RSTMGR_ADDRESS + ldr x0, [x1] + /* Check whether any L4 watchdogs or MPUs had triggered warm reset */ + ldr x2, =0x000F0F00 + ands x0, x0, x2 + /* + * If current Reset Manager's status is warm reset just reload the + * .data section by copying the data from data preserve section. + * Otherwise, copy the .data section to the data preserve section to + * keep an original copy of .data section. This ensure SPL is + * reentrant after warm reset. + */ + b.ne reload_data_section + /* Copy from .data to preserved .data to backup the SPL state */ + ldr x0, =__data_start + ldr x1, =__preserve_data_start + ldr x2, =__preserve_data_end + b copy_loop +reload_data_section: + /* Copy from preserved .data to .data to restore the SPL state */ + ldr x0, =__preserve_data_start + ldr x1, =__data_start + ldr x2, =__data_end +copy_loop: + ldr w3, [x0] + add x0, x0, #4 + str w3, [x1] + add x1, x1, #4 + cmp x1, x2 + b.ne copy_loop +3: +#endif mov lr, x29 /* Restore LR */ ret ENDPROC(lowlevel_init)