From patchwork Wed Aug 31 11:20:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1672302 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=FL8A6mZl; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MHhZp3Yqwz1yhy for ; Wed, 31 Aug 2022 21:21:38 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8B6C1849AC; Wed, 31 Aug 2022 13:21:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="FL8A6mZl"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A7087849C0; Wed, 31 Aug 2022 13:21:34 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A954184997 for ; Wed, 31 Aug 2022 13:21:31 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661944891; x=1693480891; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MaaAYmyA/Rt5BKnLEubpaMq5EhEmjztx2NGIr7T8O5w=; b=FL8A6mZluS3UUVMJwfZMuNAStgyiSXmV4833AMLNK2Vgdbw8y0LnLThs xFeKrVOuxAdbMOx5vLMDFfaIfTE42d2wxQT4zjHCQ7B8VHUNdmQitqdQ4 EM/Nnw6wIGr679z5KD9pSIhgIPmoQOZCmJYQoNCj8EDdy1gGwYq/F7LF6 bHSP39jzie+YnQqwgfnMsDSkv4XOG4IAs3gSuObCDISWrY0qcWs27gNrk xzrAKKPsZhWGwiERHMUU0TCM4SWO1rF9KB30qmBmp6kIEh6ypbaBEuG+i 2z/cDPW4zfdMhDvQWopVdcYVgj7ru+kWOOoPpzkhmrEHs6WckPCJ08Ngu w==; X-IronPort-AV: E=McAfee;i="6500,9779,10455"; a="275827754" X-IronPort-AV: E=Sophos;i="5.93,277,1654585200"; d="scan'208";a="275827754" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 04:20:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,277,1654585200"; d="scan'208";a="754393586" Received: from pglmail07.png.intel.com ([10.221.193.207]) by fmsmga001.fm.intel.com with ESMTP; 31 Aug 2022 04:20:47 -0700 Received: from localhost (pgli0117.png.intel.com [10.221.240.80]) by pglmail07.png.intel.com (Postfix) with ESMTP id A571B32E3; Wed, 31 Aug 2022 19:20:46 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id A44423D51; Wed, 31 Aug 2022 19:20:46 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Sieu Mun Tang , Jit Loon Lim , Chee Hong Ang Subject: [PATCH 1/2] arm: socfpga: soc64: Enable L2 reset on S10 Date: Wed, 31 Aug 2022 19:20:43 +0800 Message-Id: <20220831112044.25371-2-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220831112044.25371-1-jit.loon.lim@intel.com> References: <20220831112044.25371-1-jit.loon.lim@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Chee Hong Ang Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes the magic word into system manager's scratch register to indicate the system has performed L2 reset and request reset manager to perform hardware handshake and then trigger L2 reset. CPU0 put itself into WFI mode. L2 reset will reboot all HPS CPU cores after which all HPS cores are in WFI mode. L2 reset is followed by warm reset request by SPL via RMR_EL3 system register. To trigger L2 + warm reset under u-boot, set 'reset=warm' in the u-boot environment then input 'reset' command in the u-boot command prompt. Signed-off-by: Chee Hong Ang Signed-off-by: Jit Loon Lim --- .../include/mach/reset_manager_soc64.h | 1 + drivers/sysreset/sysreset_socfpga_soc64.c | 58 ++++++++++++++++++- include/configs/socfpga_soc64_common.h | 7 +++ 3 files changed, 64 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index c8bb727aa2..2af6598998 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -10,6 +10,7 @@ void reset_deassert_peripherals_handoff(void); int cpu_has_been_warmreset(void); void print_reset_info(void); void socfpga_bridges_reset(int enable); +void l2_reset_cpu(void); #define RSTMGR_SOC64_STATUS 0x00 #define RSTMGR_SOC64_MPUMODRST 0x20 diff --git a/drivers/sysreset/sysreset_socfpga_soc64.c b/drivers/sysreset/sysreset_socfpga_soc64.c index 9837aadf64..15d8c8a7a0 100644 --- a/drivers/sysreset/sysreset_socfpga_soc64.c +++ b/drivers/sysreset/sysreset_socfpga_soc64.c @@ -5,19 +5,73 @@ */ #include +#include +#include #include #include #include #include +#include +#include static int socfpga_sysreset_request(struct udevice *dev, enum sysreset_t type) { - puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); - mbox_reset_cold(); +#ifndef CONFIG_SPL_BUILD + const char *reset = env_get("reset"); + + if (reset && !strcmp(reset, "warm")) { + /* flush dcache */ + flush_dcache_all(); + + /* request a warm reset */ + puts("Do warm reset now...\n"); + l2_reset_cpu(); + } else { +#endif + puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); + mbox_reset_cold(); +#ifndef CONFIG_SPL_BUILD + } +#endif + return -EINPROGRESS; } +void l2_reset_cpu(void) +{ + asm volatile( + "str %0, [%1]\n" + /* Increase timeout in rstmgr.hdsktimeout */ + "ldr x2, =0xFFFFFF\n" + "str w2, [%2, #0x64]\n" + "ldr w2, [%2, #0x10]\n" + /* + * Set l2flushen = 1, etrstallen = 1, + * fpgahsen = 1 and sdrselfrefen = 1 + * in rstmgr.hdsken to perform handshake + * in certain peripherals before trigger + * L2 reset. + */ + "ldr x3, =0x10D\n" + "orr x2, x2, x3\n" + "str w2, [%2, #0x10]\n" + /* Trigger L2 reset in rstmgr.coldmodrst */ + "ldr w2, [%2, #0x34]\n" + "orr x2, x2, #0x100\n" + "isb\n" + "dsb sy\n" + "str w2, [%2, #0x34]\n" + /* Put all cores into WFI mode */ + "wfi_loop:\n" + " wfi\n" + " b wfi_loop\n" + : : "r" (L2_RESET_DONE_STATUS), + "r" (L2_RESET_DONE_REG), + "r" (SOCFPGA_RSTMGR_ADDRESS) + : "x1", "x2", "x3"); +} + static struct sysreset_ops socfpga_sysreset = { .request = socfpga_sysreset_request, }; diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 06198ddd82..74c88ee2a2 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -16,6 +16,13 @@ */ /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ #define CPU_RELEASE_ADDR 0xFFD12210 +/* + * Share sysmgr.boot_scratch_cold6 & 7 (64bit) with VBAR_LE3_BASE_ADDR + * Indicate L2 reset is done. HPS should trigger warm reset via RMR_EL3. + */ +#define L2_RESET_DONE_REG 0xFFD12218 +/* Magic word to indicate L2 reset is completed */ +#define L2_RESET_DONE_STATUS 0x1228E5E7 /* * U-Boot console configurations From patchwork Wed Aug 31 11:20:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1672301 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=lHvJFC+z; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MHhZ65nZMz1yhy for ; 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31 Aug 2022 04:20:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,277,1654585200"; d="scan'208";a="857433636" Received: from pglmail07.png.intel.com ([10.221.193.207]) by fmsmga006.fm.intel.com with ESMTP; 31 Aug 2022 04:20:49 -0700 Received: from localhost (pgli0117.png.intel.com [10.221.240.80]) by pglmail07.png.intel.com (Postfix) with ESMTP id C49FC32E2; Wed, 31 Aug 2022 19:20:48 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id C35E03D51; Wed, 31 Aug 2022 19:20:48 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Sieu Mun Tang , Jit Loon Lim , Chee Hong Ang Subject: [PATCH 2/2] arm: socfpga: soc64: Perform warm reset after L2 reset in SPL on S10 Date: Wed, 31 Aug 2022 19:20:44 +0800 Message-Id: <20220831112044.25371-3-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220831112044.25371-1-jit.loon.lim@intel.com> References: <20220831112044.25371-1-jit.loon.lim@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Chee Hong Ang SPL checks for magic word in system manager's scratch register to find out whether the system has performed L2 reset. If L2 reset was performed, SPL put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) requests warm reset via RMR_EL3 system register and put itself into WFI mode. Firmware will get the warm reset request from HPS and perform the warm reset sequence to reboot all the HPS cores. Signed-off-by: Chee Hong Ang Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/lowlevel_init_soc64.S | 24 +++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S index 875927cc4d..1fd0a50b3a 100644 --- a/arch/arm/mach-socfpga/lowlevel_init_soc64.S +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -12,6 +12,30 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */ +#ifdef CONFIG_SPL_BUILD + /* Check for L2 reset magic word */ + ldr x4, =L2_RESET_DONE_REG + ldr x5, [x4] + ldr x1, =L2_RESET_DONE_STATUS + cmp x1, x5 + /* No L2 reset, skip warm reset */ + b.ne skipwarmreset + /* L2 reset completed */ + str xzr, [x4] + /* Put all slaves CPUs into WFI mode */ + branch_if_slave x0, put_cpu_in_wfi + /* Master CPU (CPU0) request for warm reset */ + mrs x1, rmr_el3 + orr x1, x1, #0x02 + msr rmr_el3, x1 + isb + dsb sy +put_cpu_in_wfi: + wfi + b put_cpu_in_wfi +skipwarmreset: +#endif + #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) wait_for_atf: