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Thu, 25 Aug 2022 09:15:03 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3668F100034; Thu, 25 Aug 2022 09:15:01 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9D12021513E; Thu, 25 Aug 2022 09:15:01 +0200 (CEST) Received: from localhost (10.75.127.117) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2308.20; Thu, 25 Aug 2022 09:15:01 +0200 From: Patrice Chotard To: CC: Patrice CHOTARD , Patrick DELAUNAY , U-Boot STM32 , Grzegorz Szymaszek Subject: [PATCH v2] configs: stih410-b2260: Fix SYS_HZ_CLOCK value Date: Thu, 25 Aug 2022 09:14:57 +0200 Message-ID: <20220825071457.1136386-1-patrice.chotard@foss.st.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.75.127.117] X-ClientProxiedBy: GPXDAG2NODE4.st.com (10.75.127.68) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-25_03,2022-08-22_02,2022-06-22_01 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean SYS_HZ_CLOCK was wrongly set to 1GHz whereas it's set to 750MHz by default by bootrom. Signed-off-by: Patrice Chotard Reviewed-by: Grzegorz Szymaszek --- Changes in v2: - Replace 1MHz by 1GHz in commit description include/configs/stih410-b2260.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index b1a011bacb..1e966a2322 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -14,7 +14,7 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x3E000000 -#define CONFIG_SYS_HZ_CLOCK 1000000000 /* 1 GHz */ +#define CONFIG_SYS_HZ_CLOCK 750000000 /* 750 MHz */ /* Environment */