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([171.76.87.159]) by smtp.gmail.com with ESMTPSA id g5-20020a170902d1c500b0016eea511f2dsm13318881plb.242.2022.08.24.21.52.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Aug 2022 21:52:29 -0700 (PDT) From: Anup Patel To: Atish Patra , Alistair Francis Cc: Anup Patel , opensbi@lists.infradead.org, Anup Patel , Andrew Jones Subject: [PATCH 1/7] lib: sbi_pmu: Remove "event_idx" member from struct sbi_pmu_fw_event Date: Thu, 25 Aug 2022 10:21:38 +0530 Message-Id: <20220825045144.752619-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220825045144.752619-1-apatel@ventanamicro.com> References: <20220825045144.752619-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220824_215231_646563_4249A302 X-CRM114-Status: UNSURE ( 7.62 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The "event_idx" member of struct sbi_pmu_fw_event is not used anywhere so let us remove it. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- lib/sbi/sbi_pmu.c | 3 --- 1 file changed, 3 deletions(-) Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:429 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The "event_idx" member of struct sbi_pmu_fw_event is not used anywhere so let us remove it. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- lib/sbi/sbi_pmu.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 5a294a2..535e5cc 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -35,9 +35,6 @@ struct sbi_pmu_hw_event { /** Representation of a firmware event */ struct sbi_pmu_fw_event { - /* Event associated with the particular counter */ - uint32_t event_idx; - /* Current value of the counter */ unsigned long curr_count; From patchwork Thu Aug 25 04:51:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1670052 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=IGjQ8Lzy; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=HbAzVhbP; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MCrGD2fK7z1ygV for ; Thu, 25 Aug 2022 14:53:56 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3YTA4ADyDW4SFQys0ByUUGmHBhOF3miVO50ALYsC/ZU=; b=IGjQ8LzyE7Mcah hmG+Wqr7Wpp+FHfXZMqPi85PAQ1+ri5sYdlVwJSljBdvcSmP3UkuLyeW73iwQM21pSsy/QkUMxJQl BCSwnH6BysfRnxsdZ40ScVFdRz/LWESAezDGenGJTSzRaPIX7YulHBCE1q8lamGit9F69Ze1rMH86 oJulTmsfSijBcPJzIQ0CEsfsQPfBDqo9HkBDiboRoGwLNWqRZ6OcFGzkLadxcLIBNqPNjMsZ0PjlG PYh1Ndcp9W5WTwXNrAkgxFdhCWer20qZe/o+dkmmDS60PyY5Qovr7+L4l1R0g6EbAZowalff02zq/ cSxk4q8LWENDoeivN/0Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oR4rA-006rCq-38; Thu, 25 Aug 2022 04:52:40 +0000 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oR4r4-006r9F-5g for opensbi@lists.infradead.org; Thu, 25 Aug 2022 04:52:38 +0000 Received: by mail-pj1-x102a.google.com with SMTP id x14-20020a17090a8a8e00b001fb61a71d99so3733581pjn.2 for ; Wed, 24 Aug 2022 21:52:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=vVdv96j2elz6GGb02sVBag3vO2sZHiA94ACC9OCACIA=; b=HbAzVhbPrUJaqvj69cMZXGn51EZ5uR4yXugEZ1+XvBD5OSmEJG5cXkcF9noVhWLuuq s9UCvhhYXK57Y2BWRMzQgEjNOHMAyp22u1ZuuN1gDlPnu/KafqBcNFR3q85keODVvO9w PVwEIABGqXepOaW2g6o+Y+4MghPugR1dd94kjEtzPnS5mG1iakFZY9Ix+nEN3dbNMK9R 50WVrZoXTkjZfFgnUTY/yCp1d7v6GBjUQQxCmhggnffScU+4zSQkSQIto8xdigbuy+aV psJi+bByFWz5I1WGgQ9C2PZZsXGQ58b3w9FX4CbI3AmoJillHcXgiLohfEgIT8geN7i4 lwOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=vVdv96j2elz6GGb02sVBag3vO2sZHiA94ACC9OCACIA=; b=XwdQ26IQm6jmp0tgQ4+szYX+v070LwrCQha0ftfcZ25pIrY/1t6r1KbXulUzL1tr+a tINg6lC3WqpCbhamejfmpZEEIbVi4nyCRrfcpj5yPdjwjfbiiMe2gf1wKWI4TQUuIzjs p17ewD7X3ji2VamsHjUob0ywvGOjyzI4aos6ZRXd6JH8FWuHz7BibW1v7zsimTU7TrP/ MkFO6lkFE4ZMSDDmNYyDk4Q2R1rM03UY/0kEkDn+iKFaeni5Ms66pBIb1BWt5G7g5mOv EkrPX0DcFrNpGeYh/+Tlq63tiXiYcXMus4qD6JLA5y7HWKyvFLgcxGhJGSQCuX1Ls0fQ 3AVQ== X-Gm-Message-State: ACgBeo1EBMVDXuEirKHNHZz3vaPyIebxTn3J9Nn4l2/DIgUvop1O2Z+S D5Gm7+EBxjFSVv9TkKTtvOzqpA== X-Google-Smtp-Source: AA6agR7BQ/5vXT86+tk+MbZxf7HkfRg08wt86UfLak5WfBZz9mervMiBzTR1cbVMdJ7lDcAfQ8wJlQ== X-Received: by 2002:a17:90a:9907:b0:1f5:2318:ea6d with SMTP id b7-20020a17090a990700b001f52318ea6dmr2686054pjp.163.1661403152833; Wed, 24 Aug 2022 21:52:32 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.87.159]) by smtp.gmail.com with ESMTPSA id g5-20020a170902d1c500b0016eea511f2dsm13318881plb.242.2022.08.24.21.52.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Aug 2022 21:52:32 -0700 (PDT) From: Anup Patel To: Atish Patra , Alistair Francis Cc: Anup Patel , opensbi@lists.infradead.org, Anup Patel , Andrew Jones Subject: [PATCH 2/7] lib: sbi_pmu: Replace sbi_pmu_ctr_read() with sbi_pmu_ctr_fw_read() Date: Thu, 25 Aug 2022 10:21:39 +0530 Message-Id: <20220825045144.752619-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220825045144.752619-1-apatel@ventanamicro.com> References: <20220825045144.752619-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220824_215234_230542_D888EC61 X-CRM114-Status: GOOD ( 12.40 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The "read a firmware counter" SBI call should only work for firmware counters so let us replace sbi_pmu_ctr_read() with sbi_pmu_ctr_fw_read() which works only on firmware counters. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- include/sbi/sbi_pmu.h | 2 +- lib/sbi/sbi_ecall_pmu.c | 3 ++- lib/sbi/sbi_pmu.c | 45 +++++++- [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:102a listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The "read a firmware counter" SBI call should only work for firmware counters so let us replace sbi_pmu_ctr_read() with sbi_pmu_ctr_fw_read() which works only on firmware counters. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- include/sbi/sbi_pmu.h | 2 +- lib/sbi/sbi_ecall_pmu.c | 3 ++- lib/sbi/sbi_pmu.c | 45 +++++++---------------------------------- 3 files changed, 10 insertions(+), 40 deletions(-) diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h index f5e3dbd..34336f7 100644 --- a/include/sbi/sbi_pmu.h +++ b/include/sbi/sbi_pmu.h @@ -53,7 +53,7 @@ int sbi_pmu_add_hw_event_counter_map(u32 eidx_start, u32 eidx_end, u32 cmap); int sbi_pmu_add_raw_event_counter_map(uint64_t select, uint64_t select_mask, u32 cmap); -int sbi_pmu_ctr_read(uint32_t cidx, unsigned long *cval); +int sbi_pmu_ctr_fw_read(uint32_t cidx, uint64_t *cval); int sbi_pmu_ctr_stop(unsigned long cidx_base, unsigned long cidx_mask, unsigned long flag); diff --git a/lib/sbi/sbi_ecall_pmu.c b/lib/sbi/sbi_ecall_pmu.c index 9ee9e81..826c8a8 100644 --- a/lib/sbi/sbi_ecall_pmu.c +++ b/lib/sbi/sbi_ecall_pmu.c @@ -51,7 +51,8 @@ static int sbi_ecall_pmu_handler(unsigned long extid, unsigned long funcid, break; case SBI_EXT_PMU_COUNTER_FW_READ: - ret = sbi_pmu_ctr_read(regs->a0, out_val); + ret = sbi_pmu_ctr_fw_read(regs->a0, &temp); + *out_val = temp; break; case SBI_EXT_PMU_COUNTER_START: diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 535e5cc..250808e 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -167,50 +167,19 @@ static int pmu_ctr_validate(uint32_t cidx, uint32_t *event_idx_code) return event_idx_type; } -static int pmu_ctr_read_fw(uint32_t cidx, unsigned long *cval, - uint32_t fw_evt_code) -{ - u32 hartid = current_hartid(); - struct sbi_pmu_fw_event fevent; - - fevent = fw_event_map[hartid][fw_evt_code]; - *cval = fevent.curr_count; - - return 0; -} - -/* Add a hardware counter read for completeness for future purpose */ -static int pmu_ctr_read_hw(uint32_t cidx, uint64_t *cval) -{ - /* Check for invalid hw counter read requests */ - if (unlikely(cidx == 1)) - return SBI_EINVAL; -#if __riscv_xlen == 32 - uint32_t temp, temph = 0; - - temp = csr_read_num(CSR_MCYCLE + cidx); - temph = csr_read_num(CSR_MCYCLEH + cidx); - *cval = ((uint64_t)temph << 32) | temp; -#else - *cval = csr_read_num(CSR_MCYCLE + cidx); -#endif - - return 0; -} - -int sbi_pmu_ctr_read(uint32_t cidx, unsigned long *cval) +int sbi_pmu_ctr_fw_read(uint32_t cidx, uint64_t *cval) { int event_idx_type; uint32_t event_code; - uint64_t cval64; + u32 hartid = current_hartid(); + struct sbi_pmu_fw_event *fevent; event_idx_type = pmu_ctr_validate(cidx, &event_code); - if (event_idx_type < 0) + if (event_idx_type != SBI_PMU_EVENT_TYPE_FW) return SBI_EINVAL; - else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW) - pmu_ctr_read_fw(cidx, cval, event_code); - else - pmu_ctr_read_hw(cidx, &cval64); + + fevent = &fw_event_map[hartid][event_code]; + *cval = fevent->curr_count; return 0; } From patchwork Thu Aug 25 04:51:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1670049 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: As-per SBI specification, all firmware counters are always 64 bits wide so let us update the SBI PMU implementation to reflect this fact. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- lib/sbi/sbi_pmu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:52e listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org As-per SBI specification, all firmware counters are always 64 bits wide so let us update the SBI PMU implementation to reflect this fact. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- lib/sbi/sbi_pmu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 250808e..1c01d34 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -36,7 +36,7 @@ struct sbi_pmu_hw_event { /** Representation of a firmware event */ struct sbi_pmu_fw_event { /* Current value of the counter */ - unsigned long curr_count; + uint64_t curr_count; /* A flag indicating pmu event monitoring is started */ bool bStarted; @@ -719,8 +719,8 @@ int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info) } else { /* it's a firmware counter */ cinfo.type = SBI_PMU_CTR_TYPE_FW; - /* Firmware counters are XLEN bits wide */ - cinfo.width = BITS_PER_LONG - 1; + /* Firmware counters are always 64 bits wide */ + cinfo.width = 63; } *ctr_info = cinfo.value; From patchwork Thu Aug 25 04:51:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1670047 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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([171.76.87.159]) by smtp.gmail.com with ESMTPSA id g5-20020a170902d1c500b0016eea511f2dsm13318881plb.242.2022.08.24.21.52.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Aug 2022 21:52:38 -0700 (PDT) From: Anup Patel To: Atish Patra , Alistair Francis Cc: Anup Patel , opensbi@lists.infradead.org, Anup Patel , Andrew Jones Subject: [PATCH 4/7] lib: sbi_pmu: Simplify FW counters to reduce memory usage Date: Thu, 25 Aug 2022 10:21:41 +0530 Message-Id: <20220825045144.752619-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220825045144.752619-1-apatel@ventanamicro.com> References: <20220825045144.752619-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220824_215241_046803_C804B955 X-CRM114-Status: GOOD ( 18.73 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Currently, we have 32 elements (i.e. SBI_PMU_FW_EVENT_MAX) array of "struct sbi_pmu_fw_event" for each of 128 possible HARTs (i.e. SBI_HARTMASK_MAX_BITS). To reduce memory usage of OpenSBI, we update FW counter implementation as follows: 1) Remove SBI_PMU_FW_EVENT_MAX 2) Remove "struct sbi_pmu_fw_event" 3) Create per-HART bitmap of XLEN bits to track FW [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:530 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Currently, we have 32 elements (i.e. SBI_PMU_FW_EVENT_MAX) array of "struct sbi_pmu_fw_event" for each of 128 possible HARTs (i.e. SBI_HARTMASK_MAX_BITS). To reduce memory usage of OpenSBI, we update FW counter implementation as follows: 1) Remove SBI_PMU_FW_EVENT_MAX 2) Remove "struct sbi_pmu_fw_event" 3) Create per-HART bitmap of XLEN bits to track FW counters which are started on each HART 4) Create per-HART uint64_t array to track values of FW counters on each HART. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- include/sbi/sbi_pmu.h | 3 -- lib/sbi/sbi_pmu.c | 78 ++++++++++++++++++++----------------------- 2 files changed, 36 insertions(+), 45 deletions(-) diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h index 34336f7..39cf007 100644 --- a/include/sbi/sbi_pmu.h +++ b/include/sbi/sbi_pmu.h @@ -19,9 +19,6 @@ /* Maximum number of hardware events that can mapped by OpenSBI */ #define SBI_PMU_HW_EVENT_MAX 256 -/* Maximum number of firmware events that can mapped by OpenSBI */ -#define SBI_PMU_FW_EVENT_MAX 32 - /* Counter related macros */ #define SBI_PMU_FW_CTR_MAX 16 #define SBI_PMU_HW_CTR_MAX 32 diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 1c01d34..26c9406 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -33,15 +33,6 @@ struct sbi_pmu_hw_event { uint64_t select_mask; }; -/** Representation of a firmware event */ -struct sbi_pmu_fw_event { - /* Current value of the counter */ - uint64_t curr_count; - - /* A flag indicating pmu event monitoring is started */ - bool bStarted; -}; - /* Information about PMU counters as per SBI specification */ union sbi_pmu_ctr_info { unsigned long value; @@ -63,8 +54,14 @@ static struct sbi_pmu_hw_event hw_event_map[SBI_PMU_HW_EVENT_MAX] = {0}; /* counter to enabled event mapping */ static uint32_t active_events[SBI_HARTMASK_MAX_BITS][SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX]; -/* Contains all the information about firmwares events */ -static struct sbi_pmu_fw_event fw_event_map[SBI_HARTMASK_MAX_BITS][SBI_PMU_FW_EVENT_MAX] = {0}; +/* Bitmap of firmware counters started on each HART */ +#if SBI_PMU_FW_CTR_MAX >= BITS_PER_LONG +#error "Can't handle firmware counters beyond BITS_PER_LONG" +#endif +static unsigned long fw_counters_started[SBI_HARTMASK_MAX_BITS]; + +/* Values of firmwares counters on each HART */ +static uint64_t fw_counters_value[SBI_HARTMASK_MAX_BITS][SBI_PMU_FW_CTR_MAX] = {0}; /* Maximum number of hardware events available */ static uint32_t num_hw_events; @@ -172,14 +169,12 @@ int sbi_pmu_ctr_fw_read(uint32_t cidx, uint64_t *cval) int event_idx_type; uint32_t event_code; u32 hartid = current_hartid(); - struct sbi_pmu_fw_event *fevent; event_idx_type = pmu_ctr_validate(cidx, &event_code); if (event_idx_type != SBI_PMU_EVENT_TYPE_FW) return SBI_EINVAL; - fevent = &fw_event_map[hartid][event_code]; - *cval = fevent->curr_count; + *cval = fw_counters_value[hartid][cidx - num_hw_ctrs]; return 0; } @@ -333,16 +328,13 @@ skip_inhibit_update: return 0; } -static int pmu_ctr_start_fw(uint32_t cidx, uint32_t fw_evt_code, - uint64_t ival, bool ival_update) +static int pmu_ctr_start_fw(uint32_t cidx, uint64_t ival, bool ival_update) { u32 hartid = current_hartid(); - struct sbi_pmu_fw_event *fevent; - fevent = &fw_event_map[hartid][fw_evt_code]; if (ival_update) - fevent->curr_count = ival; - fevent->bStarted = TRUE; + fw_counters_value[hartid][cidx - num_hw_ctrs] = ival; + fw_counters_started[hartid] |= BIT(cidx - num_hw_ctrs); return 0; } @@ -369,7 +361,7 @@ int sbi_pmu_ctr_start(unsigned long cbase, unsigned long cmask, /* Continue the start operation for other counters */ continue; else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW) - ret = pmu_ctr_start_fw(cidx, event_code, ival, bUpdate); + ret = pmu_ctr_start_fw(cidx, ival, bUpdate); else ret = pmu_ctr_start_hw(cidx, ival, bUpdate); } @@ -399,11 +391,9 @@ static int pmu_ctr_stop_hw(uint32_t cidx) return SBI_EALREADY_STOPPED; } -static int pmu_ctr_stop_fw(uint32_t cidx, uint32_t fw_evt_code) +static int pmu_ctr_stop_fw(uint32_t cidx) { - u32 hartid = current_hartid(); - - fw_event_map[hartid][fw_evt_code].bStarted = FALSE; + fw_counters_started[current_hartid()] &= ~BIT(cidx - num_hw_ctrs); return 0; } @@ -444,7 +434,7 @@ int sbi_pmu_ctr_stop(unsigned long cbase, unsigned long cmask, continue; else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW) - ret = pmu_ctr_stop_fw(cidx, event_code); + ret = pmu_ctr_stop_fw(cidx); else ret = pmu_ctr_stop_hw(cidx); @@ -624,8 +614,6 @@ int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask, int ctr_idx = SBI_ENOTSUPP; u32 hartid = current_hartid(); int event_type; - struct sbi_pmu_fw_event *fevent; - uint32_t fw_evt_code; /* Do a basic sanity check of counter base & mask */ if ((cidx_base + sbi_fls(cidx_mask)) >= total_ctrs) @@ -665,30 +653,36 @@ skip_match: if (flags & SBI_PMU_CFG_FLAG_AUTO_START) pmu_ctr_start_hw(ctr_idx, 0, false); } else if (event_type == SBI_PMU_EVENT_TYPE_FW) { - fw_evt_code = get_cidx_code(event_idx); - fevent = &fw_event_map[hartid][fw_evt_code]; if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE) - fevent->curr_count = 0; + fw_counters_value[hartid][ctr_idx - num_hw_ctrs] = 0; if (flags & SBI_PMU_CFG_FLAG_AUTO_START) - fevent->bStarted = TRUE; + fw_counters_started[hartid] |= BIT(ctr_idx - num_hw_ctrs); } return ctr_idx; } -inline int sbi_pmu_ctr_incr_fw(enum sbi_pmu_fw_event_code_id fw_id) +int sbi_pmu_ctr_incr_fw(enum sbi_pmu_fw_event_code_id fw_id) { - u32 hartid = current_hartid(); - struct sbi_pmu_fw_event *fevent; + u32 cidx, hartid = current_hartid(); + uint64_t *fcounter = NULL; + + if (likely(!fw_counters_started[hartid])) + return 0; if (unlikely(fw_id >= SBI_PMU_FW_MAX)) return SBI_EINVAL; - fevent = &fw_event_map[hartid][fw_id]; + for (cidx = num_hw_ctrs; cidx < total_ctrs; cidx++) { + if (get_cidx_code(active_events[hartid][cidx]) == fw_id && + (fw_counters_started[hartid] & BIT(cidx - num_hw_ctrs))) { + fcounter = &fw_counters_value[hartid][cidx - num_hw_ctrs]; + break; + } + } - /* PMU counters will be only enabled during performance debugging */ - if (unlikely(fevent->bStarted)) - fevent->curr_count++; + if (fcounter) + (*fcounter)++; return 0; } @@ -735,9 +729,9 @@ static void pmu_reset_event_map(u32 hartid) /* Initialize the counter to event mapping table */ for (j = 3; j < total_ctrs; j++) active_events[hartid][j] = SBI_PMU_EVENT_IDX_INVALID; - for (j = 0; j < SBI_PMU_FW_EVENT_MAX; j++) - sbi_memset(&fw_event_map[hartid][j], 0, - sizeof(struct sbi_pmu_fw_event)); + for (j = 0; j < SBI_PMU_FW_CTR_MAX; j++) + fw_counters_value[hartid][j] = 0; + fw_counters_started[hartid] = 0; } void sbi_pmu_exit(struct sbi_scratch *scratch) From patchwork Thu Aug 25 04:51:42 2022 Content-Type: text/plain; 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([171.76.87.159]) by smtp.gmail.com with ESMTPSA id g5-20020a170902d1c500b0016eea511f2dsm13318881plb.242.2022.08.24.21.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Aug 2022 21:52:41 -0700 (PDT) From: Anup Patel To: Atish Patra , Alistair Francis Cc: Anup Patel , opensbi@lists.infradead.org, Anup Patel Subject: [PATCH 5/7] lib: sbi_pmu: Add custom PMU device operations Date: Thu, 25 Aug 2022 10:21:42 +0530 Message-Id: <20220825045144.752619-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220825045144.752619-1-apatel@ventanamicro.com> References: <20220825045144.752619-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220824_215243_674019_D695F226 X-CRM114-Status: GOOD ( 19.24 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: We extend SBI PMU implementation to allow custom PMU device operations which a platform can use for platform specific quirks. The custom PMU device operations added by this patch include: 1) Operations to allow a platform implement custom firmware events. These custom firmware events can be SBI vendor extension related event [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1034 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org We extend SBI PMU implementation to allow custom PMU device operations which a platform can use for platform specific quirks. The custom PMU device operations added by this patch include: 1) Operations to allow a platform implement custom firmware events. These custom firmware events can be SBI vendor extension related events or platform specific per-HART events are not possible to count through HPM CSRs. 2) Operations to allow a platform implement custom way for enabling (or disabling) an overflow interrupt (e.g. T-Head C9xx). Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- include/sbi/sbi_pmu.h | 57 ++++++++++++++++++++++ lib/sbi/sbi_pmu.c | 108 ++++++++++++++++++++++++++++++++++-------- 2 files changed, 144 insertions(+), 21 deletions(-) diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h index 39cf007..d787575 100644 --- a/include/sbi/sbi_pmu.h +++ b/include/sbi/sbi_pmu.h @@ -25,6 +25,63 @@ #define SBI_PMU_CTR_MAX (SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX) #define SBI_PMU_FIXED_CTR_MASK 0x07 +struct sbi_pmu_device { + /** Name of the PMU platform device */ + char name[32]; + + /** + * Validate event code of custom firmware event + * Note: SBI_PMU_FW_MAX <= event_idx_code + */ + int (*fw_event_validate_code)(uint32_t event_idx_code); + + /** + * Match custom firmware counter with custom firmware event + * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX + */ + bool (*fw_counter_match_code)(uint32_t counter_index, + uint32_t event_idx_code); + + /** + * Read value of custom firmware counter + * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX + */ + uint64_t (*fw_counter_read_value)(uint32_t counter_index); + + /** + * Start custom firmware counter + * Note: SBI_PMU_FW_MAX <= event_idx_code + * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX + */ + int (*fw_counter_start)(uint32_t counter_index, + uint32_t event_idx_code, + uint64_t init_val, bool init_val_update); + + /** + * Stop custom firmware counter + * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX + */ + int (*fw_counter_stop)(uint32_t counter_index); + + /** + * Custom enable irq for hardware counter + * Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX + */ + void (*hw_counter_enable_irq)(uint32_t counter_index); + + /** + * Custom disable irq for hardware counter + * Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX + */ + void (*hw_counter_disable_irq)(uint32_t counter_index); +}; + +/** Get the PMU platform device */ +const struct sbi_pmu_device *sbi_pmu_get_device(void); + +/** Set the PMU platform device */ +void sbi_pmu_set_device(const struct sbi_pmu_device *dev); + /** Initialize PMU */ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot); diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 26c9406..87e1ff8 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -48,6 +48,9 @@ union sbi_pmu_ctr_info { }; }; +/* Platform specific PMU device */ +static const struct sbi_pmu_device *pmu_dev = NULL; + /* Mapping between event range and possible counters */ static struct sbi_pmu_hw_event hw_event_map[SBI_PMU_HW_EVENT_MAX] = {0}; @@ -113,7 +116,11 @@ static int pmu_event_validate(unsigned long event_idx) event_idx_code_max = SBI_PMU_HW_GENERAL_MAX; break; case SBI_PMU_EVENT_TYPE_FW: - event_idx_code_max = SBI_PMU_FW_MAX; + if (SBI_PMU_FW_MAX <= event_idx_code && + pmu_dev && pmu_dev->fw_event_validate_code) + return pmu_dev->fw_event_validate_code(event_idx_code); + else + event_idx_code_max = SBI_PMU_FW_MAX; break; case SBI_PMU_EVENT_TYPE_HW_CACHE: cache_ops_result = event_idx_code & @@ -174,6 +181,11 @@ int sbi_pmu_ctr_fw_read(uint32_t cidx, uint64_t *cval) if (event_idx_type != SBI_PMU_EVENT_TYPE_FW) return SBI_EINVAL; + if (SBI_PMU_FW_MAX <= event_code && + pmu_dev && pmu_dev->fw_counter_read_value) + fw_counters_value[hartid][cidx - num_hw_ctrs] = + pmu_dev->fw_counter_read_value(cidx - num_hw_ctrs); + *cval = fw_counters_value[hartid][cidx - num_hw_ctrs]; return 0; @@ -319,6 +331,8 @@ static int pmu_ctr_start_hw(uint32_t cidx, uint64_t ival, bool ival_update) if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF)) pmu_ctr_enable_irq_hw(cidx); + if (pmu_dev && pmu_dev->hw_counter_enable_irq) + pmu_dev->hw_counter_enable_irq(cidx); csr_write(CSR_MCOUNTINHIBIT, mctr_inhbt); skip_inhibit_update: @@ -328,10 +342,21 @@ skip_inhibit_update: return 0; } -static int pmu_ctr_start_fw(uint32_t cidx, uint64_t ival, bool ival_update) +static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code, + uint64_t ival, bool ival_update) { + int ret; u32 hartid = current_hartid(); + if (SBI_PMU_FW_MAX <= event_code && + pmu_dev && pmu_dev->fw_counter_start) { + ret = pmu_dev->fw_counter_start(cidx - num_hw_ctrs, + event_code, + ival, ival_update); + if (ret) + return ret; + } + if (ival_update) fw_counters_value[hartid][cidx - num_hw_ctrs] = ival; fw_counters_started[hartid] |= BIT(cidx - num_hw_ctrs); @@ -361,7 +386,7 @@ int sbi_pmu_ctr_start(unsigned long cbase, unsigned long cmask, /* Continue the start operation for other counters */ continue; else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW) - ret = pmu_ctr_start_fw(cidx, ival, bUpdate); + ret = pmu_ctr_start_fw(cidx, event_code, ival, bUpdate); else ret = pmu_ctr_start_hw(cidx, ival, bUpdate); } @@ -391,8 +416,17 @@ static int pmu_ctr_stop_hw(uint32_t cidx) return SBI_EALREADY_STOPPED; } -static int pmu_ctr_stop_fw(uint32_t cidx) +static int pmu_ctr_stop_fw(uint32_t cidx, uint32_t event_code) { + int ret; + + if (SBI_PMU_FW_MAX <= event_code && + pmu_dev && pmu_dev->fw_counter_stop) { + ret = pmu_dev->fw_counter_stop(cidx - num_hw_ctrs); + if (ret) + return ret; + } + fw_counters_started[current_hartid()] &= ~BIT(cidx - num_hw_ctrs); return 0; @@ -434,7 +468,7 @@ int sbi_pmu_ctr_stop(unsigned long cbase, unsigned long cmask, continue; else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW) - ret = pmu_ctr_stop_fw(cidx); + ret = pmu_ctr_stop_fw(cidx, event_code); else ret = pmu_ctr_stop_hw(cidx); @@ -481,6 +515,9 @@ static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx, mhpmevent_val = (mhpmevent_val & ~MHPMEVENT_SSCOF_MASK) | MHPMEVENT_MINH | MHPMEVENT_OF; + if (pmu_dev && pmu_dev->hw_counter_disable_irq) + pmu_dev->hw_counter_disable_irq(ctr_idx); + /* Update the inhibit flags based on inhibit flags received from supervisor */ pmu_update_inhibit_flags(flags, &mhpmevent_val); @@ -588,21 +625,26 @@ static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, unsigned lo * Thus, select the first available fw counter after sanity * check. */ -static int pmu_ctr_find_fw(unsigned long cbase, unsigned long cmask, u32 hartid) +static int pmu_ctr_find_fw(unsigned long cbase, unsigned long cmask, + uint32_t event_code, u32 hartid) { - int i = 0; - int fw_base; - unsigned long ctr_mask = cmask << cbase; + int i, cidx; - if (cbase < num_hw_ctrs) - fw_base = num_hw_ctrs; - else - fw_base = cbase; + for_each_set_bit(i, &cmask, BITS_PER_LONG) { + cidx = i + cbase; + if (cidx < num_hw_ctrs || total_ctrs <= cidx) + continue; + if (active_events[hartid][i] != SBI_PMU_EVENT_IDX_INVALID) + continue; + if (SBI_PMU_FW_MAX <= event_code && + pmu_dev && pmu_dev->fw_counter_match_code) { + if (!pmu_dev->fw_counter_match_code(cidx - num_hw_ctrs, + event_code)) + continue; + } - for (i = fw_base; i < total_ctrs; i++) - if ((active_events[hartid][i] == SBI_PMU_EVENT_IDX_INVALID) && - ((1UL << i) & ctr_mask)) - return i; + return i; + } return SBI_ENOTSUPP; } @@ -611,8 +653,8 @@ int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask, unsigned long flags, unsigned long event_idx, uint64_t event_data) { - int ctr_idx = SBI_ENOTSUPP; - u32 hartid = current_hartid(); + int ret, ctr_idx = SBI_ENOTSUPP; + u32 event_code, hartid = current_hartid(); int event_type; /* Do a basic sanity check of counter base & mask */ @@ -622,6 +664,7 @@ int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask, event_type = pmu_event_validate(event_idx); if (event_type < 0) return SBI_EINVAL; + event_code = get_cidx_code(event_idx); if (flags & SBI_PMU_CFG_FLAG_SKIP_MATCH) { /* The caller wants to skip the match because it already knows the @@ -636,7 +679,7 @@ int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask, if (event_type == SBI_PMU_EVENT_TYPE_FW) { /* Any firmware counter can be used track any firmware event */ - ctr_idx = pmu_ctr_find_fw(cidx_base, cidx_mask, hartid); + ctr_idx = pmu_ctr_find_fw(cidx_base, cidx_mask, event_code, hartid); } else { ctr_idx = pmu_ctr_find_hw(cidx_base, cidx_mask, flags, event_idx, event_data); @@ -655,8 +698,18 @@ skip_match: } else if (event_type == SBI_PMU_EVENT_TYPE_FW) { if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE) fw_counters_value[hartid][ctr_idx - num_hw_ctrs] = 0; - if (flags & SBI_PMU_CFG_FLAG_AUTO_START) + if (flags & SBI_PMU_CFG_FLAG_AUTO_START) { + if (SBI_PMU_FW_MAX <= event_code && + pmu_dev && pmu_dev->fw_counter_start) { + ret = pmu_dev->fw_counter_start( + ctr_idx - num_hw_ctrs, event_code, + fw_counters_value[hartid][ctr_idx - num_hw_ctrs], + true); + if (ret) + return ret; + } fw_counters_started[hartid] |= BIT(ctr_idx - num_hw_ctrs); + } } return ctr_idx; @@ -734,6 +787,19 @@ static void pmu_reset_event_map(u32 hartid) fw_counters_started[hartid] = 0; } +const struct sbi_pmu_device *sbi_pmu_get_device(void) +{ + return pmu_dev; +} + +void sbi_pmu_set_device(const struct sbi_pmu_device *dev) +{ + if (!dev || pmu_dev) + return; + + pmu_dev = dev; +} + void sbi_pmu_exit(struct sbi_scratch *scratch) { u32 hartid = current_hartid(); From patchwork Thu Aug 25 04:51:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1670045 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; 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([171.76.87.159]) by smtp.gmail.com with ESMTPSA id g5-20020a170902d1c500b0016eea511f2dsm13318881plb.242.2022.08.24.21.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Aug 2022 21:52:44 -0700 (PDT) From: Anup Patel To: Atish Patra , Alistair Francis Cc: Anup Patel , opensbi@lists.infradead.org, Anup Patel , Andrew Jones Subject: [PATCH 6/7] lib: sbi: Print platform PMU device at boot-time Date: Thu, 25 Aug 2022 10:21:43 +0530 Message-Id: <20220825045144.752619-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220825045144.752619-1-apatel@ventanamicro.com> References: <20220825045144.752619-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220824_215247_307948_1E34AE6C X-CRM114-Status: UNSURE ( 8.04 ) X-CRM114-Notice: Please train this message. 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Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- lib/sbi/sbi_init.c | 4 ++++ 1 file changed, 4 insertions(+) Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:102d listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Let us print the platform PMU device name at the boot-time so that users know whether the underlying platform has custom per-HART PMU operations. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- lib/sbi/sbi_init.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c index d57efa7..a8500e5 100644 --- a/lib/sbi/sbi_init.c +++ b/lib/sbi/sbi_init.c @@ -63,6 +63,7 @@ static void sbi_boot_print_banner(struct sbi_scratch *scratch) static void sbi_boot_print_general(struct sbi_scratch *scratch) { char str[128]; + const struct sbi_pmu_device *pdev; const struct sbi_hsm_device *hdev; const struct sbi_ipi_device *idev; const struct sbi_timer_device *tdev; @@ -93,6 +94,9 @@ static void sbi_boot_print_general(struct sbi_scratch *scratch) hdev = sbi_hsm_get_device(); sbi_printf("Platform HSM Device : %s\n", (hdev) ? hdev->name : "---"); + pdev = sbi_pmu_get_device(); + sbi_printf("Platform PMU Device : %s\n", + (pdev) ? pdev->name : "---"); srdev = sbi_system_reset_get_device(SBI_SRST_RESET_TYPE_COLD_REBOOT, 0); sbi_printf("Platform Reboot Device : %s\n", (srdev) ? srdev->name : "---"); From patchwork Thu Aug 25 04:51:44 2022 Content-Type: text/plain; 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([171.76.87.159]) by smtp.gmail.com with ESMTPSA id g5-20020a170902d1c500b0016eea511f2dsm13318881plb.242.2022.08.24.21.52.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Aug 2022 21:52:47 -0700 (PDT) From: Anup Patel To: Atish Patra , Alistair Francis Cc: Anup Patel , opensbi@lists.infradead.org, Anup Patel , Andrew Jones Subject: [PATCH 7/7] include: sbi: Reduce includes in sbi_pmu.h Date: Thu, 25 Aug 2022 10:21:44 +0530 Message-Id: <20220825045144.752619-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220825045144.752619-1-apatel@ventanamicro.com> References: <20220825045144.752619-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220824_215250_044734_9E9A1E07 X-CRM114-Status: UNSURE ( 8.83 ) X-CRM114-Notice: Please train this message. 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Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- include/sbi/sbi_pmu.h | 5 ++--- lib/sbi/sbi_pmu.c | 2 ++ lib/sbi/sbi_trap.c | 1 + 3 files ch [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:102c listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The sbi_pmu.h should only include minimal required headers whereas sbi_pmu.c should include all required headers. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- include/sbi/sbi_pmu.h | 5 ++--- lib/sbi/sbi_pmu.c | 2 ++ lib/sbi/sbi_trap.c | 1 + 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h index d787575..a2ce42d 100644 --- a/include/sbi/sbi_pmu.h +++ b/include/sbi/sbi_pmu.h @@ -11,9 +11,8 @@ #define __SBI_PMU_H__ #include -#include -#include -#include + +struct sbi_scratch; /* Event related macros */ /* Maximum number of hardware events that can mapped by OpenSBI */ diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 87e1ff8..214d5e8 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -10,7 +10,9 @@ #include #include #include +#include #include +#include #include #include #include diff --git a/lib/sbi/sbi_trap.c b/lib/sbi/sbi_trap.c index 0e30946..4c1339e 100644 --- a/lib/sbi/sbi_trap.c +++ b/lib/sbi/sbi_trap.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include