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Received: from AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) by VI1PR04MB4016.eurprd04.prod.outlook.com (2603:10a6:803:4a::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5525.10; Sun, 14 Aug 2022 07:42:14 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::2549:869e:d80b:3a1b]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::2549:869e:d80b:3a1b%6]) with mapi id 15.20.5504.027; Sun, 14 Aug 2022 07:42:14 +0000 From: Liu Ying To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, saravanak@google.com, gregkh@linuxfoundation.org, geert+renesas@glider.be, krzysztof.kozlowski@linaro.org, robh@kernel.org Subject: [PATCH v4 2/2] dt-bindings: bus: Add Freescale i.MX8qxp pixel link MSI bus binding Date: Sun, 14 Aug 2022 15:43:38 +0800 Message-Id: <20220814074338.453608-3-victor.liu@nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220814074338.453608-1-victor.liu@nxp.com> References: <20220814074338.453608-1-victor.liu@nxp.com> X-ClientProxiedBy: SG2PR06CA0197.apcprd06.prod.outlook.com (2603:1096:4:1::29) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 78d2ab91-196c-448c-2240-08da7dc880f2 X-MS-TrafficTypeDiagnostic: VI1PR04MB4016:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6Fuz4GBa6OxqFRFXD/ALo7rhrjzTkNlY6hxX2aPgTUTzQyEr+BpTfaLXmX/fuICWeBKNyNt/xutL4PmiXq6p2x61w8LQiw/h9At4TJRjgrFXX61uI7TK/fkiTb4kFLwuzzeIuYjEiezDw8bnK/CZBfCGO0XVSEFPcwaZCzBbQafVA8uvlgVI9Mgo/NZD47EUTIGI/gv6NzDZrtjJ77BYCEiiGAF4KsSHR9vvcb7uun0V1rPIpYRhJ6BSKx3Ku2b2OBqEvyweONQPMy0WATYicItlspl0f9nzT7BQlWzZ5CLahZN3MY5AuNP0nutEcERUzp52FbVBhqklSYICsj1ZuLfmgNejfzo3u3SKYRXuVhzMJcxaUA+fsuDXAFc9H/C9D5dzNXLYUbRr5oOmLTQHir4oB0IgYcd4PSx8WHYdjtghFRqxk/Cyr7b97D0V9n4j+Kjyp8XN8pcD5uEhEp7QHoWhKpleCPStnfsuG+u6JWpbOs7VRYTckrC/2pncyd9XFPU/8DmgX0EG0Fzuw5cZnt6ioPoylDVF3T+71WTFSXlJFlZt6Ywec1xsX/dpP2LaYhIBt29ed3RM7hvTt0KC2A8kuBJg6AQYbUUcRpMC09OIYWZ/l4T+LnNMBrHyssz0pDgHA3dGBpH9iGvtGgjN7vSIe8thJqWlXl9yvez7MYBgZ2ypXXmFVkz09qhCEhX2njWjpv/y+yDjMnujcyprRw2pv/hO7nvLwrPa/QKeuC9ndGaVc9BYIbT96l7Lz6rqeo+6U6GAVgjescxSYfy93PGm/01eOnORUMfQZqlCj4Unukd20ujSjKVxALoySWphuZyPsU6GO8pc+gfq7d5iK8FPgb2xMZBv+SuoR9WlNg64H1XpMSVpd3Lgu8Qw/YauKzg9hcb4FR0fNcqlLu8svwbFIoEQndKXHb6qG9/3ZSiIKZa6lh0FotGJ0nisXfrXNG+zmF4TqEzHG35d8eqemAK3jxjm8dZkzgRJd/o2qXgV9e9345MArcaeIvS8fIN/iN5P1rt2GYzitUudq8MiqEdmUzGLI7gkwWPq/BaYbyMwWIRQbU1bu1qxLhxRGsYOczcspmRj65VAz7FQmFJzGw2xcDVYUDlXOA6N09bZMF6v2c3yIxCmJrezD84F2o2wjxvQ5aHrzr2RReeBQ8LtWLICgKjTB9tDZ1KNLW7y7gU7YPUGgshOqhMGjpyBgvzzc77fGw2UPxMsfJoCr5bKIwfr+hTQttzSO1FYN3jgMTPy/cS8OBvNItaMv8WVM8BqaRrBAP7wERtkDPrwDl65OTYS38iGTgOUK9XaZK+UoDhFZWxruxLTsTOM9b1kMKLEWhWfVzv3XxI/5gDHB/4FBdUcaHAjWuNovtkMwxSKO4+OIjqcJ8FTeu+3a+hcYZDj8iY+6w/sjyL8tvZqefiR/v4XC/KKpx65yukV0AFw6WhiDUuogrL5hhjLJEd6BnfTGFNm98wtTBwQzlL5+5nOWTFCOncrLoOjfKg9hrttuXuAKZpKt0VXOzVCR+J25782Ud4cjjNAzAu9eYZ8fTCzS4lZOQRbf2FcrimXb0fFaYG4SSq1J+ey9r7pTsdWDTJ7 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 78d2ab91-196c-448c-2240-08da7dc880f2 X-MS-Exchange-CrossTenant-AuthSource: AM7PR04MB7046.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Aug 2022 07:42:13.9754 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +M4QHIrEh5oCvWKLl0WaWXfDV3PaDJFr9RBDQb3ebsRaE/6OYO9HfJxrp8f7cYgJtn5+muh8bjQwXed7v1PKIA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB4016 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Freescale i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. It is used to access peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems, like I2C controller, PWM controller, MIPI DSI controller and Control and Status Registers (CSR) module. Reference simple-pm-bus bindings and add Freescale i.MX8qxp pixel link MSI bus specific bindings. Signed-off-by: Liu Ying --- v3->v4: * Add child nodes in the example MSI bus node of the MSI bus dt-binding. (Krzysztof) v2->v3: * Add a pattern property to allow child nodes. (Rob) v1->v2: Address Krzysztof's comments: * Add a select to explicitly select the MSI bus dt-binding. * List 'simple-pm-bus' explicitly as one item of compatible strings. * Require compatible and reg properties. * Put reg property just after compatible property in example. .../bus/fsl,imx8qxp-pixel-link-msi-bus.yaml | 232 ++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml diff --git a/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml new file mode 100644 index 000000000000..b568d0ce438d --- /dev/null +++ b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml @@ -0,0 +1,232 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus + +maintainers: + - Liu Ying + +description: | + i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os + sitting together with the PHYs. It is not the same as the MSI bus coming + from i.MX8 System Controller Unit (SCU) which is used to control power, + clock and reset through the i.MX8 Distributed Slave System Controller (DSC). + + i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks, + that is, MSI clock and AHB clock, need to be enabled so that peripherals + connected to the bus can be accessed. Also, the bus is part of a power + domain. The power domain needs to be enabled before the peripherals can + be accessed. + + Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems, + like I2C controller, PWM controller, MIPI DSI controller and Control and + Status Registers (CSR) module, are accessed through the bus. + + The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp + pixel link MSI bus controller and does not allow SCFW user to control it. + So, the controller's registers cannot be accessed by SCFW user. Hence, + the interrupts generated by the controller don't make any sense from SCFW + user's point of view. + +allOf: + - $ref: simple-pm-bus.yaml# + +# We need a select here so we don't match all nodes with 'simple-pm-bus'. +select: + properties: + compatible: + contains: + enum: + - fsl,imx8qxp-display-pixel-link-msi-bus + - fsl,imx8qm-display-pixel-link-msi-bus + required: + - compatible + +properties: + compatible: + items: + - enum: + - fsl,imx8qxp-display-pixel-link-msi-bus + - fsl,imx8qm-display-pixel-link-msi-bus + - const: simple-pm-bus + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: master gated clock from system + - description: AHB clock + + clock-names: + items: + - const: msi + - const: ahb + +patternProperties: + "^.*@[0-9a-f]+$": + description: Devices attached to the bus + type: object + properties: + reg: + maxItems: 1 + + required: + - reg + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + bus@56200000 { + compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus"; + reg = <0x56200000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&dc0_irqsteer>; + interrupts = <320>; + ranges; + clocks = <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>, + <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>; + clock-names = "msi", "ahb"; + power-domains = <&pd IMX_SC_R_DC_0>; + + syscon@56221000 { + compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd"; + reg = <0x56221000 0x1000>; + clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>; + clock-names = "ipg"; + + pxl2dpi { + compatible = "fsl,imx8qxp-pxl2dpi"; + fsl,sc-resource = ; + power-domains = <&pd IMX_SC_R_MIPI_0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>; + }; + + mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>; + }; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>; + }; + }; + }; + }; + + ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>; + }; + }; + + port@1 { + reg = <1>; + + /* ... */ + }; + }; + + channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>; + }; + }; + + port@1 { + reg = <1>; + + /* ... */ + }; + }; + }; + }; + + clock-controller@56223004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223004 0x4>; + #clock-cells = <1>; + clocks = <&mipi_lvds_0_ipg_clk>; + clock-indices = ; + clock-output-names = "mipi_lvds_0_di_mipi_lvds_regs_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + phy@56228300 { + compatible = "fsl,imx8qxp-mipi-dphy"; + reg = <0x56228300 0x100>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + fsl,syscon = <&mipi_lvds_0_csr>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + };