From patchwork Thu Jul 21 17:21:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1659233 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=conchuod.ie header.i=@conchuod.ie header.a=rsa-sha256 header.s=google header.b=MPZoE7gQ; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LpfVy3ztwz9s07 for ; Fri, 22 Jul 2022 03:21:30 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229750AbiGURV1 (ORCPT ); Thu, 21 Jul 2022 13:21:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229517AbiGURV0 (ORCPT ); Thu, 21 Jul 2022 13:21:26 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF32A2CC95 for ; Thu, 21 Jul 2022 10:21:24 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id f24-20020a1cc918000000b003a30178c022so3741097wmb.3 for ; Thu, 21 Jul 2022 10:21:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XkkKPN3JJIki5/fJ0m2iMmrfk4IJDQ0Iyb2jgEwcMfA=; b=MPZoE7gQwOxPubrMsSNTRL2lSMXyd7GdLpsv87PPzdomrz6yEU381zHGLjU0kmnqeQ WtGx7JqzCm8T0cLSIzMZ5v5SrIr3ldYAkBNphbsgO6sAXriMu5lefm+3TPJzBs1yp2o4 UNIRU3SS8Z0voBJ6/nUisMbU0iz1vkak5zWJDLUK7ntavyNgeaAkrGT8Nxxa/1sXLAen vY4eDgkECXnqYcPEX2Ckqn/xr5bFqLiUZFlYFin4gcB3e8pCsy49RWJEjvTMubhJT/3k UdnH6aq/fqdfp+5TUF5OB38JDpy3yExgYHEVNT1hfYXYmPktMJbQGROk7dqSLV+CTlDl xa5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XkkKPN3JJIki5/fJ0m2iMmrfk4IJDQ0Iyb2jgEwcMfA=; b=Z/FN9m8A5s+6DYulMktWalwmSSG8IRYaC1RzT0iJUr3rV55TOJ/bmtejfzUhrGs0Fv rLPq8zw1b8o0LIrbG4ZuQepYrQuT0DrMkHpQoHsNkqsWk2ts7l2gh3pR8HtvzwPVcTNv gt6nWHHNdA9PJkAdF/6htMFSqz/6AMEcFJyu9i7FAYxFJXd0SbetUsrq3hF32mp6W9rR NPxg1Tjg7RAYa5GXMBcCkPYWU5g6pXi/GNq3FWd8WK+aMS5oTYOM7ghs5UaNt9w3CBmM sByuBgKFR6B+zdq4Nxf/Ek7zUaaUm9hIzTpYXE7ea3Ji4dl0fZveYnbxcvh5ukd1rRBk U31w== X-Gm-Message-State: AJIora/aQfW/60S9NGO6bTA0E6EIYGF06kyX1wFs8U4B/EwdJGKFFiJg DdRL7JswzvwonsMrJWV6AGqhIw== X-Google-Smtp-Source: AGRyM1uhhSObQMZkAZrCHl/IohFymT6ZizEWGdATrGEa0Aj1iPY95PQHYw/2A70KC/Ux7C4ZW05kEg== X-Received: by 2002:a1c:f314:0:b0:3a2:fee4:91d4 with SMTP id q20-20020a1cf314000000b003a2fee491d4mr8835647wmq.108.1658424083196; Thu, 21 Jul 2022 10:21:23 -0700 (PDT) Received: from henark71.. ([109.76.125.251]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003a2cf1535aasm2455697wme.17.2022.07.21.10.21.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 10:21:22 -0700 (PDT) From: Conor Dooley To: u.kleine-koenig@pengutronix.de Cc: conor.dooley@microchip.com, daire.mcnamara@microchip.com, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org, robh+dt@kernel.org, thierry.reding@gmail.com, Rob Herring Subject: [PATCH v7 1/4] dt-bindings: pwm: fix microchip corePWM's pwm-cells Date: Thu, 21 Jul 2022 18:21:07 +0100 Message-Id: <20220721172109.941900-2-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220721172109.941900-1-mail@conchuod.ie> References: <20220721172109.941900-1-mail@conchuod.ie> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Conor Dooley corePWM is capable of inverted operation but the binding requires \#pwm-cells of 2. Expand the binding to support setting the polarity. Fixes: df77f7735786 ("dt-bindings: pwm: add microchip corepwm binding") Acked-by: Rob Herring Signed-off-by: Conor Dooley Acked-by: Uwe Kleine-König --- Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml index a7fae1772a81..cd8e9a8907f8 100644 --- a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml +++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml @@ -30,7 +30,9 @@ properties: maxItems: 1 "#pwm-cells": - const: 2 + enum: [2, 3] + description: + The only flag supported by the controller is PWM_POLARITY_INVERTED. microchip,sync-update-mask: description: | From patchwork Thu Jul 21 17:21:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1659234 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=conchuod.ie header.i=@conchuod.ie header.a=rsa-sha256 header.s=google header.b=BE/cWNCZ; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LpfVz1ww0z9s07 for ; Fri, 22 Jul 2022 03:21:31 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229696AbiGURV2 (ORCPT ); Thu, 21 Jul 2022 13:21:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229684AbiGURV1 (ORCPT ); Thu, 21 Jul 2022 13:21:27 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13C912CDD9 for ; Thu, 21 Jul 2022 10:21:26 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id bv24so3219954wrb.3 for ; Thu, 21 Jul 2022 10:21:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FRltm9CBKXROfT3TUcmTyCGbNeVKq4rgRYEpJSVmOTw=; b=BE/cWNCZlI0Yl2QqiuxKv8xSMdjJtWyLI/XATrhxomnVoulKNVnl6BscEEGiBjoi9J BZOY1voXavMn91Z/eD4KGNkYrKldYtbHnOVL31JiY9igICQa28VuBFpx1hmSWvjqUBMi EAF89C6f9VFQib4yYUeWDY4QnawWxcEGZaqJxhodUJRAMPnLNgBM1MsV8JAH3Pm8Q/K3 QLWhvk4FjCGQ8/NuTqbwo4jLB77Q/+7i44oo4RfpKwLjr/T9JMa90ra6huIGyOmB+4rE rnWdSdTKQ60CBLLWjeIuFgpJMUz3Ao57HKpHTsKgf5FKN+P/m5U1ukj43M+l8uMN9ZR0 BWog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FRltm9CBKXROfT3TUcmTyCGbNeVKq4rgRYEpJSVmOTw=; b=fWx7pK28pJzf1YNdE4U9g3MVvJ+xcNRlama/YwwCBG7O6eYCu6lg6LKeAV4FiupNwn kX5B67Ydb2h6LxKelqFn+Njmuz4k5R+rTFNEo5DKcFFry66sDXXUdEoYQyyn2GfzW1YI MRohkL9j4GJC/liJ4V7g5f0iHn7yao85Uvrx6O4ipbDp9QmQVuJZqAngFsRvEogaa/ef MixgaF9j9cyutacXd3M+Qfaj0wnjdgcc19uAUBBBY12YqdO8iBEibjz4Pwdd7PxPO1XL j7Z3Cb+aacFzhUGQ3Jpe+vF+Km5RmNU54I7uV52jHpzDedpQ1ffJ6o0YELVaEkU2pdX/ tKUQ== X-Gm-Message-State: AJIora/DQwxVJYTfppW3DX17aTrfhsbK9JVTNi7wb2MQnzLT9Jkpa+16 x19KPi6dA1a/SIfwfekN+tf7tRK8/45sdYd8 X-Google-Smtp-Source: AGRyM1vbAYGz2xsyca/zeMEjF8XABXoOModC93BUJZC9+XeAjfvxiTzDa0Td1Cv679XzakodtlQW7A== X-Received: by 2002:a05:6000:609:b0:21d:92ad:562 with SMTP id bn9-20020a056000060900b0021d92ad0562mr34175479wrb.369.1658424084463; Thu, 21 Jul 2022 10:21:24 -0700 (PDT) Received: from henark71.. ([109.76.125.251]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003a2cf1535aasm2455697wme.17.2022.07.21.10.21.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 10:21:23 -0700 (PDT) From: Conor Dooley To: u.kleine-koenig@pengutronix.de Cc: conor.dooley@microchip.com, daire.mcnamara@microchip.com, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org, robh+dt@kernel.org, thierry.reding@gmail.com Subject: [PATCH v7 2/4] riscv: dts: fix the icicle's #pwm-cells Date: Thu, 21 Jul 2022 18:21:08 +0100 Message-Id: <20220721172109.941900-3-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220721172109.941900-1-mail@conchuod.ie> References: <20220721172109.941900-1-mail@conchuod.ie> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Conor Dooley \#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 & blindly overridden by the (out of tree) driver anyway. The core can support inverted operation, so update the entry to correctly report its capabilities. Fixes: 72560c6559b8 ("riscv: dts: microchip: add fpga fabric section to icicle kit") Signed-off-by: Conor Dooley Reviewed-by: Uwe Kleine-König --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 0d28858b83f2..e09a13aef268 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -8,7 +8,7 @@ core_pwm0: pwm@41000000 { compatible = "microchip,corepwm-rtl-v4"; reg = <0x0 0x41000000 0x0 0xF0>; microchip,sync-update-mask = /bits/ 32 <0>; - #pwm-cells = <2>; + #pwm-cells = <3>; clocks = <&fabric_clk3>; status = "disabled"; }; From patchwork Thu Jul 21 17:21:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1659235 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=conchuod.ie header.i=@conchuod.ie header.a=rsa-sha256 header.s=google header.b=NuG5LtZs; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LpfW057ZWz9s07 for ; Fri, 22 Jul 2022 03:21:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230482AbiGURVa (ORCPT ); Thu, 21 Jul 2022 13:21:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230302AbiGURV3 (ORCPT ); Thu, 21 Jul 2022 13:21:29 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A75DA2B613 for ; Thu, 21 Jul 2022 10:21:27 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id k11so2760996wrx.5 for ; Thu, 21 Jul 2022 10:21:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XKFlMNoRZNMbimi2EeV/cgP8CxzqyNd0gTC1i+1Q0p8=; b=NuG5LtZsrE2y2A2GHZ2TmuQPJSmxlwbrG+2zxN/GuT9QJrf/5B9dCPAEYzfAMvkQ/d +KTELN1uQgvJ0H6dZHI3zcoCvC2Y3p8JZZM4mYQyxouFvPM2jSpyfwjylflL8+TGnVkd hQTtJPF5v4zZduBRo67prW8oFjCJi0m5RyEmIXytCqfQIW0OeKaO6+hbcACsle7iQdyr Sy7h3b1oA+jlhHraI3BAn5lYDpQ90xCShwGEl3wTy4tVqfgMdn2RXN7yiI8g3C8YjqTC nk+Z+TsZOE9ZVvI15OxptB5yvRXPA9DmivDyjY7f1G8gcMyoQcaATmj+Hggu85jCkjlZ RMMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XKFlMNoRZNMbimi2EeV/cgP8CxzqyNd0gTC1i+1Q0p8=; b=jqgevuSFNM4R1V18X83CZKtefzblOkJnaRSCXY7yPCZKbRdb4W1KJyEIDznsWSq0qT 9WXFB/7+ZUcztPg950YO0VPFlqRypTGFhsFXdZikjZFPjtKheCYRsSwYqlGMPNc60uHC Y7OabbtJreyIlEDEggIw48L0BAbCv0t0+yuqsCjVe108K3FVVgkBZQhv3YTe7Ca+bDDc Sbsh9e8/fFMVQoScPlPyyTcSdUaSMzaEfjeK0CJKJ+oJXPNLnv5A103QT0f2W05P1evB ZopQIu/O+7mjvoYeH36Jn9W4DGHgfXE9+j6fyPOQ8XvkIgAp4SLfreK60isgHTEYxwII CdQg== X-Gm-Message-State: AJIora8E+YAehfaDEHUkWC3hz0enD6cMlAxsBuBVkX7NYu7cG2bUJVNU CVVo3NWpRXULenfu+BA/WnsVmg== X-Google-Smtp-Source: AGRyM1sNWeQliiCvTj3Nyh2PceHU2MN/Ch0q7YlErtvxjeyO/+YzH1WqBfejVKJOhLQ/0vDKJRk6Yw== X-Received: by 2002:a5d:5311:0:b0:21d:656b:807e with SMTP id e17-20020a5d5311000000b0021d656b807emr34478737wrv.521.1658424085611; Thu, 21 Jul 2022 10:21:25 -0700 (PDT) Received: from henark71.. ([109.76.125.251]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003a2cf1535aasm2455697wme.17.2022.07.21.10.21.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 10:21:25 -0700 (PDT) From: Conor Dooley To: u.kleine-koenig@pengutronix.de Cc: conor.dooley@microchip.com, daire.mcnamara@microchip.com, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org, robh+dt@kernel.org, thierry.reding@gmail.com Subject: [PATCH v7 3/4] pwm: add microchip soft ip corePWM driver Date: Thu, 21 Jul 2022 18:21:09 +0100 Message-Id: <20220721172109.941900-4-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220721172109.941900-1-mail@conchuod.ie> References: <20220721172109.941900-1-mail@conchuod.ie> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Conor Dooley Add a driver that supports the Microchip FPGA "soft" PWM IP core. Signed-off-by: Conor Dooley --- drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-microchip-core.c | 371 +++++++++++++++++++++++++++++++ 3 files changed, 382 insertions(+) create mode 100644 drivers/pwm/pwm-microchip-core.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 904de8d61828..007ea5750e73 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -383,6 +383,16 @@ config PWM_MEDIATEK To compile this driver as a module, choose M here: the module will be called pwm-mediatek. +config PWM_MICROCHIP_CORE + tristate "Microchip corePWM PWM support" + depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST + depends on HAS_IOMEM && OF + help + PWM driver for Microchip FPGA soft IP core. + + To compile this driver as a module, choose M here: the module + will be called pwm-microchip-core. + config PWM_MXS tristate "Freescale MXS PWM support" depends on ARCH_MXS || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 5c08bdb817b4..43feb7cfc66a 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o obj-$(CONFIG_PWM_MESON) += pwm-meson.o obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o +obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o obj-$(CONFIG_PWM_MXS) += pwm-mxs.o obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o diff --git a/drivers/pwm/pwm-microchip-core.c b/drivers/pwm/pwm-microchip-core.c new file mode 100644 index 000000000000..2d12248f86b8 --- /dev/null +++ b/drivers/pwm/pwm-microchip-core.c @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * corePWM driver for Microchip "soft" FPGA IP cores. + * + * Copyright (c) 2021-2022 Microchip Corporation. All rights reserved. + * Author: Conor Dooley + * Documentation: + * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb + * + * Limitations: + * - If the IP block is configured without "shadow registers", all register + * writes will take effect immediately, causing glitches on the output. + * If shadow registers *are* enabled, a write to the "SYNC_UPDATE" register + * notifies the core that it needs to update the registers defining the + * waveform from the contents of the "shadow registers". + * - The IP block has no concept of a duty cycle, only rising/falling edges of + * the waveform. Unfortunately, if the rising & falling edges registers have + * the same value written to them the IP block will do whichever of a rising + * or a falling edge is possible. I.E. a 50% waveform at twice the requested + * period. Therefore to get a 0% waveform, the output is set the max high/low + * time depending on polarity. + * - The PWM period is set for the whole IP block not per channel. The driver + * will only change the period if no other PWM output is enabled. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PREG_TO_VAL(PREG) ((PREG) + 1) + +#define MCHPCOREPWM_PRESCALE_MAX 0x100 +#define MCHPCOREPWM_PERIOD_STEPS_MAX 0xff +#define MCHPCOREPWM_PERIOD_MAX 0xff00 + +#define MCHPCOREPWM_PRESCALE 0x00 +#define MCHPCOREPWM_PERIOD 0x04 +#define MCHPCOREPWM_EN(i) (0x08 + 0x04 * (i)) /* 0x08, 0x0c */ +#define MCHPCOREPWM_POSEDGE(i) (0x10 + 0x08 * (i)) /* 0x10, 0x18, ..., 0x88 */ +#define MCHPCOREPWM_NEGEDGE(i) (0x14 + 0x08 * (i)) /* 0x14, 0x1c, ..., 0x8c */ +#define MCHPCOREPWM_SYNC_UPD 0xe4 + +struct mchp_core_pwm_chip { + struct pwm_chip chip; + struct clk *clk; + struct mutex lock; /* protect the shared period */ + void __iomem *base; + u32 sync_update_mask; + u16 channel_enabled; +}; + +static inline struct mchp_core_pwm_chip *to_mchp_core_pwm(struct pwm_chip *chip) +{ + return container_of(chip, struct mchp_core_pwm_chip, chip); +} + +static void mchp_core_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, + bool enable, u64 period) +{ + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip); + u8 channel_enable, reg_offset, shift; + + /* + * There are two adjacent 8 bit control regs, the lower reg controls + * 0-7 and the upper reg 8-15. Check if the pwm is in the upper reg + * and if so, offset by the bus width. + */ + reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3); + shift = pwm->hwpwm & 7; + + channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset); + channel_enable &= ~(1 << shift); + channel_enable |= (enable << shift); + + writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset); + mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm); + mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm; + + /* + * Notify the block to update the waveform from the shadow registers. + * The updated values will not appear on the bus until they have been + * applied to the waveform at the beginning of the next period. We must + * write these registers and wait for them to be applied before calling + * enable(). + */ + if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm)) { + writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD); + usleep_range(period, period * 2); + } +} + +static u64 mchp_core_pwm_calc_duty(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state, u8 prescale, u8 period_steps) +{ + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip); + u64 duty_steps, period, tmp; + u16 prescale_val = PREG_TO_VAL(prescale); + u8 period_steps_val = PREG_TO_VAL(period_steps); + + period = period_steps_val * prescale_val * NSEC_PER_SEC; + period = DIV64_U64_ROUND_UP(period, clk_get_rate(mchp_core_pwm->clk)); + + /* + * Calculate the duty cycle in multiples of the prescaled period: + * duty_steps = duty_in_ns / step_in_ns + * step_in_ns = (prescale * NSEC_PER_SEC) / clk_rate + * The code below is rearranged slightly to only divide once. + */ + duty_steps = state->duty_cycle * clk_get_rate(mchp_core_pwm->clk); + tmp = prescale_val * NSEC_PER_SEC; + return div64_u64(duty_steps, tmp); +} + +static void mchp_core_pwm_apply_duty(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state, u64 duty_steps, u8 period_steps) +{ + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip); + u8 posedge, negedge; + u8 period_steps_val = PREG_TO_VAL(period_steps); + + /* + * Turn the output on unless posedge == negedge, in which case the + * duty is intended to be 0, but limitations of the IP block don't + * allow a zero length duty cycle - so just set the max high/low time + * respectively. + */ + if (state->polarity == PWM_POLARITY_INVERSED) { + negedge = !duty_steps ? period_steps_val : 0u; + posedge = duty_steps; + } else { + posedge = !duty_steps ? period_steps_val : 0u; + negedge = duty_steps; + } + + writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm)); + writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm)); +} + +static int mchp_core_pwm_calc_period(struct pwm_chip *chip, const struct pwm_state *state, + u8 *prescale, u8 *period_steps) +{ + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip); + u64 tmp, clk_rate; + + /* + * Calculate the period cycles and prescale values. + * The registers are each 8 bits wide & multiplied to compute the period + * using the formula: + * (clock_period) * (prescale + 1) * (period_steps + 1) + * so the maximum period that can be generated is 0x10000 times the + * period of the input clock. + * However, due to the design of the "hardware", it is not possible to + * attain a 100% duty cycle if the full range of period_steps is used. + * Therefore period_steps is restricted to 0xFE and the maximum multiple + * of the clock period attainable is 0xFF00. + */ + clk_rate = clk_get_rate(mchp_core_pwm->clk); + + /* + * If clk_rate is too big, the following multiplication might overflow. + * However this is implausible, as the fabric of current FPGAs cannot + * provide clocks at a rate high enough. + */ + if (clk_rate >= NSEC_PER_SEC) + return -EINVAL; + + tmp = mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC); + + if (tmp >= MCHPCOREPWM_PERIOD_MAX) { + *prescale = MCHPCOREPWM_PRESCALE_MAX - 1; + *period_steps = MCHPCOREPWM_PERIOD_STEPS_MAX - 1; + return 0; + } + + *prescale = div_u64(tmp, MCHPCOREPWM_PERIOD_STEPS_MAX); + /* PREG_TO_VAL() can produce a value larger than UINT8_MAX */ + *period_steps = div_u64(tmp, PREG_TO_VAL((u32)*prescale)) - 1; + + return 0; +} + +static inline void mchp_core_pwm_apply_period(struct mchp_core_pwm_chip *mchp_core_pwm, + u8 prescale, u8 period_steps) +{ + writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); + writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD); +} + +static int mchp_core_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip); + struct pwm_state current_state = pwm->state; + bool period_locked; + u64 duty_steps; + u8 prescale, period_steps, hw_prescale, hw_period_steps; + int ret; + + ret = mutex_lock_interruptible(&mchp_core_pwm->lock); + if (ret) + return ret; + + if (!state->enabled) { + mchp_core_pwm_enable(chip, pwm, false, current_state.period); + mutex_unlock(&mchp_core_pwm->lock); + return 0; + } + + /* + * If the only thing that has changed is the duty cycle or the polarity, + * we can shortcut the calculations and just compute/apply the new duty + * cycle pos & neg edges + * As all the channels share the same period, do not allow it to be + * changed if any other channels are enabled. + * If the period is locked, it may not be possible to use a period + * less than that requested. In that case, we just abort. + */ + period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm); + + if (period_locked) { + mchp_core_pwm_calc_period(chip, state, &prescale, &period_steps); + hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); + hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD); + + if ((period_steps * prescale) < (hw_period_steps * hw_prescale)) { + mutex_unlock(&mchp_core_pwm->lock); + return -EINVAL; + } + + prescale = hw_prescale; + period_steps = hw_period_steps; + } else if (!current_state.enabled || current_state.period != state->period) { + ret = mchp_core_pwm_calc_period(chip, state, &prescale, &period_steps); + if (ret) { + mutex_unlock(&mchp_core_pwm->lock); + return ret; + } + mchp_core_pwm_apply_period(mchp_core_pwm, prescale, period_steps); + } else { + prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); + period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD); + } + + duty_steps = mchp_core_pwm_calc_duty(chip, pwm, state, prescale, period_steps); + + /* + * Because the period is per channel, it is possible that the requested + * duty cycle is longer than the period, in which case cap it to the + * period, IOW a 100% duty cycle. + */ + if (duty_steps > period_steps) + duty_steps = period_steps + 1; + + mchp_core_pwm_apply_duty(chip, pwm, state, duty_steps, period_steps); + + mchp_core_pwm_enable(chip, pwm, true, state->period); + + mutex_unlock(&mchp_core_pwm->lock); + + return 0; +} + +static void mchp_core_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip); + u16 prescale; + u8 period_steps, duty_steps, posedge, negedge; + int ret; + + ret = mutex_lock_interruptible(&mchp_core_pwm->lock); + if (ret) + return; + + if (mchp_core_pwm->channel_enabled & (1 << pwm->hwpwm)) + state->enabled = true; + else + state->enabled = false; + + prescale = PREG_TO_VAL(readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE)); + + period_steps = PREG_TO_VAL(readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD)); + state->period = period_steps * prescale * NSEC_PER_SEC; + state->period = DIV64_U64_ROUND_UP(state->period, clk_get_rate(mchp_core_pwm->clk)); + + posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm)); + negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm)); + + if (negedge == posedge) { + state->duty_cycle = state->period / 2; + } else { + duty_steps = abs((s16)posedge - (s16)negedge); + state->duty_cycle = duty_steps * prescale * NSEC_PER_SEC; + state->duty_cycle = DIV64_U64_ROUND_UP(state->duty_cycle, + clk_get_rate(mchp_core_pwm->clk)); + } + + state->polarity = negedge < posedge ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; + + mutex_unlock(&mchp_core_pwm->lock); +} + +static const struct pwm_ops mchp_core_pwm_ops = { + .apply = mchp_core_pwm_apply, + .get_state = mchp_core_pwm_get_state, + .owner = THIS_MODULE, +}; + +static const struct of_device_id mchp_core_of_match[] = { + { + .compatible = "microchip,corepwm-rtl-v4", + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mchp_core_of_match); + +static int mchp_core_pwm_probe(struct platform_device *pdev) +{ + struct mchp_core_pwm_chip *mchp_pwm; + struct resource *regs; + int ret; + + mchp_pwm = devm_kzalloc(&pdev->dev, sizeof(*mchp_pwm), GFP_KERNEL); + if (!mchp_pwm) + return -ENOMEM; + + mchp_pwm->base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); + if (IS_ERR(mchp_pwm->base)) + return PTR_ERR(mchp_pwm->base); + + mchp_pwm->clk = devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(mchp_pwm->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(mchp_pwm->clk), + "failed to get PWM clock\n"); + + if (of_property_read_u32(pdev->dev.of_node, "microchip,sync-update-mask", + &mchp_pwm->sync_update_mask)) + mchp_pwm->sync_update_mask = 0u; + + mutex_init(&mchp_pwm->lock); + + mchp_pwm->chip.dev = &pdev->dev; + mchp_pwm->chip.ops = &mchp_core_pwm_ops; + mchp_pwm->chip.npwm = 16; + + ret = devm_pwmchip_add(&pdev->dev, &mchp_pwm->chip); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n"); + + return 0; +} + +static struct platform_driver mchp_core_pwm_driver = { + .driver = { + .name = "mchp-core-pwm", + .of_match_table = mchp_core_of_match, + }, + .probe = mchp_core_pwm_probe, +}; +module_platform_driver(mchp_core_pwm_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("corePWM driver for Microchip FPGAs"); From patchwork Thu Jul 21 17:21:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1659236 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=conchuod.ie header.i=@conchuod.ie header.a=rsa-sha256 header.s=google header.b=OSGxsO7g; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LpfW372g5z9s2R for ; Fri, 22 Jul 2022 03:21:35 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230256AbiGURVc (ORCPT ); Thu, 21 Jul 2022 13:21:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229833AbiGURV3 (ORCPT ); Thu, 21 Jul 2022 13:21:29 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7166D2D1CF for ; Thu, 21 Jul 2022 10:21:28 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id k11so2761054wrx.5 for ; Thu, 21 Jul 2022 10:21:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SXLvUdDnjJEodQJ94faqLUeDy8d1elhS2wljuKyR9r4=; b=OSGxsO7g2K40pu0NwLqzvnlUz82CEbFPTvtAHhq0Lt42XIo478IZ0cVHDyZcv3LzN+ doQwS0X5S7UHIxC9NIByl8mpgfD+9fykQt8oCdaEmU61OOI4m/PpDnv1MosqFBkN+Mm6 Eah/SZ6SreSS+CWTZNEMdvTvTRoLgblAU2dfyUrMl5tNJESdszbOWXfe3Gd+tsC1mNIa V/LZjsE1Rq7iYgiJNcx4XZ1FcwcPBXWrZdOyi6bpWW07Bp7wovr21Nkp97BOPnXf9a9S k2mwT8d9r+UvMll3RAl+MpEmvZNnLBOi+1iHTbqB2z5dlGiFL851dRrd2FQgyyixo8v7 HSYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SXLvUdDnjJEodQJ94faqLUeDy8d1elhS2wljuKyR9r4=; b=u+idPBYmvedgZ5rjNQeNHnnhrgjysqM0wwkC7/yZefGdnDpnTxlZDLsV09AANY+Z/s rlBz5yDBrzh+d7AYxfzIH29LAxwu0zeiq/UIYwBxKEGnrFM94SavNsU+aSDyi8R89oLk PSOcx1AyO3mW3WdrGE7gmgGZlep/W+Mt7JXEwdyL92l8prpfTvONVpwfNtODaXr6m6uz AI/J8NOG2UCfa2C/jZuYojeBG5g8xpJv/sLcjgvHpKz7F9sxJXevSklmJpkKm/JOQsVi 10YhaVjQ0TpT6NTmji8dyRm3vvyUQ7oVpo+7K6Pfe1d8kL09728LQm7m9OwlIsB/0YzB a3Aw== X-Gm-Message-State: AJIora/UVybcpO3P3JFFZSjzyQzBfDWUmKVPywLqxtTKinsLjdksqc4F z0XBJOgI2zYuQvc2FAWJZFb1hg== X-Google-Smtp-Source: AGRyM1sIASv9vmR7KNGAFsXqp4jOf5Se7BsMQgouD3zNrQ1FA0oeq0+2XKTq6qHLn4chl5q3KOnZWQ== X-Received: by 2002:a05:6000:1847:b0:21d:c149:263 with SMTP id c7-20020a056000184700b0021dc1490263mr30567246wri.449.1658424086844; Thu, 21 Jul 2022 10:21:26 -0700 (PDT) Received: from henark71.. ([109.76.125.251]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003a2cf1535aasm2455697wme.17.2022.07.21.10.21.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 10:21:26 -0700 (PDT) From: Conor Dooley To: u.kleine-koenig@pengutronix.de Cc: conor.dooley@microchip.com, daire.mcnamara@microchip.com, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org, robh+dt@kernel.org, thierry.reding@gmail.com Subject: [PATCH v7 4/4] MAINTAINERS: add pwm to PolarFire SoC entry Date: Thu, 21 Jul 2022 18:21:10 +0100 Message-Id: <20220721172109.941900-5-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220721172109.941900-1-mail@conchuod.ie> References: <20220721172109.941900-1-mail@conchuod.ie> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Conor Dooley Add the newly introduced pwm driver to the existing PolarFire SoC entry. Signed-off-by: Conor Dooley --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7d14a446df13..c785765c66b7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17510,6 +17510,7 @@ F: drivers/char/hw_random/mpfs-rng.c F: drivers/clk/microchip/clk-mpfs.c F: drivers/mailbox/mailbox-mpfs.c F: drivers/pci/controller/pcie-microchip-host.c +F: drivers/pwm/pwm-microchip-core.c F: drivers/rtc/rtc-mpfs.c F: drivers/soc/microchip/ F: drivers/spi/spi-microchip-core.c