From patchwork Mon Jul 11 15:20:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1654963 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=KC6EbrSp; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LhSHy148dz9s09 for ; Tue, 12 Jul 2022 01:20:30 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230340AbiGKPU1 (ORCPT ); Mon, 11 Jul 2022 11:20:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229470AbiGKPU1 (ORCPT ); Mon, 11 Jul 2022 11:20:27 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41BE7CE00; Mon, 11 Jul 2022 08:20:26 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id eq6so6687960edb.6; Mon, 11 Jul 2022 08:20:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=wTu+cUyVm67/XnEYVu1jCf3AbukYLlOvv0/JzbYxvHI=; b=KC6EbrSpDy73y3WlSzo8MwvTpGUK1Git/9SSp2QIYbQhRPY9niOBB359xQLyKWE+I1 m/ygzgk93Z5hsiEVeaJZSQick6AFccfFVJDE2OgdTLZQd/Re31TLS14mvxq/ZbYRX+gI 7LpJayOonnqIbR89NhbmWQpYoiQwGVUKhzYN/p3A9WfpRPNlNXheppzpdD23TEJ2DE6K tYRcVRaWLEi7TN2bAbtzBKmz11IbFMO8z6XqUKcFkbWJ6CtqeXjACjEMr4sB/sf2hde9 YXlp6SE+z8LJDEbx8/CL3yT8zQFyNXXOk68RB6TVpcsKgTsQ0rpcdFxzMRcsLjuRDBu3 2MJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=wTu+cUyVm67/XnEYVu1jCf3AbukYLlOvv0/JzbYxvHI=; b=XwhR8xIQzHbWKCcPSgcxEH9ugCoRRdfnmvGezuqJ7FGnZahNFYmwJ4nhZDtVRACeQx TKs0bS8Ga7hZ+I+x9yCVMU10FMc3hrIeXS/bz/IXvQjENvPdG6f6OrTvS0+7jALDfSI+ QCG2O2uocO4TYTwTL3fGSsJGqCqNtFxAMMHml+Y3u5WIVsNI5P1yuLz9TBI07U1cWeph F+RWn/SHR5kVTVuxkstkvHur+R+hz9yhwbZISd924rI+4T4pFCPXM3lXV5+KWTFaOTBI M0bKR3BPPRUMwpshGcalOb59N0rBWrY3dnswYsj2/qARxkRgvVX62fHoTaa0xzFaUR09 +xpA== X-Gm-Message-State: AJIora8spXGOqZyX/8oBBY1CZcfQ6fnjM5wBpiR1KaurgJDzc3B4y4y9 7kGSKXranr1T747WqglZPUI= X-Google-Smtp-Source: AGRyM1tnjQQ/SbI6vQBKXIrGHkZgnghzoNqWod2XuAp81gRZjqdSL5DOdZ1gLVkcq8B6fWUK/Z6qAw== X-Received: by 2002:a05:6402:1e8c:b0:43a:c57f:2cbb with SMTP id f12-20020a0564021e8c00b0043ac57f2cbbmr15202685edf.97.1657552824569; Mon, 11 Jul 2022 08:20:24 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id h8-20020aa7cdc8000000b004355998ec1asm4459274edw.14.2022.07.11.08.20.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 08:20:23 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 1/5] dt-bindings: arm: tegra: flowctrl: Convert to json-schema Date: Mon, 11 Jul 2022 17:20:16 +0200 Message-Id: <20220711152020.688461-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Convert the Tegra flow controller bindings from the free-form text format to json-schema. Signed-off-by: Thierry Reding Reviewed-by: Krzysztof Kozlowski --- .../arm/tegra/nvidia,tegra20-flowctrl.txt | 18 -------- .../arm/tegra/nvidia,tegra20-flowctrl.yaml | 41 +++++++++++++++++++ 2 files changed, 41 insertions(+), 18 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.yaml diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt deleted file mode 100644 index a855c1bffc0f..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -NVIDIA Tegra Flow Controller - -Required properties: -- compatible: Should contain one of the following: - - "nvidia,tegra20-flowctrl": for Tegra20 - - "nvidia,tegra30-flowctrl": for Tegra30 - - "nvidia,tegra114-flowctrl": for Tegra114 - - "nvidia,tegra124-flowctrl": for Tegra124 - - "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl": for Tegra132 - - "nvidia,tegra210-flowctrl": for Tegra210 -- reg: Should contain one register range (address and length) - -Example: - - flow-controller@60007000 { - compatible = "nvidia,tegra20-flowctrl"; - reg = <0x60007000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.yaml new file mode 100644 index 000000000000..416739ad8c1e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-flowctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Flow Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-flowctrl + - nvidia,tegra30-flowctrl + - nvidia,tegra114-flowctrl + - nvidia,tegra124-flowctrl + - nvidia,tegra210-flowctrl + + - items: + - const: nvidia,tegra132-flowctrl + - const: nvidia,tegra124-flowctrl + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + flow-controller@60007000 { + compatible = "nvidia,tegra20-flowctrl"; + reg = <0x60007000 0x1000>; + }; From patchwork Mon Jul 11 15:20:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1654965 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=Kne6cbNr; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LhSHz2cJKz9s2R for ; Tue, 12 Jul 2022 01:20:31 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231143AbiGKPU3 (ORCPT ); Mon, 11 Jul 2022 11:20:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229470AbiGKPU2 (ORCPT ); Mon, 11 Jul 2022 11:20:28 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8496CE00; Mon, 11 Jul 2022 08:20:27 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id b11so9378309eju.10; Mon, 11 Jul 2022 08:20:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h5gtdbHKuHCnRNnjB1FkKh1pxZFvIslnnJHoDKnfMjw=; b=Kne6cbNrZk11oZbX1a2QjLJQ8ohuxDpVL2qw+RKE0twX1amma5/Xqpah4tcLWcppA7 Dzkorp23taPHDeyYB1P8eD87qk5LOg0ezlXMQHgUDe6FjMI+bsMcdUSzcHnMKI5AFtZh aMlDIBifGm2u2L0/Y3P+mSd67vxxl+LjauIb5Dqap1lOOhyz3CEB7y5mHgzJKMnUZnBH HUj//YDGDeBcX+Did06O7KzaWNV8RpqkrxWl3plwOyXJGloNRHFcAyTBhChg8uVEy1N+ 5T43dZylmy1T31FVkqCsPqpC79dt4h6czr/ui12BdZcNTW917YhRh+TnrRhjDBhaUF4y IGWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h5gtdbHKuHCnRNnjB1FkKh1pxZFvIslnnJHoDKnfMjw=; b=U8b152JUE2IexMBxt+FSrWyIvCtFdqT0llE4Yf9ivoC2cfZUPL4MguqHsSSD66wb86 blSxwLMQNaZDaFncx9/bxNdgvJqOtW5ARhbmXSke/74YEQ6sRVivT7l51sVHIsD8wJFW 5fFANn+bFj1vJNRLgJjBNgo4rjTin6Tg3gE2L/GuUgX4sfNNNclxE4UqWv5tyNQLn6RC ogjzMbCiSlBz4ea2Nsp7DGjacD4oCeD0FoWDt8S8cGlvbZCvcHlRD/kq5slIVVWKyCrx CxG8uM/uNJhgzPvuU9WbbGLbVzw+k/9kyWZzFDJMTqr3h56A6v4eNuj6ws0/mTZZiGR1 D0Sw== X-Gm-Message-State: AJIora8hc+oZaXWDhLJx3Gyexn91Cc/qt5a/FwSGVml2yRHTaBQ439QE Uf5/+fFlG3G9/jSCX8Bm3zs= X-Google-Smtp-Source: AGRyM1vfmJM7CTKQmWx8yY9R7xPm256zvQyg99TTiwmCOT4a9gLVD4P+mKIKa7tB0lnTJ/TuDt+CVw== X-Received: by 2002:a17:906:84fa:b0:72b:3257:527b with SMTP id zp26-20020a17090684fa00b0072b3257527bmr14944847ejb.477.1657552826314; Mon, 11 Jul 2022 08:20:26 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id l6-20020a170906938600b006fec56c57e6sm2755558ejx.46.2022.07.11.08.20.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 08:20:25 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 2/5] dt-bindings: arm: tegra: ahb: Convert to json-schema Date: Mon, 11 Jul 2022 17:20:17 +0200 Message-Id: <20220711152020.688461-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220711152020.688461-1-thierry.reding@gmail.com> References: <20220711152020.688461-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Convert the NVIDIA Tegra AHB bindings from the free-form text format to json-schema. Signed-off-by: Thierry Reding --- .../bindings/arm/tegra/nvidia,tegra20-ahb.txt | 17 -------- .../arm/tegra/nvidia,tegra20-ahb.yaml | 39 +++++++++++++++++++ 2 files changed, 39 insertions(+), 17 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.yaml diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt deleted file mode 100644 index 9a4295b54539..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt +++ /dev/null @@ -1,17 +0,0 @@ -NVIDIA Tegra AHB - -Required properties: -- compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For - Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain - '"nvidia,-ahb", "nvidia,tegra30-ahb"' where is tegra124, - tegra132, or tegra210. -- reg : Should contain 1 register ranges(address and length). For - Tegra20, Tegra30, and Tegra114 chips, the value must be <0x6000c004 - 0x10c>. For Tegra124, Tegra132 and Tegra210 chips, the value should - be be <0x6000c000 0x150>. - -Example (for a Tegra20 chip): - ahb: ahb@6000c004 { - compatible = "nvidia,tegra20-ahb"; - reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ - }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.yaml new file mode 100644 index 000000000000..6d9baab76258 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-ahb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Thierry Reding + - Jon Hunter + +title: NVIDIA Tegra AHB + +properties: + compatible: + oneOf: + - const: nvidia,tegra20-ahb + - const: nvidia,tegra30-ahb + - items: + - enum: + - nvidia,tegra114-ahb + - nvidia,tegra124-ahb + - nvidia,tegra210-ahb + - const: nvidia,tegra30-ahb + + reg: + maxItems: 1 + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + ahb@6000c004 { + compatible = "nvidia,tegra20-ahb"; + reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ + }; From patchwork Mon Jul 11 15:20:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1654967 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=FB/y12xG; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LhSJ00BP8z9s09 for ; Tue, 12 Jul 2022 01:20:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232236AbiGKPUb (ORCPT ); Mon, 11 Jul 2022 11:20:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229470AbiGKPUa (ORCPT ); Mon, 11 Jul 2022 11:20:30 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78905CE00; Mon, 11 Jul 2022 08:20:29 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id a9so9397297ejf.6; Mon, 11 Jul 2022 08:20:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cnfAJe/WXrON+hzYDcI3/SEXE/mQyPp3cVRsfY90PD0=; b=FB/y12xGxuK3LKR7CMhiOjbf4U6Cbqh/myuQrj57Pdg06IXLL0XjJN9YdTzU9jwH8V Ds+UBeGM8vhc5DSb1+HZEOVy+IPXGnuNOHG/M4k9DdvoB8o5K1W4+au8tKyOBGh9gdij fljQhdT13x8pC1TTKimaMnQhwh/8BdRpwSjLNUEdBL0tOJXrEqPFc40WlUGxnm4ePOpJ dQezddbmGLgOqwf1yR6J+xuE5BUg0HNiTpZvXCQL/f1oB+g1bM1CmxMJFrei1oUI7jmC eXVS4H8OntRPIgndZrtDnJA/0wpG2gcLdznEyzHVMzOsSkko8VA98FmIuOgeX+KtY2+0 hQPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cnfAJe/WXrON+hzYDcI3/SEXE/mQyPp3cVRsfY90PD0=; b=tY3/BJBusnQ8YIkURJSJt/H2YfrXIywN9gFpDQoxYY+xysXSjPG7tJLsj4lmGPBYzK GWhiwdfGko/fOQtoaeuuHn/f1jYa+FZX/RVDYehJ/LUPu8izSRg3CJiArb9pBeuh8IzZ 7ouurTj1l+ZTaLLcJJxSZOaC758o84vbjONWDCoudWX2gJuRWj+8Fc43ZvHte7r/d7oW jZXV8L1WWu/QZY31IHg70AN4CcU3+CcvRG1outdvDoGuPzDvBWSFHzm/Iy0UXFfymaSx MR3+AERTIdoQrnLQ5IHwkGKK36oQVCAhyMGNHzB4uRNeEan44WOQLjHEavyPMce3ReaF kv7Q== X-Gm-Message-State: AJIora/h2qk/91pgYLKfrFIIU69OZqIZ8GnqYGiTNXLJaEBqRRuLT3nH dbZVRAuJ+dGJLuCnHh3u+Pk= X-Google-Smtp-Source: AGRyM1t888CD3hwlRJuWkHHqX87MJ8DaVfnNQUeohIopyGnDJs31B8cj2f482PgDV9pBT4cCTyM6UQ== X-Received: by 2002:a17:906:8479:b0:72a:5610:f151 with SMTP id hx25-20020a170906847900b0072a5610f151mr18806600ejc.125.1657552827945; Mon, 11 Jul 2022 08:20:27 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id 14-20020a170906318e00b00715705dd23asm2767265ejy.89.2022.07.11.08.20.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 08:20:27 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Marc Dietrich Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 3/5] dt-bindings: arm: tegra: nvec: Convert to json-schema Date: Mon, 11 Jul 2022 17:20:18 +0200 Message-Id: <20220711152020.688461-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220711152020.688461-1-thierry.reding@gmail.com> References: <20220711152020.688461-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Convert the NVIDIA embedded controller bindings from the free-form text format to json-schema. Signed-off-by: Thierry Reding Acked-by: Marc Dietrich --- Marc, you authored this binding a long time ago, which makes the default license for this GPL-2.0. However, the preference is for DT bindings to be dual-licensed under the more permissive GPL-2.0-only OR BSD-2-Clause as done in this patch. Do you have any objections to relicensing? Thierry .../bindings/arm/tegra/nvidia,nvec.txt | 21 ----- .../bindings/arm/tegra/nvidia,nvec.yaml | 94 +++++++++++++++++++ 2 files changed, 94 insertions(+), 21 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.yaml diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt deleted file mode 100644 index 5ae601e7f51f..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt +++ /dev/null @@ -1,21 +0,0 @@ -NVIDIA compliant embedded controller - -Required properties: -- compatible : should be "nvidia,nvec". -- reg : the iomem of the i2c slave controller -- interrupts : the interrupt line of the i2c slave controller -- clock-frequency : the frequency of the i2c bus -- gpios : the gpio used for ec request -- slave-addr: the i2c address of the slave controller -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - Tegra20/Tegra30: - - div-clk - - fast-clk - Tegra114: - - div-clk -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - i2c diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.yaml new file mode 100644 index 000000000000..c997faa42c31 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tegra/nvidia,nvec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA compliant embedded controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + const: nvidia,nvec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: divider clock + - description: fast clock + + clock-names: + minItems: 1 + items: + - const: div-clk + - const: fast-clk + + resets: + items: + - description: module reset + + reset-names: + items: + - const: i2c + + clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: frequency of the I2C bus + + request-gpios: + description: phandle to the GPIO used for EC request + + slave-addr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: I2C address of the slave controller + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - clock-frequency + - request-gpios + - slave-addr + +examples: + - | + #include + #include + #include + + nvec@7000c500 { + compatible = "nvidia,nvec"; + reg = <0x7000c500 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <80000>; + request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + slave-addr = <138>; + clocks = <&tegra_car TEGRA20_CLK_I2C3>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + }; From patchwork Mon Jul 11 15:20:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1654969 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=F+ZCFn3/; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LhSJ31JLtz9s09 for ; Tue, 12 Jul 2022 01:20:35 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232241AbiGKPUe (ORCPT ); Mon, 11 Jul 2022 11:20:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229470AbiGKPUd (ORCPT ); Mon, 11 Jul 2022 11:20:33 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 534F04B0E0; Mon, 11 Jul 2022 08:20:31 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id y8so6692554eda.3; Mon, 11 Jul 2022 08:20:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ClRfJRhEpCh3RM9OVDqrADuXPxnO5plmMnxKMpoS2Qg=; b=F+ZCFn3/TibP9VuxuNLappnxlwA6G5LDVjJBT8zeG1XdfQHvTjefIAwv8EEqDF+bMP Jf3nINnQrKGHBTg8Tf9nBCY98/1kiiW4W9b7Wz7nN9lrEtQaTgyxxsWbKPCx/YDs5ZgI MPSGK60a4sCIgGwhpA7i2mLp7y2JA4mVHkzuVgsIqqRK2Tezf3evDcYAUzYXaYbKk1pB Q//kdtDAS7V92eExY9ZW+X7J9JZ7pAW/QceUu3tUGWW+9QX5mZV0Q8vycTD6F0qXb6aL AFR3KKIcyJafRVA7MdhOdu6dHbGb82HFD77+qQqftk0qNHXniVn2pUZqBHsnWoV50R1S RE2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ClRfJRhEpCh3RM9OVDqrADuXPxnO5plmMnxKMpoS2Qg=; b=oiyYManh5IcFNKu/TkDRtI34C3wj40mU8sIkUqjzMzc/CpCLEMpZbLqUDh+Eqo6Zmd AmyL305ulqEbzCHzy5TmWSlzoZc3I14GnVMWnQ7LwSSEnOvEBGAv8TvopXzTpRkKyRak A/MSWurIm2uMwKtVAJO7GuROOmorcORZqQ2Mj5qauhktBcDYoVD3e48j0r6nhL0XqezH XEOPerk17XFiwMsqP6dwTTZazkMB5+ZfFTzrAUoq8dnUwl6XHj6ecqgTaT5w/WUM8lBr V+zlwp1pmVpQntTKQwwbONSuhy/zYU/9jOLKE495Jc87a/vlVWi+/xZvkbEsoUDpUOCU 9IeQ== X-Gm-Message-State: AJIora/ZZNDGop+K+otg5J7JqRuFfRADRzVX8EqUobO45JKhh+e/rom3 w8bwlfK3LUqbWLLIG+e72qdnr8E5IB8= X-Google-Smtp-Source: AGRyM1upFoQ/YMhXR1zqg/LASemd1gWt65N58XmpWGplhtVhVdUkaj3T5D+cLbAbd8rc4qyW+JTvLw== X-Received: by 2002:a05:6402:240a:b0:437:d2b6:3dde with SMTP id t10-20020a056402240a00b00437d2b63ddemr25794043eda.62.1657552829528; Mon, 11 Jul 2022 08:20:29 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id 15-20020a170906318f00b0072b2ffc662esm2774705ejy.156.2022.07.11.08.20.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 08:20:28 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 4/5] dt-bindings: arm: tegra: Revise Tegra20 PMC bindings Date: Mon, 11 Jul 2022 17:20:19 +0200 Message-Id: <20220711152020.688461-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220711152020.688461-1-thierry.reding@gmail.com> References: <20220711152020.688461-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Update the Tegra20 PMC bindings to make use of some advanced json-schema features such as describing list elements or validating the contents of string arrays. While at it, also restructure the pad configuration node schema to make sure it doesn't accidentally match other properties. Signed-off-by: Thierry Reding --- .../arm/tegra/nvidia,tegra20-pmc.yaml | 512 ++++++++++-------- 1 file changed, 282 insertions(+), 230 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 564ae6aaccf7..6894addb3c9a 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# @@ -21,141 +21,134 @@ properties: reg: maxItems: 1 - description: - Offset and length of the register set for the device. + description: Offset and length of the register set for the device. clock-names: items: - const: pclk - const: clk32k_in - description: - Must includes entries pclk and clk32k_in. - pclk is the Tegra clock of that name and clk32k_in is 32KHz clock - input to Tegra. + description: Must includes entries pclk and clk32k_in. pclk is the Tegra + clock of that name and clk32k_in is 32KHz clock input to Tegra. clocks: maxItems: 2 - description: - Must contain an entry for each entry in clock-names. - See ../clocks/clocks-bindings.txt for details. + description: Must contain an entry for each entry in clock-names. See + ../clocks/clocks-bindings.txt for details. '#clock-cells': const: 1 - description: - Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. - PMC also has blink control which allows 32Khz clock output to - Tegra blink pad. - Consumer of PMC clock should specify the desired clock by having - the clock ID in its "clocks" phandle cell with pmc clock provider. - See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC - clock IDs. + description: | + Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. PMC also has blink + control which allows 32Khz clock output to Tegra blink pad. + + Consumer of PMC clock should specify the desired clock by having the + clock ID in its "clocks" phandle cell with PMC clock provider. See + include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC clock IDs. '#interrupt-cells': const: 2 - description: - Specifies number of cells needed to encode an interrupt source. - The value must be 2. + description: Specifies number of cells needed to encode an interrupt + source. interrupt-controller: true nvidia,invert-interrupt: $ref: /schemas/types.yaml#/definitions/flag - description: Inverts the PMU interrupt signal. - The PMU is an external Power Management Unit, whose interrupt output - signal is fed into the PMC. This signal is optionally inverted, and - then fed into the ARM GIC. The PMC is not involved in the detection - or handling of this interrupt signal, merely its inversion. + description: Inverts the PMU interrupt signal. The PMU is an external Power + Management Unit, whose interrupt output signal is fed into the PMC. This + signal is optionally inverted, and then fed into the ARM GIC. The PMC is + not involved in the detection or handling of this interrupt signal, + merely its inversion. nvidia,core-power-req-active-high: $ref: /schemas/types.yaml#/definitions/flag - description: Core power request active-high. + description: core power request active-high nvidia,sys-clock-req-active-high: $ref: /schemas/types.yaml#/definitions/flag - description: System clock request active-high. + description: system clock request active-high nvidia,combined-power-req: $ref: /schemas/types.yaml#/definitions/flag - description: combined power request for CPU and Core. + description: combined power request for CPU and core nvidia,cpu-pwr-good-en: $ref: /schemas/types.yaml#/definitions/flag - description: - CPU power good signal from external PMIC to PMC is enabled. + description: CPU power good signal from external PMIC to PMC is enabled nvidia,suspend-mode: $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2] - description: - The suspend mode that the platform should use. - Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh - Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh - Mode 2 is for LP2, CPU voltage off + description: the suspend mode that the platform should use + oneOf: + - description: LP0, CPU + Core voltage off and DRAM in self-refresh + const: 0 + - description: LP1, CPU voltage off and DRAM in self-refresh + const: 1 + - description: LP2, CPU voltage off + const: 2 nvidia,cpu-pwr-good-time: $ref: /schemas/types.yaml#/definitions/uint32 - description: CPU power good time in uSec. + description: CPU power good time in microseconds nvidia,cpu-pwr-off-time: $ref: /schemas/types.yaml#/definitions/uint32 - description: CPU power off time in uSec. + description: CPU power off time in microseconds nvidia,core-pwr-good-time: $ref: /schemas/types.yaml#/definitions/uint32-array - description: - - Core power good time in uSec. + description: core power good time in microseconds + items: + - description: oscillator stable time + - description: power stable time nvidia,core-pwr-off-time: $ref: /schemas/types.yaml#/definitions/uint32 - description: Core power off time in uSec. + description: core power off time in microseconds nvidia,lp0-vec: $ref: /schemas/types.yaml#/definitions/uint32-array - description: - Starting address and length of LP0 vector. - The LP0 vector contains the warm boot code that is executed - by AVP when resuming from the LP0 state. - The AVP (Audio-Video Processor) is an ARM7 processor and - always being the first boot processor when chip is power on - or resume from deep sleep mode. When the system is resumed - from the deep sleep mode, the warm boot code will restore - some PLLs, clocks and then brings up CPU0 for resuming the - system. + description: | + Starting address and length of LP0 vector. The LP0 vector contains the + warm boot code that is executed by AVP when resuming from the LP0 state. + The AVP (Audio-Video Processor) is an ARM7 processor and always being + the first boot processor when chip is power on or resume from deep sleep + mode. When the system is resumed from the deep sleep mode, the warm boot + code will restore some PLLs, clocks and then brings up CPU0 for resuming + the system. + items: + - description: starting address of LP0 vector + - description: length of LP0 vector i2c-thermtrip: type: object - description: - On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, - hardware-triggered thermal reset will be enabled. + description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode + exists, hardware-triggered thermal reset will be enabled. properties: nvidia,i2c-controller-id: $ref: /schemas/types.yaml#/definitions/uint32 - description: - ID of I2C controller to send poweroff command to PMU. - Valid values are described in section 9.2.148 - "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference - Manual. + description: ID of I2C controller to send poweroff command to PMU. + Valid values are described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" + of the Tegra K1 Technical Reference Manual. nvidia,bus-addr: $ref: /schemas/types.yaml#/definitions/uint32 - description: Bus address of the PMU on the I2C bus. + description: bus address of the PMU on the I2C bus nvidia,reg-addr: $ref: /schemas/types.yaml#/definitions/uint32 - description: PMU I2C register address to issue poweroff command. + description: PMU I2C register address to issue poweroff command nvidia,reg-data: $ref: /schemas/types.yaml#/definitions/uint32 - description: Poweroff command to write to PMU. + description: power-off command to write to PMU nvidia,pinmux-id: $ref: /schemas/types.yaml#/definitions/uint32 - description: - Pinmux used by the hardware when issuing Poweroff command. - Defaults to 0. Valid values are described in section 12.5.2 - "Pinmux Support" of the Tegra4 Technical Reference Manual. + description: Pinmux used by the hardware when issuing power-off command. + Defaults to 0. Valid values are described in section 12.5.2 "Pinmux + Support" of the Tegra4 Technical Reference Manual. required: - nvidia,i2c-controller-id @@ -165,65 +158,91 @@ properties: additionalProperties: false + core-domain: + type: object + description: The vast majority of hardware blocks of Tegra SoC belong to a + core power domain, which has a dedicated voltage rail that powers the + blocks. + + properties: + operating-points-v2: + description: Should contain level, voltages and opp-supported-hw + property. The supported-hw is a bitfield indicating SoC speedo or + process ID mask. + + "#power-domain-cells": + const: 0 + + required: + - operating-points-v2 + - "#power-domain-cells" + + additionalProperties: false + + core-supply: + description: phandle to voltage regulator connected to the SoC core power + rail + powergates: type: object description: | - This node contains a hierarchy of power domain nodes, which should - match the powergates on the Tegra SoC. Each powergate node - represents a power-domain on the Tegra SoC that can be power-gated - by the Tegra PMC. - Hardware blocks belonging to a power domain should contain - "power-domains" property that is a phandle pointing to corresponding - powergate node. - The name of the powergate node should be one of the below. Note that - not every powergate is applicable to all Tegra devices and the following - list shows which powergates are applicable to which devices. - Please refer to Tegra TRM for mode details on the powergate nodes to - use for each power-gate block inside Tegra. - Name Description Devices Applicable - 3d 3D Graphics Tegra20/114/124/210 - 3d0 3D Graphics 0 Tegra30 - 3d1 3D Graphics 1 Tegra30 - aud Audio Tegra210 - dfd Debug Tegra210 - dis Display A Tegra114/124/210 - disb Display B Tegra114/124/210 - heg 2D Graphics Tegra30/114/124/210 - iram Internal RAM Tegra124/210 - mpe MPEG Encode All - nvdec NVIDIA Video Decode Engine Tegra210 - nvjpg NVIDIA JPEG Engine Tegra210 - pcie PCIE Tegra20/30/124/210 - sata SATA Tegra30/124/210 - sor Display interfaces Tegra124/210 - ve2 Video Encode Engine 2 Tegra210 - venc Video Encode Engine All - vdec Video Decode Engine Tegra20/30/114/124 - vic Video Imaging Compositor Tegra124/210 - xusba USB Partition A Tegra114/124/210 - xusbb USB Partition B Tegra114/124/210 - xusbc USB Partition C Tegra114/124/210 + This node contains a hierarchy of power domain nodes, which should match + the powergates on the Tegra SoC. Each powergate node represents a power- + domain on the Tegra SoC that can be power-gated by the Tegra PMC. + + Hardware blocks belonging to a power domain should contain "power-domains" + property that is a phandle pointing to corresponding powergate node. + + The name of the powergate node should be one of the below. Note that not + every powergate is applicable to all Tegra devices and the following list + shows which powergates are applicable to which devices. + + Please refer to Tegra TRM for mode details on the powergate nodes to use + for each power-gate block inside Tegra. + + Name Description Devices Applicable + -------------------------------------------------------------- + 3d 3D Graphics Tegra20/114/124/210 + 3d0 3D Graphics 0 Tegra30 + 3d1 3D Graphics 1 Tegra30 + aud Audio Tegra210 + dfd Debug Tegra210 + dis Display A Tegra114/124/210 + disb Display B Tegra114/124/210 + heg 2D Graphics Tegra30/114/124/210 + iram Internal RAM Tegra124/210 + mpe MPEG Encode All + nvdec NVIDIA Video Decode Engine Tegra210 + nvjpg NVIDIA JPEG Engine Tegra210 + pcie PCIE Tegra20/30/124/210 + sata SATA Tegra30/124/210 + sor Display interfaces Tegra124/210 + ve2 Video Encode Engine 2 Tegra210 + venc Video Encode Engine All + vdec Video Decode Engine Tegra20/30/114/124 + vic Video Imaging Compositor Tegra124/210 + xusba USB Partition A Tegra114/124/210 + xusbb USB Partition B Tegra114/124/210 + xusbc USB Partition C Tegra114/124/210 patternProperties: "^[a-z0-9]+$": type: object - - patternProperties: + properties: clocks: minItems: 1 - maxItems: 8 - description: - Must contain an entry for each clock required by the PMC - for controlling a power-gate. - See ../clocks/clock-bindings.txt document for more details. + maxItems: 10 + description: | + Must contain an entry for each clock required by the PMC for + controlling a powergate. See ../clocks/clock-bindings.txt document + for more details. resets: minItems: 1 maxItems: 8 - description: - Must contain an entry for each reset required by the PMC - for controlling a power-gate. - See ../reset/reset.txt for more details. + description: | + Must contain an entry for each reset required by the PMC for + controlling a powergate. See ../reset/reset.txt for more details. '#power-domain-cells': const: 0 @@ -236,96 +255,84 @@ properties: additionalProperties: false -patternProperties: - "^[a-f0-9]+-[a-f0-9]+$": + pinmux: type: object - description: - This is a Pad configuration node. On Tegra SOCs a pad is a set of - pins which are configured as a group. The pin grouping is a fixed - attribute of the hardware. The PMC can be used to set pad power state - and signaling voltage. A pad can be either in active or power down mode. - The support for power state and signaling voltage configuration varies - depending on the pad in question. 3.3V and 1.8V signaling voltages - are supported on pins where software controllable signaling voltage - switching is available. - - The pad configuration state nodes are placed under the pmc node and they - are referred to by the pinctrl client properties. For more information - see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. - The pad name should be used as the value of the pins property in pin - configuration nodes. - - The following pads are present on Tegra124 and Tegra132 - audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic, - hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl, - sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias. - - The following pads are present on Tegra210 - audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, - debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi, - hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, - sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias. - properties: - pins: - $ref: /schemas/types.yaml#/definitions/string - description: Must contain name of the pad(s) to be configured. + status: true - low-power-enable: - $ref: /schemas/types.yaml#/definitions/flag - description: Configure the pad into power down mode. + additionalProperties: + type: object + description: | + This is a pad configuration node. On Tegra SoCs a pad is a set of pins + which are configured as a group. The pin grouping is a fixed attribute + of the hardware. The PMC can be used to set pad power state and + signaling voltage. A pad can be either in active or power down mode. + The support for power state and signaling voltage configuration varies + depending on the pad in question. 3.3V and 1.8V signaling voltages are + supported on pins where software controllable signaling voltage + switching is available. - low-power-disable: - $ref: /schemas/types.yaml#/definitions/flag - description: Configure the pad into active mode. + The pad configuration state nodes are placed under the pmc node and + they are referred to by the pinctrl client properties. For more + information see: - power-source: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or - TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. - The values are defined in - include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. - Power state can be configured on all Tegra124 and Tegra132 - pads. None of the Tegra124 or Tegra132 pads support signaling - voltage switching. - All of the listed Tegra210 pads except pex-cntrl support power - state configuration. Signaling voltage switching is supported - on below Tegra210 pads. - audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, - sdmmc3, spi, spi-hv, and uart. + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - required: - - pins + The pad name should be used as the value of the pins property in pin + configuration nodes. - additionalProperties: false + The following pads are present on Tegra124 and Tegra132: - core-domain: - type: object - description: | - The vast majority of hardware blocks of Tegra SoC belong to a - Core power domain, which has a dedicated voltage rail that powers - the blocks. + audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, + hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, + pex-cntrl, sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, + usb_bias - properties: - operating-points-v2: - description: - Should contain level, voltages and opp-supported-hw property. - The supported-hw is a bitfield indicating SoC speedo or process - ID mask. + The following pads are present on Tegra210: - "#power-domain-cells": - const: 0 + audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, + debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, + hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, + sdmmc1, sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias - required: - - operating-points-v2 - - "#power-domain-cells" + properties: + pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: Must contain name of the pad(s) to be configured. - additionalProperties: false + low-power-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: Configure the pad into power down mode. - core-supply: - description: - Phandle to voltage regulator connected to the SoC Core power rail. + low-power-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: Configure the pad into active mode. + + power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or + TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. The + values are defined in: + + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h + + Power state can be configured on all Tegra124 and Tegra132 pads. + None of the Tegra124 or Tegra132 pads support signaling voltage + switching. All of the listed Tegra210 pads except pex-cntrl support + power state configuration. Signaling voltage switching is supported + on the following Tegra210 pads: + + audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, sdmmc3, + spi, spi-hv, uart + + phandle: + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - pins + + additionalProperties: false required: - compatible @@ -334,6 +341,52 @@ required: - clocks - '#clock-cells' +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra124-pmc + then: + properties: + pinmux: + properties: + status: true + + additionalProperties: + type: object + properties: + pins: + items: + enum: [ audio, bb, cam, comp, csia, csb, cse, dsi, dsib, + dsic, dsid, hdmi, hsic, hv, lvds, mipi-bias, nand, + pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, + sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, + usb_bias ] + + - if: + properties: + compatible: + contains: + const: nvidia,tegra210-pmc + then: + properties: + pinmux: + properties: + status: true + + additionalProperties: + type: object + properties: + pins: + items: + enum: [ audio, audio-hv, cam, csia, csib, csic, csid, csie, + csif, dbg, debug-nonao, dmic, dp, dsi, dsib, dsic, + dsid, emmc, emmc2, gpio, hdmi, hsic, lvds, mipi-bias, + pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, + sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, + usb-bias ] + additionalProperties: false dependencies: @@ -343,47 +396,46 @@ dependencies: examples: - | - #include #include #include - tegra_pmc: pmc@7000e400 { - compatible = "nvidia,tegra210-pmc"; - reg = <0x7000e400 0x400>; - core-supply = <®ulator>; - clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - #clock-cells = <1>; - - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <0>; - nvidia,cpu-pwr-off-time = <0>; - nvidia,core-pwr-good-time = <4587 3876>; - nvidia,core-pwr-off-time = <39065>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - pd_core: core-domain { - operating-points-v2 = <&core_opp_table>; - #power-domain-cells = <0>; - }; - - powergates { - pd_audio: aud { - clocks = <&tegra_car TEGRA210_CLK_APE>, - <&tegra_car TEGRA210_CLK_APB2APE>; - resets = <&tegra_car 198>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_xusbss: xusba { - clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; - resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - }; + pmc@7000e400 { + compatible = "nvidia,tegra210-pmc"; + reg = <0x7000e400 0x400>; + core-supply = <®ulator>; + clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; + + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + + pd_core: core-domain { + operating-points-v2 = <&core_opp_table>; + #power-domain-cells = <0>; + }; + + powergates { + pd_audio: aud { + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + resets = <&tegra_car 198>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_xusbss: xusba { + clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; + resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + }; }; From patchwork Mon Jul 11 15:20:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1654972 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=q5lmrfLR; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LhSJ431sDz9s1l for ; Tue, 12 Jul 2022 01:20:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231625AbiGKPUe (ORCPT ); Mon, 11 Jul 2022 11:20:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232239AbiGKPUe (ORCPT ); Mon, 11 Jul 2022 11:20:34 -0400 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13F45422FA; Mon, 11 Jul 2022 08:20:33 -0700 (PDT) Received: by mail-ej1-x633.google.com with SMTP id l23so9395269ejr.5; Mon, 11 Jul 2022 08:20:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5b8UWOyZ49xxzDiCA8+Xk3JKrtP0H16bFd6219QDvZA=; b=q5lmrfLR3ikjlAM0i1sUYFRVqQVSRofRgu7G4fnZ493LqjJ8qoMHiGBWWLjg+A4l5b QnKq/w0OZ3oE+mb5oa37llLYTvi90KQfG9vL3x+0VHTG8ixisEHFogjR07QHtxRfFZpG MxjzrRSq0TxQDZf50/VnvQiTfsCOZHfx60YaJgctTqEyhmFikNcry7elzdUnMrjU3UlQ J4vLjZtp8gyaETODWnuNeETjX3Jv2iURr8G2Mwz4xMJNiDx1htdR1lqMYZQYObRyJnd4 g0YdHn1vDc6plunCsJaR2I6qE4kR3vQSUpF5p5cTb8PPw/k/4WzjOmpD1KtS9f8CUIGO rVqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5b8UWOyZ49xxzDiCA8+Xk3JKrtP0H16bFd6219QDvZA=; b=7hFAZ9f50BFfzz6K8ar2s7ULsaXcxQnK7T52RIVFenlEzwXrMgfyn172tDBTWAKHhz ksMUPtSsX95X4EGo9mjcKHis6vstSzaT6YniszQFuWnnV+9SGFkMX7p27GSdWFlv/ALe 7AXtJA1l3xIb+cuRrok2UtcvJBS/QfbZKqtVjg2tnh7zwQJyDrpCE0lXB4uTZlLr0wX5 Lih0+9MMwY1JLTdgyOvFjwXgJln3sPQ96yzNCeDcP8uWvQW1SibehGa2otUcG+cvz4hG LtdQIZBRwV3xyLKppW632YRQrUkwdTLPxMRtET2k3M6ElFnpiWImlUaeEneaVKihRXuI J+kA== X-Gm-Message-State: AJIora/JHppcB7VevBYs/40hvLIiuGnMCBvPXkpoj34M4vN8A3ky0Ig3 edJByyULA39QJZE9p+OK9L8= X-Google-Smtp-Source: AGRyM1uZQiL59BUxwlBraRLkU617JdLwElH7er6ODVAfU4DSUbwAmDnABHuJ2ZONcQuHXbfkLKo21w== X-Received: by 2002:a17:907:72ce:b0:722:e1a5:164c with SMTP id du14-20020a17090772ce00b00722e1a5164cmr19519590ejc.111.1657552831515; Mon, 11 Jul 2022 08:20:31 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id fd15-20020a056402388f00b0043adc6552d6sm1060373edb.20.2022.07.11.08.20.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 08:20:30 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 5/5] dt-bindings: arm: tegra: Add missing compatible strings Date: Mon, 11 Jul 2022 17:20:20 +0200 Message-Id: <20220711152020.688461-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220711152020.688461-1-thierry.reding@gmail.com> References: <20220711152020.688461-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The Nyan Blaze and Nyan Big, as well as Jetson Nano (P3450-0000), Darcy (P2894-0050-A08) and Pixel C (Smaug) were never mentioned. Add them. While at it, also fix a typo in the compatible string for Apalis Tegra30 v1.1 evaluation board. Signed-off-by: Thierry Reding Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/tegra.yaml | 50 ++++++++++++++++++- 1 file changed, 48 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 49841ca272ee..187d832a14ac 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -114,6 +114,33 @@ properties: - const: toradex,apalis-tk1-v1.2 - const: toradex,apalis-tk1 - const: nvidia,tegra124 + - items: + - const: google,nyan-big-rev7 + - const: google,nyan-big-rev6 + - const: google,nyan-big-rev5 + - const: google,nyan-big-rev4 + - const: google,nyan-big-rev3 + - const: google,nyan-big-rev2 + - const: google,nyan-big-rev1 + - const: google,nyan-big-rev0 + - const: google,nyan-big + - const: google,nyan + - const: nvidia,tegra124 + - items: + - const: google,nyan-blaze-rev10 + - const: google,nyan-blaze-rev9 + - const: google,nyan-blaze-rev8 + - const: google,nyan-blaze-rev7 + - const: google,nyan-blaze-rev6 + - const: google,nyan-blaze-rev5 + - const: google,nyan-blaze-rev4 + - const: google,nyan-blaze-rev3 + - const: google,nyan-blaze-rev2 + - const: google,nyan-blaze-rev1 + - const: google,nyan-blaze-rev0 + - const: google,nyan-blaze + - const: google,nyan + - const: nvidia,tegra124 - items: - enum: - nvidia,norrin @@ -121,11 +148,30 @@ properties: - const: nvidia,tegra124 - items: - enum: - - nvidia,darcy - nvidia,p2371-0000 - nvidia,p2371-2180 - nvidia,p2571 - - nvidia,p2894-0050-a08 + - const: nvidia,tegra210 + - description: NVIDIA Jetson Nano + items: + - const: nvidia,p3450-0000 + - const: nvidia,tegra210 + - description: NVIDIA Shield TV + items: + - const: nvidia,p2894-0050-a08 + - const: nvidia,darcy + - const: nvidia,tegra210 + - description: Google Pixel C + items: + - const: google,smaug-rev8 + - const: google,smaug-rev7 + - const: google,smaug-rev6 + - const: google,smaug-rev5 + - const: google,smaug-rev4 + - const: google,smaug-rev3 + - const: google,smaug-rev2 + - const: google,smaug-rev1 + - const: google,smaug - const: nvidia,tegra210 - description: Jetson TX2 Developer Kit items: