From patchwork Wed Jul 6 21:32:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1653222 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=VL+ggLiQ; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LdXpC2wQzz9s2R for ; Thu, 7 Jul 2022 07:33:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234048AbiGFVdG (ORCPT ); Wed, 6 Jul 2022 17:33:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232789AbiGFVdF (ORCPT ); Wed, 6 Jul 2022 17:33:05 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75B1C27145; Wed, 6 Jul 2022 14:33:04 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id bk26so8686511wrb.11; Wed, 06 Jul 2022 14:33:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Fg/phBGKhZr7UrHQOPXuoLQtqwIeUVgaOU3TILEF07Q=; b=VL+ggLiQ9rzXiwBSovopuHxOXFel3Xhv127KxNiPzpYMOUJGAq+aC25L3/C2QxYPt8 s7r3wWaozRrfkZiwdDg3GQBXS/H75PEcXUmFh0ChuFF+3SSP3Hx5L3JkAsWcA/hUL9kx Y3zFnDEJbukzWApw1yYlwXS73Ds71s0tvUjmt70PR62inqOFeQmibnDEWomQAc+s9Ecr urZ1N24xEILx87Rxw7s9lAQ6DKF2D20GRm/0JCfTxpqBWopBoNikhutdYSy2LErSNKVA bvrcrJtujRmjOaZ3JzlnPM0ml5yiUu7h69htmTzz8qQuIA1EVS/ubOPxR7bDRWdelgc3 SXPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Fg/phBGKhZr7UrHQOPXuoLQtqwIeUVgaOU3TILEF07Q=; b=o6LDYY8x9ff380qtV9V9UneRIWve5XeGLyHRZFWq+c9XVCSXdcBZbF/c7Ab6XNe5s3 XnXrxxEBwqxJDyF4LdI02wspYITnC9C/wu3bX7AqTS3Jt+C7eE/60YeF05tjmnARnMle Hiv+3LH6Nyv6Q+rpE5xUzE9WpCLbMKMIwMJfZw1BMWi8q7cTw9P3odQDRx7Du8BADeEB l/C2VPsT4TaPmsg9sThl2oAL5alOvI1J/es/2WO3sr/uqosi+47LOmj/N7MPN81TrFl1 2Eho3DdeGXnqyxuVXixieOeSP8ey1ruCVgwTElMD2wlNDjbMLRnWNbsaXZ1j/kYFtNGS 8Cmg== X-Gm-Message-State: AJIora9cIlpwflEnYPNKtPszQWC43m0gR/OBiiciosVCX2B5AIX13eC3 xPRXoLySjaIsbTtjBxI2HNw= X-Google-Smtp-Source: AGRyM1uysZZkfTar5qcs0P2RtQiH2zA7twOcPZSQdqOuscQRra/ocxGsMPqKorDoXbhv6GmCUB05Rg== X-Received: by 2002:adf:f9ce:0:b0:21d:68b7:e7af with SMTP id w14-20020adff9ce000000b0021d68b7e7afmr18658227wrr.236.1657143183028; Wed, 06 Jul 2022 14:33:03 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id bd16-20020a05600c1f1000b003a18ecfcd8csm18092287wmb.19.2022.07.06.14.33.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 14:33:02 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Date: Wed, 6 Jul 2022 23:32:47 +0200 Message-Id: <20220706213255.1473069-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220706213255.1473069-1-thierry.reding@gmail.com> References: <20220706213255.1473069-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Add power domain IDs for the four Multi-Gigabit Ethernet (MGBE) power partitions found on NVIDIA Tegra234. Signed-off-by: Bhadram Varka Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- include/dt-bindings/power/tegra234-powergate.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h index f610eee9bce8..df1d4dd8dcf3 100644 --- a/include/dt-bindings/power/tegra234-powergate.h +++ b/include/dt-bindings/power/tegra234-powergate.h @@ -18,5 +18,6 @@ #define TEGRA234_POWER_DOMAIN_MGBEA 17U #define TEGRA234_POWER_DOMAIN_MGBEB 18U #define TEGRA234_POWER_DOMAIN_MGBEC 19U +#define TEGRA234_POWER_DOMAIN_MGBED 20U #endif From patchwork Wed Jul 6 21:32:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1653224 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=Wa3nZRhL; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LdXpJ3FyTz9s2R for ; Thu, 7 Jul 2022 07:33:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232789AbiGFVdL (ORCPT ); Wed, 6 Jul 2022 17:33:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234229AbiGFVdI (ORCPT ); Wed, 6 Jul 2022 17:33:08 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75C6D27145; Wed, 6 Jul 2022 14:33:06 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id q9so23753828wrd.8; Wed, 06 Jul 2022 14:33:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hsb46ZR+iAjqJM/8jf9bwePKdQ+/VlInmNQnXhNixRE=; b=Wa3nZRhLF9IHRHbwDFrn1FWmzoVxEe86/4eIaRBlZPnYa5XrWxF/wPux8zCxjedEgX zH1luibjn/6XoZOXRkl5XC0whSxrvaFZo+JuwIICukmnAwDQZMfRlvkbc5doIjsm1ama 7h4KJmSIRyZSa9W9N7Xnbd2CNfrAHpxp6oNcSfEcxFv8p/lsX52mjKaMg/8jr/gtfbZN UF+j43kPXekINVTaVB/PdDGC19QKOMxxvT1gPSgcbGanJh4Ig+l1p1hm5YiwCfNWggO4 ZQOk+HJN9M1+QhScQ8xgJJJgjLia/EpxdF/7UG2PlrgNRUSlVB0TzmY0SL9mNNHdUB8f rGJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hsb46ZR+iAjqJM/8jf9bwePKdQ+/VlInmNQnXhNixRE=; b=qdB3Kx/V/blknejwRb405pNCJ0iIbDUS3DeLPstAm/vWoBzrapJtmS5PpW1wL5zqcR wO9cjQg/ddg+AK/qyy6YER/2uJsjfxlTDbtnvRRW7QTXH883tnfrdrPrzrBZHieGyg1v ChIt7VJAKqbJSSFIhpvsroWeKmrqaKQQuE2vD4Bqi7BHxOFQtQLMIvTdoGZaFIu6CTjs HfURNjjpCWCH9KXoKoEBl7zMjj1EOJMatlkhS6nPGiB+7VVv0F6rMN8127n7bgc2791I uN/wI8E59Rdf5cXUgTuAoTkxFlqeS/UNpFf24F9wWa+AJsm/nMTatsm+pv2TxDLDDmlE 3phA== X-Gm-Message-State: AJIora/FUStG3x28kxcQGgqo1qa3CWqdD7Jfg4g+Kdd7XX1fiYjK5e2K FtK4Io3Nyj+IrIHIgLtX64A= X-Google-Smtp-Source: AGRyM1vyW79xSHqhJZ9b3VpkkIdExBoC880cCzeYt+jyEemqyowpVRmIY5gtv1pfkD4tsrPnjWxvNw== X-Received: by 2002:adf:fcc6:0:b0:21d:8093:1b5c with SMTP id f6-20020adffcc6000000b0021d80931b5cmr2875478wrs.41.1657143184999; Wed, 06 Jul 2022 14:33:04 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id i30-20020a1c541e000000b003a032c88877sm23140851wmb.15.2022.07.06.14.33.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 14:33:03 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 2/9] dt-bindings: Add Tegra234 MGBE clocks and resets Date: Wed, 6 Jul 2022 23:32:48 +0200 Message-Id: <20220706213255.1473069-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220706213255.1473069-1-thierry.reding@gmail.com> References: <20220706213255.1473069-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Add the clocks and resets used by the Multi-Gigabit Ethernet (MGBE) hardware found on NVIDIA Tegra234 SoCs. Signed-off-by: Bhadram Varka Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- include/dt-bindings/clock/tegra234-clock.h | 101 +++++++++++++++++++++ include/dt-bindings/reset/tegra234-reset.h | 8 ++ 2 files changed, 109 insertions(+) diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 6fbe66063066..b8c64e0f120c 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -174,10 +174,111 @@ #define TEGRA234_CLK_PEX1_C5_CORE 225U /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ #define TEGRA234_CLK_PLLC4 237U +/** @brief RX clock recovered from MGBE0 lane input */ +#define TEGRA234_CLK_MGBE0_RX_INPUT 248U +/** @brief RX clock recovered from MGBE1 lane input */ +#define TEGRA234_CLK_MGBE1_RX_INPUT 249U +/** @brief RX clock recovered from MGBE2 lane input */ +#define TEGRA234_CLK_MGBE2_RX_INPUT 250U +/** @brief RX clock recovered from MGBE3 lane input */ +#define TEGRA234_CLK_MGBE3_RX_INPUT 251U /** @brief 32K input clock provided by PMIC */ #define TEGRA234_CLK_CLK_32K 289U +/** @brief Monitored branch of MBGE0 RX input clock */ +#define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U +/** @brief Monitored branch of MBGE1 RX input clock */ +#define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U +/** @brief Monitored branch of MBGE2 RX input clock */ +#define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U +/** @brief Monitored branch of MBGE3 RX input clock */ +#define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U +/** @brief Monitored branch of MGBE0 RX PCS mux output */ +#define TEGRA234_CLK_MGBE0_RX_PCS_M 361U +/** @brief Monitored branch of MGBE1 RX PCS mux output */ +#define TEGRA234_CLK_MGBE1_RX_PCS_M 362U +/** @brief Monitored branch of MGBE2 RX PCS mux output */ +#define TEGRA234_CLK_MGBE2_RX_PCS_M 363U +/** @brief Monitored branch of MGBE3 RX PCS mux output */ +#define TEGRA234_CLK_MGBE3_RX_PCS_M 364U +/** @brief RX PCS clock recovered from MGBE0 lane input */ +#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U +/** @brief RX PCS clock recovered from MGBE1 lane input */ +#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U +/** @brief RX PCS clock recovered from MGBE2 lane input */ +#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U +/** @brief RX PCS clock recovered from MGBE3 lane input */ +#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U +/** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE0_RX_PCS 373U +/** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE0_TX 374U +/** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE0_TX_PCS 375U +/** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U +/** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE0_MAC 377U +/** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */ +#define TEGRA234_CLK_MGBE0_MACSEC 378U +/** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE0_EEE_PCS 379U +/** @brief GBE_UPHY_MGBE0_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE0_APP 380U +/** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE0_PTP_REF 381U +/** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE1_RX_PCS 382U +/** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE1_TX 383U +/** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE1_TX_PCS 384U +/** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U +/** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE1_MAC 386U +/** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE1_EEE_PCS 388U +/** @brief GBE_UPHY_MGBE1_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE1_APP 389U +/** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE1_PTP_REF 390U +/** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE2_RX_PCS 391U +/** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE2_TX 392U +/** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE2_TX_PCS 393U +/** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U +/** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE2_MAC 395U +/** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE2_EEE_PCS 397U +/** @brief GBE_UPHY_MGBE2_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE2_APP 398U +/** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE2_PTP_REF 399U +/** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE3_RX_PCS 400U +/** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE3_TX 401U +/** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE3_TX_PCS 402U +/** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U +/** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE3_MAC 404U +/** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */ +#define TEGRA234_CLK_MGBE3_MACSEC 405U +/** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE3_EEE_PCS 406U +/** @brief GBE_UPHY_MGBE3_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE3_APP 407U +/** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE3_PTP_REF 408U /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ #define TEGRA234_CLK_AZA_2XBIT 457U /** @brief aza_2xbitclk / 2 (aza_bitclk) */ #define TEGRA234_CLK_AZA_BIT 458U + #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 4f72ed1c2320..92c94ee1f13d 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -31,6 +31,12 @@ #define TEGRA234_RESET_I2C7 33U #define TEGRA234_RESET_I2C8 34U #define TEGRA234_RESET_I2C9 35U +#define TEGRA234_RESET_MGBE0_PCS 45U +#define TEGRA234_RESET_MGBE0_MAC 46U +#define TEGRA234_RESET_MGBE1_PCS 49U +#define TEGRA234_RESET_MGBE1_MAC 50U +#define TEGRA234_RESET_MGBE2_PCS 53U +#define TEGRA234_RESET_MGBE2_MAC 54U #define TEGRA234_RESET_PEX2_CORE_10 56U #define TEGRA234_RESET_PEX2_CORE_10_APB 57U #define TEGRA234_RESET_PEX2_COMMON_APB 58U @@ -45,6 +51,8 @@ #define TEGRA234_RESET_QSPI0 76U #define TEGRA234_RESET_QSPI1 77U #define TEGRA234_RESET_SDMMC4 85U +#define TEGRA234_RESET_MGBE3_PCS 87U +#define TEGRA234_RESET_MGBE3_MAC 88U #define TEGRA234_RESET_UARTA 100U #define TEGRA234_RESET_PEX0_CORE_0 116U #define TEGRA234_RESET_PEX0_CORE_1 117U From patchwork Wed Jul 6 21:32:49 2022 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[2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id f190-20020a1c38c7000000b0039c5328ad92sm23605784wma.41.2022.07.06.14.33.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 14:33:05 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients Date: Wed, 6 Jul 2022 23:32:49 +0200 Message-Id: <20220706213255.1473069-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220706213255.1473069-1-thierry.reding@gmail.com> References: <20220706213255.1473069-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Add the memory client and stream ID definitions for the Multi-Gigabit Ethernet (MGBE) hardware found on NVIDIA Tegra234 SoCs. Signed-off-by: Bhadram Varka Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- include/dt-bindings/memory/tegra234-mc.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index 35491bacbc86..8c785c1937f2 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -12,11 +12,15 @@ #define TEGRA234_SID_APE 0x02 #define TEGRA234_SID_HDA 0x03 #define TEGRA234_SID_GPCDMA 0x04 +#define TEGRA234_SID_MGBE 0x06 #define TEGRA234_SID_PCIE0 0x12 #define TEGRA234_SID_PCIE4 0x13 #define TEGRA234_SID_PCIE5 0x14 #define TEGRA234_SID_PCIE6 0x15 #define TEGRA234_SID_PCIE9 0x1f +#define TEGRA234_SID_MGBE_VF1 0x49 +#define TEGRA234_SID_MGBE_VF2 0x4a +#define TEGRA234_SID_MGBE_VF3 0x4b /* NISO1 stream IDs */ #define TEGRA234_SID_SDMMC4 0x02 @@ -63,8 +67,24 @@ #define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 /* PCIE7r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 +/* MGBE0 read client */ +#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58 +/* MGBEB read client */ +#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59 +/* MGBEC read client */ +#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a +/* MGBED read client */ +#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b +/* MGBE0 write client */ +#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c +/* MGBEB write client */ +#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f +/* MGBEC write client */ +#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61 /* sdmmcd memory read client */ #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 +/* MGBED write client */ +#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65 /* sdmmcd memory write client */ #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 /* EQOS read client */ From patchwork Wed Jul 6 21:32:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1653229 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=I4pmdpKo; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LdXpN3VTqz9s2R for ; Thu, 7 Jul 2022 07:33:16 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234606AbiGFVdN (ORCPT ); Wed, 6 Jul 2022 17:33:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234240AbiGFVdM (ORCPT ); Wed, 6 Jul 2022 17:33:12 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E25E27145; Wed, 6 Jul 2022 14:33:10 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id q9so23754028wrd.8; Wed, 06 Jul 2022 14:33:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HVZSEC+VenCeIo/8yTgKOXSfNE5opDjFHGiQ9pUUIZQ=; b=I4pmdpKoYpzTo0R0cK3zBQTv7GMk/4JjvJX/Bb7G70Pe55svcXBfQZq0IdjGCiskV+ P0vZwx5cPexjitW+Q/8VvWOU5bhjJr45veMEq6CKbJEfePqNrDgTV4nArcAwQ/e50HU/ JkgzzQ3H+DmLFLbxpg3WIP4ZXMkB2YPswlb5tGJAnJHD3C2fKVx8YDR8uvTDy4G8e5lJ 3Df1EbJ9Luqo4LL/9q+aaHU8SDImw+drJ1Zt+KcZ8czRWWe5KTH+9oqhiMtSSM3J6+CO X6jWftEf3Mi2N7ni+hju2Ju1/lJYkSh7xcazJbarF6HP3ZJMzmAEl2Mv8qdqk2z9bBGT CjPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HVZSEC+VenCeIo/8yTgKOXSfNE5opDjFHGiQ9pUUIZQ=; b=Ytllck8HuLi2kXiHLxuVCwHZdN55jlMXUrc4WFfAHmTUrROZ4la0pw0JhrjSwJDJ86 CBnpoOMjD98NvgWk4+Cev6Kqy+nE6pVzVeA6dDV+s5dY6wF/KLBoAyVp3Hhbm9LD62VD wjg7+gSh7Ruba8JBK1V/Q2PKGQKs35t85RG3CpYzTmdgqqwhh8EH1bQjFEXHghvm7tzD TZeVcx/rPr49akFy/8KPXi7trGsDdxOnEVZX1BDEuj4t9QFbHuYTJPTqL27470zN/5BJ IWtQBFgl/A7nhynHk4czSSUMfO3hyDxjkrFbb5hyjsQq8qfu4xa9eCke7VEEvjC9gyUK Uudg== X-Gm-Message-State: AJIora/4T5QPksCSLyYUw1WCkRkOosYUeaHKcL+lIlQbJolZD1k9RXRk H/iOzMKHxuoY2akYwIvGiuo= X-Google-Smtp-Source: AGRyM1vubie3i/VEfKiH+iR/HW2Dc7ZjSUlOMm50+gV42c6qtc1hWOltqsrSGwR6eWjVTiJj8LklRQ== X-Received: by 2002:a05:6000:1152:b0:21d:7646:a976 with SMTP id d18-20020a056000115200b0021d7646a976mr9219831wrx.416.1657143190468; Wed, 06 Jul 2022 14:33:10 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id j18-20020a05600c191200b003973ea7e725sm30611255wmq.0.2022.07.06.14.33.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 14:33:09 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski Cc: Thierry Reding , Jon Hunter , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH v3 5/9] dt-bindings: net: Add Tegra234 MGBE Date: Wed, 6 Jul 2022 23:32:51 +0200 Message-Id: <20220706213255.1473069-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220706213255.1473069-1-thierry.reding@gmail.com> References: <20220706213255.1473069-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Bhadram Varka Add device-tree binding documentation for the Multi-Gigabit Ethernet (MGBE) controller found on NVIDIA Tegra234 SoCs. Signed-off-by: Jon Hunter Signed-off-by: Bhadram Varka Signed-off-by: Thierry Reding --- Changes in v3: - add macsec and macsec-ns interrupt names - improve mdio bus node description - drop power-domains description - improve bindings title Changes in v2: - add supported PHY modes - change to dual license .../bindings/net/nvidia,tegra234-mgbe.yaml | 169 ++++++++++++++++++ 1 file changed, 169 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml diff --git a/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml new file mode 100644 index 000000000000..3d242ef1ca57 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra234 MGBE Multi-Gigabit Ethernet Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + + compatible: + const: nvidia,tegra234-mgbe + + reg: + minItems: 3 + maxItems: 3 + + reg-names: + items: + - const: hypervisor + - const: mac + - const: xpcs + + interrupts: + minItems: 1 + + interrupt-names: + minItems: 1 + items: + - const: common + - const: macsec-ns + - const: macsec + + clocks: + minItems: 12 + maxItems: 12 + + clock-names: + minItems: 12 + maxItems: 12 + contains: + enum: + - mgbe + - mac + - mac-divider + - ptp-ref + - rx-input-m + - rx-input + - tx + - eee-pcs + - rx-pcs-input + - rx-pcs-m + - rx-pcs + - tx-pcs + + resets: + minItems: 2 + maxItems: 2 + + reset-names: + contains: + enum: + - mac + - pcs + + interconnects: + items: + - description: memory read client + - description: memory write client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + + power-domains: + maxItems: 1 + + phy-handle: true + + phy-mode: + contains: + enum: + - usxgmii + - 10gbase-kr + + mdio: + $ref: mdio.yaml# + unevaluatedProperties: false + description: + Optional node for embedded MDIO controller. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - power-domains + - phy-handle + - phy-mode + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + ethernet@6800000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06800000 0x10000>, + <0x06810000 0x10000>, + <0x068a0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = ; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, + <&bpmp TEGRA234_CLK_MGBE0_MAC>, + <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_TX>, + <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, + <&bpmp TEGRA234_RESET_MGBE0_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; + + phy-handle = <&mgbe0_phy>; + phy-mode = "usxgmii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mgbe0_phy: phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + + #phy-cells = <0>; + }; + }; + };