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[95.114.61.215]) by smtp.googlemail.com with ESMTPSA id f13-20020a170906824d00b00726e108b566sm622871ejx.173.2022.06.28.05.45.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 05:45:17 -0700 (PDT) From: Martin Blumenstingl To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, p.zabel@pengutronix.de Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, vkoul@kernel.org, kishon@ti.com, rtanwar@maxlinear.com, Martin Blumenstingl Subject: [PATCH v1 1/9] dt-bindings: phy: lantiq: xway-rcu-usb2-phy: Convert to YAML Date: Tue, 28 Jun 2022 14:44:33 +0200 Message-Id: <20220628124441.2385023-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> References: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Lantiq XWAY RCU USB2 PHY bindings to YAML. Signed-off-by: Martin Blumenstingl --- .../phy/lantiq,xway-rcu-usb2-phy.yaml | 68 +++++++++++++++++++ .../bindings/phy/phy-lantiq-rcu-usb2.txt | 40 ----------- 2 files changed, 68 insertions(+), 40 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/lantiq,xway-rcu-usb2-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt diff --git a/Documentation/devicetree/bindings/phy/lantiq,xway-rcu-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/lantiq,xway-rcu-usb2-phy.yaml new file mode 100644 index 000000000000..702a8e8c64b5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/lantiq,xway-rcu-usb2-phy.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/lantiq,xway-rcu-usb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding + +maintainers: + - Martin Blumenstingl + +properties: + "#phy-cells": + const: 0 + + compatible: + enum: + - lantiq,ase-usb2-phy + - lantiq,danube-usb2-phy + - lantiq,xrx100-usb2-phy + - lantiq,xrx200-usb2-phy + - lantiq,xrx300-usb2-phy + + reg: + minItems: 2 + + clocks: + minItems: 1 + + clock-names: + items: + - const: phy + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + items: + - const: phy + - const: ctrl + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + usb_phy0: usb2-phy@18 { + compatible = "lantiq,xrx200-usb2-phy"; + reg = <0x18 4>, <0x38 4>; + + clocks = <&pmu_USB0_PHY>; + clock-names = "phy"; + + resets = <&reset1 4 4>, <&reset0 4 4>; + reset-names = "phy", "ctrl"; + + #phy-cells = <0>; + }; +... diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt deleted file mode 100644 index 643948b6b576..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt +++ /dev/null @@ -1,40 +0,0 @@ -Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding -=========================================== - -This binding describes the USB PHY hardware provided by the RCU module on the -Lantiq XWAY SoCs. - -This node has to be a sub node of the Lantiq RCU block. - -------------------------------------------------------------------------------- -Required properties (controller (parent) node): -- compatible : Should be one of - "lantiq,ase-usb2-phy" - "lantiq,danube-usb2-phy" - "lantiq,xrx100-usb2-phy" - "lantiq,xrx200-usb2-phy" - "lantiq,xrx300-usb2-phy" -- reg : Defines the following sets of registers in the parent - syscon device - - Offset of the USB PHY configuration register - - Offset of the USB Analog configuration - register (only for xrx200 and xrx200) -- clocks : References to the (PMU) "phy" clk gate. -- clock-names : Must be "phy" -- resets : References to the RCU USB configuration reset bits. -- reset-names : Must be one of the following: - "phy" (optional) - "ctrl" (shared) - -------------------------------------------------------------------------------- -Example for the USB PHYs on an xRX200 SoC: - usb_phy0: usb2-phy@18 { - compatible = "lantiq,xrx200-usb2-phy"; - reg = <0x18 4>, <0x38 4>; - - clocks = <&pmu PMU_GATE_USB0_PHY>; - clock-names = "phy"; - resets = <&reset1 4 4>, <&reset0 4 4>; - reset-names = "phy", "ctrl"; - #phy-cells = <0>; - }; From patchwork Tue Jun 28 12:44:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 1649495 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=googlemail.com header.i=@googlemail.com header.a=rsa-sha256 header.s=20210112 header.b=GI2bfTI+; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LXPT14BLNz9sGJ for ; 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[95.114.61.215]) by smtp.googlemail.com with ESMTPSA id f13-20020a170906824d00b00726e108b566sm622871ejx.173.2022.06.28.05.45.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 05:45:18 -0700 (PDT) From: Martin Blumenstingl To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, p.zabel@pengutronix.de Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, vkoul@kernel.org, kishon@ti.com, rtanwar@maxlinear.com, Martin Blumenstingl Subject: [PATCH v1 2/9] dt-bindings: reset: intel,rcu-gw: Allow up to three global reset items Date: Tue, 28 Jun 2022 14:44:34 +0200 Message-Id: <20220628124441.2385023-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> References: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Legacy SoCs use three elements for the global reset: - offset - reset bit - status bit Allow this in the dt-bindings as well. Fixes: b7ab0cb00d086b ("dt-bindings: reset: Add YAML schemas for the Intel Reset controller") Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml index 13bf6bb3f097..be64f8597710 100644 --- a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml +++ b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml @@ -22,11 +22,15 @@ properties: intel,global-reset: description: Global reset register offset and bit offset. $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 items: - description: Register offset - description: Register bit offset minimum: 0 maximum: 31 + - description: Status bit offset (only if "#reset-cells" is 3) + minimum: 0 + maximum: 31 "#reset-cells": minimum: 2 From patchwork Tue Jun 28 12:44:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 1649496 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=googlemail.com header.i=@googlemail.com header.a=rsa-sha256 header.s=20210112 header.b=B+j85IdQ; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LXPT17580z9sGP for ; Tue, 28 Jun 2022 22:45:25 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345301AbiF1MpX (ORCPT ); Tue, 28 Jun 2022 08:45:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240118AbiF1MpW (ORCPT ); Tue, 28 Jun 2022 08:45:22 -0400 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09DA11D0FE; Tue, 28 Jun 2022 05:45:21 -0700 (PDT) Received: by mail-ed1-x52b.google.com with SMTP id ej4so17395557edb.7; Tue, 28 Jun 2022 05:45:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cnf6pcj5vpCMbTgtadV2bK80NwflBsx3RadXRu/q84M=; b=B+j85IdQS+Xntj9SF6zbCBxyVHzt4nedW5mC16gCblDiLxqEwiEKaGjBWnJxNbbxza WRQlNzQSy1+kmCH2Mao/5NdE5KOWsSMSQM5COm2vNU25odKJ17pCD+mW/MLQkVTPx3ZL ELDxzTSrWCbKZvdjGL3Igh0lMSffAp6M8J6cIBVsaQpd8Yg4APdkUH39sbEP3qRecjOe Ev0Ag1R6uY6KX3MS49lehzdzuU+SMTY3kyMBDd1v32FavGke7XXu89oKCXW4+ybqeaj3 yUoAimTthTjprexnZ0sntVrw/LKYm0xQmRrPstdQn7ApzHnlsm2HPMm3FJ7y//POtGN2 i6cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cnf6pcj5vpCMbTgtadV2bK80NwflBsx3RadXRu/q84M=; b=rzIryrI09O8PkCL1gyo26XAOjw0lDdQRAHZ8Ywek4gRRaBBb/xXeIZjDAIf1I3CJzv J4i0EPBOm61aJQXBsdyXlUTpAl4vfBg8EtsVQCaQtOPiFPEuD3Nxuk5LaIoFbnNEtvre rZFW4JhuzG8BV6pDTcQJ/XYbAW78O3fF8T7T9c1R1RCn3w04ZVaWBVOZaYBiwJfGQtNs 7QsP91RaejSIiQXfKPqGhBnX1FUUks7jfdvld5aqCpJ9EztMDAxfpQQItOk3Nz+7ZCFI mkGF7kaOZgNWH2uFR6m+FzVwK+TBfm2jNJ99QXcJSCSokFgxz9rUXJB8XTg4MYeo2OmW Y56A== X-Gm-Message-State: AJIora9wSuTQUzbR+1Z9CDLfid/Q9ub+DqMaxEi8qsJ9r+eEvhj8bAmj ekJBZ1x3e4Rvub3XJYpIy/I= X-Google-Smtp-Source: AGRyM1uwTe6v4t4C+Cj8uTSAWOl21YQ49mX5FGF++g1vgFNyOS/JkYzaDrYYbPLO26Eiax2DA4KF1g== X-Received: by 2002:a05:6402:27c8:b0:435:d40e:c648 with SMTP id c8-20020a05640227c800b00435d40ec648mr23155962ede.200.1656420319512; Tue, 28 Jun 2022 05:45:19 -0700 (PDT) Received: from localhost.localdomain (dynamic-095-114-061-215.95.114.pool.telefonica.de. [95.114.61.215]) by smtp.googlemail.com with ESMTPSA id f13-20020a170906824d00b00726e108b566sm622871ejx.173.2022.06.28.05.45.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 05:45:19 -0700 (PDT) From: Martin Blumenstingl To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, p.zabel@pengutronix.de Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, vkoul@kernel.org, kishon@ti.com, rtanwar@maxlinear.com, Martin Blumenstingl Subject: [PATCH v1 3/9] dt-bindings: reset: intel,rcu-gw: Update bindings for "legacy" SoCs Date: Tue, 28 Jun 2022 14:44:35 +0200 Message-Id: <20220628124441.2385023-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> References: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Lantiq Amazon-SE, Danube, xRX100 and xRX200 SoCs have up to two USB2 PHYs which are part of the RCU register space. The RCU registers on these SoCs are using big endian. Update the binding for these SoCs to properly describe this IP: - Add compatible strings for Amazon-SE, Danube and xRX100 - Rename the xRX200 compatible string (which is not used anywhere) and switch to the one previously documented in mips/lantiq/rcu.txt - Allow usage of "simple-mfd" and "syscon" in the compatible string so the child devices (USB2 PHYs) can be described - Allow #address-cells and #size-cells to be set to 1 for describing the child devices (USB2 PHYs) - #reset-cells must always be 3 (offset, reset bit and status bit) on the legacy SoCs while LGM uses a fixed value of 2 (offset and reset bit - status bit is always identical to the reset bit). Signed-off-by: Martin Blumenstingl --- .../bindings/reset/intel,rcu-gw.yaml | 84 +++++++++++++++++-- 1 file changed, 79 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml index be64f8597710..b90913c7b7d3 100644 --- a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml +++ b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml @@ -11,9 +11,16 @@ maintainers: properties: compatible: - enum: - - intel,rcu-lgm - - intel,rcu-xrx200 + oneOf: + - items: + - enum: + - lantiq,ase-rcu + - lantiq,danube-rcu + - lantiq,xrx100-rcu + - lantiq,xrx200-rcu + - const: simple-mfd + - const: syscon + - const: intel,rcu-lgm reg: description: Reset controller registers. @@ -33,8 +40,6 @@ properties: maximum: 31 "#reset-cells": - minimum: 2 - maximum: 3 description: | First cell is reset request register offset. Second cell is bit offset in reset request register. @@ -43,6 +48,43 @@ properties: reset request and reset status registers is same. Whereas 3 for legacy SoCs as bit offset differs. + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + big-endian: true + +patternProperties: + "^usb2-phy@[0-9a-f]+$": + type: object + $ref: "../phy/lantiq,xway-rcu-usb2-phy.yaml" + +allOf: + - if: + properties: + compatible: + contains: + const: intel,rcu-lgm + then: + properties: + "#reset-cells": + const: 2 + - if: + properties: + compatible: + contains: + enum: + - lantiq,ase-rcu + - lantiq,danube-rcu + - lantiq,xrx100-rcu + - lantiq,xrx200-rcu + then: + properties: + "#reset-cells": + const: 3 + required: - compatible - reg @@ -67,3 +109,35 @@ examples: #pwm-cells = <2>; resets = <&rcu0 0x30 21>; }; + - | + rcu_xrx200: rcu@203000 { + compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon"; + reg = <0x203000 0x100>; + big-endian; + + #address-cells = <1>; + #size-cells = <1>; + + #reset-cells = <3>; + intel,global-reset = <0x10 30 29>; + + usb_phy0: usb2-phy@18 { + compatible = "lantiq,xrx200-usb2-phy"; + reg = <0x18 4>, <0x38 4>; + status = "disabled"; + + resets = <&rcu_xrx200 0x48 4 4>, <&rcu_xrx200 0x10 4 4>; + reset-names = "phy", "ctrl"; + #phy-cells = <0>; + }; + + usb_phy1: usb2-phy@34 { + compatible = "lantiq,xrx200-usb2-phy"; + reg = <0x34 4>, <0x3c 4>; + status = "disabled"; + + resets = <&rcu_xrx200 0x48 5 5>, <&rcu_xrx200 0x10 4 4>; + reset-names = "phy", "ctrl"; + #phy-cells = <0>; + }; + }; From patchwork Tue Jun 28 12:44:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 1649498 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=googlemail.com header.i=@googlemail.com header.a=rsa-sha256 header.s=20210112 header.b=LjmaQv+U; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LXPT42DCBz9sGC for ; Tue, 28 Jun 2022 22:45:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345347AbiF1MpZ (ORCPT ); Tue, 28 Jun 2022 08:45:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345290AbiF1MpX (ORCPT ); Tue, 28 Jun 2022 08:45:23 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 153DB193ED; Tue, 28 Jun 2022 05:45:22 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id h23so25450013ejj.12; Tue, 28 Jun 2022 05:45:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CKQyH9C8gO8jBo4jczcS1bhOdjsHy0Bi1N6w+JS8218=; b=LjmaQv+UaMIjunLurOL+z37Ha+0Ha5xCcz8TSNyiWiX4mT4KHEwjXmxN+fag+bM0Am yDXP1r7Xc6Zz5IsXYiUJh6k9bSR4DbvAQr6mvKlUF1GPcxRFliO3pFHhUdQEFvePNov0 +UIkfd/sF5nx41cPYL1xor8DJo3YHYiF/Im0ty1E8n7A12RL/Zo7VOtUYSr4JgaddVhr z/ErA31vpWhM9EtFwZomRV3mkYkLBlX1ziGbMxFswIl2irSQ/jybJ9VUylYimIv8ArsP Cdo7e59GNGqfPv89fyweeII2sry/rHE+H5XvLiw7049ZtQJl/rkSJiEKUNwVsOTBCfSr dryA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CKQyH9C8gO8jBo4jczcS1bhOdjsHy0Bi1N6w+JS8218=; b=FnduCv2gR+mc6t+K9JQaabi/FvXaRGMNA/Dfbe5MhmD+jVI4KccutYp053DVAMqhgt ALBbDlagVf5jLMwwNF11Vypvwn4aUuh4XLVyOi9UCYLgv6uvEPA7RtdH9IeW41K0LnIv zZ25xJqO/9GuBbzG8EeF2/IW8jpMVwR+Cmv2IaayowUi+MW/EHWxzRcst2kYArK5aHwp Zhnqxjw7fTIiNwH8gkgtvMvlHPhZ2DvdHZn3vbrZe5+gOiAtaX/YfPrDhpr5VY9belIV MktscxYnyM1BREJeC86rtJ7M4LgpJgtmhFW7qxzsCGQhP3ryGicOiSCn7TSa6JHjJAFn VASg== X-Gm-Message-State: AJIora/3uCq+swb0NAutNCoSmW4Dm1PQZpt51cbG9GV251CUks1Ich13 HPCriuuKZyQQfPDnPRcw4Qs= X-Google-Smtp-Source: AGRyM1uy7MEZIEthYVomXDaHu9jetS7Xdb/FUEi0ipDJra34TCTFPRGKmuJ7DXtAsyRDRkeBXtJgBQ== X-Received: by 2002:a17:906:e256:b0:726:abd9:1063 with SMTP id gq22-20020a170906e25600b00726abd91063mr8552132ejb.741.1656420320598; Tue, 28 Jun 2022 05:45:20 -0700 (PDT) Received: from localhost.localdomain (dynamic-095-114-061-215.95.114.pool.telefonica.de. [95.114.61.215]) by smtp.googlemail.com with ESMTPSA id f13-20020a170906824d00b00726e108b566sm622871ejx.173.2022.06.28.05.45.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 05:45:20 -0700 (PDT) From: Martin Blumenstingl To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, p.zabel@pengutronix.de Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, vkoul@kernel.org, kishon@ti.com, rtanwar@maxlinear.com, Martin Blumenstingl Subject: [PATCH v1 4/9] dt-bindings: mips: lantiq: rcu: Remove binding documentation Date: Tue, 28 Jun 2022 14:44:36 +0200 Message-Id: <20220628124441.2385023-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> References: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This is now part of: Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml The PHYs are still using sub-nodes while the reset-controller is moved to the main RCU node. Also the system reboot is now described directly in intel,rcu-gw.yaml which makes the syscon-reboot node obsolete. Signed-off-by: Martin Blumenstingl Acked-by: Rob Herring --- .../devicetree/bindings/mips/lantiq/rcu.txt | 69 ------------------- 1 file changed, 69 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt deleted file mode 100644 index 58d51f480c9e..000000000000 --- a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt +++ /dev/null @@ -1,69 +0,0 @@ -Lantiq XWAY SoC RCU binding -=========================== - -This binding describes the RCU (reset controller unit) multifunction device, -where each sub-device has it's own set of registers. - -The RCU register range is used for multiple purposes. Mostly one device -uses one or multiple register exclusively, but for some registers some -bits are for one driver and some other bits are for a different driver. -With this patch all accesses to the RCU registers will go through -syscon. - - -------------------------------------------------------------------------------- -Required properties: -- compatible : The first and second values must be: - "lantiq,xrx200-rcu", "simple-mfd", "syscon" -- reg : The address and length of the system control registers - - -------------------------------------------------------------------------------- -Example of the RCU bindings on a xRX200 SoC: - rcu0: rcu@203000 { - compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon"; - reg = <0x203000 0x100>; - ranges = <0x0 0x203000 0x100>; - big-endian; - - reset0: reset-controller@10 { - compatible = "lantiq,xrx200-reset"; - reg = <0x10 4>, <0x14 4>; - - #reset-cells = <2>; - }; - - reset1: reset-controller@48 { - compatible = "lantiq,xrx200-reset"; - reg = <0x48 4>, <0x24 4>; - - #reset-cells = <2>; - }; - - usb_phy0: usb2-phy@18 { - compatible = "lantiq,xrx200-usb2-phy"; - reg = <0x18 4>, <0x38 4>; - - resets = <&reset1 4 4>, <&reset0 4 4>; - reset-names = "phy", "ctrl"; - #phy-cells = <0>; - }; - - usb_phy1: usb2-phy@34 { - compatible = "lantiq,xrx200-usb2-phy"; - reg = <0x34 4>, <0x3C 4>; - - resets = <&reset1 5 4>, <&reset0 4 4>; - reset-names = "phy", "ctrl"; - #phy-cells = <0>; - }; - - reboot@10 { - compatible = "syscon-reboot"; - reg = <0x10 4>; - - regmap = <&rcu0>; - offset = <0x10>; - mask = <0x40000000>; - }; - };