From patchwork Thu May 26 12:37:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiang W X-Patchwork-Id: 1635847 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=oDUgx34E; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=126.com header.i=@126.com header.a=rsa-sha256 header.s=s110527 header.b=fq0ae18K; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4L86sV56HSz9sFk for ; Thu, 26 May 2022 22:37:50 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=tG5hNWQcJIzybMjarMmnNT7PLZWI2W/51O2J0EppB1E=; b=oDUgx34EJ/hfEV T1F3of5U7oP0o0i/M1HSL6AuTaJnqRSswbEyXjBW3yH/THrIK9nySGGb+xd9XrQZrCNMBsq10O8CR NZae94MvNkTrfUwaooIcVqWCB/XheNKvCF0Qd4ZKO1IBTDBGMWmkhNieSZndnAyyhMAgkHxjjs72B PvEQAoeuj1kGBTCQNYs/3uInnRxskNwWC5xjX/Iu5uxBdZpZu7OQVKGeXqZU42loRvddeyhAe798l 4+Q8uCKF5/n6VHyRyy8dmmZxs1ymCVLqzNXQrpgWWEOqRE4VqNxTw4PKA+zxuHyjwjCnohuzj1axP Yr3HOWxdFHLrxDueJUsg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nuCk6-00ErU8-4l; Thu, 26 May 2022 12:37:30 +0000 Received: from mail-m965.mail.126.com ([123.126.96.5]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nuCk1-00ErSW-NR for opensbi@lists.infradead.org; Thu, 26 May 2022 12:37:28 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=126.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=msdqL /4gJPxXMnLC/IJD55rNL0iY2lM3vPJbwbMGCBc=; b=fq0ae18KMq59IvAW6KC1W Xp4J+dwP3Bmx7BX1xMCX167pQ5G+JmY6asfIA6S3to7UXr1LqhwhwILSPaKeJZZw ITRiypoS9Ogolkhum4ntbjezWyDsxtX6VqbH2swiZEiacXvY4HGHPnMEXPHNammw gSBdQ8gcjCaOzc4GWX4jJE= Received: from x390.lan (unknown [210.22.74.70]) by smtp10 (Coremail) with SMTP id NuRpCgDXDnN+dI9i3bzICw--.41215S2; Thu, 26 May 2022 20:37:20 +0800 (CST) From: Xiang W To: opensbi@lists.infradead.org Cc: anup@brainfault.org, Xiang W Subject: [PATCH] lib: sbi: Improve csr read and write Date: Thu, 26 May 2022 20:37:12 +0800 Message-Id: <20220526123712.290855-1-wxjstz@126.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CM-TRANSID: NuRpCgDXDnN+dI9i3bzICw--.41215S2 X-Coremail-Antispam: 1Uf129KBjvJXoW3Jw4DGw47Ww4DAF13CFW3ZFb_yoWxArWkpr WUJFZF9r1jqr4kWwsxC3Z8J345Jw13WF97Jw1Fva93Zw13KF93Gr1kK398JrWDWF9rJws5 W3yvkw1rA3y5JrJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zKQ6phUUUUU= X-Originating-IP: [210.22.74.70] X-CM-SenderInfo: pz0m23b26rjloofrz/1tbi1wANOl53Y+feaAAAs7 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220526_053726_279003_473E6408 X-CRM114-Status: UNSURE ( 9.29 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Reduce the overhead of csr read and write code by producing a small piece of code to perform csr read and write. Signed-off-by: Xiang W --- lib/sbi/riscv_asm.c | 142 ++++ 1 file changed, 10 insertions(+), 132 deletions(-) Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [123.126.96.5 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [wxjstz[at]126.com] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Reduce the overhead of csr read and write code by producing a small piece of code to perform csr read and write. Signed-off-by: Xiang W --- lib/sbi/riscv_asm.c | 142 ++++---------------------------------------- 1 file changed, 10 insertions(+), 132 deletions(-) diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c index a09cf78..9cd8882 100644 --- a/lib/sbi/riscv_asm.c +++ b/lib/sbi/riscv_asm.c @@ -91,144 +91,22 @@ void misa_string(int xlen, char *out, unsigned int out_sz) out[pos++] = '\0'; } +static uint32_t opcode_buff[2]; + unsigned long csr_read_num(int csr_num) { -#define switchcase_csr_read(__csr_num, __val) \ - case __csr_num: \ - __val = csr_read(__csr_num); \ - break; -#define switchcase_csr_read_2(__csr_num, __val) \ - switchcase_csr_read(__csr_num + 0, __val) \ - switchcase_csr_read(__csr_num + 1, __val) -#define switchcase_csr_read_4(__csr_num, __val) \ - switchcase_csr_read_2(__csr_num + 0, __val) \ - switchcase_csr_read_2(__csr_num + 2, __val) -#define switchcase_csr_read_8(__csr_num, __val) \ - switchcase_csr_read_4(__csr_num + 0, __val) \ - switchcase_csr_read_4(__csr_num + 4, __val) -#define switchcase_csr_read_16(__csr_num, __val) \ - switchcase_csr_read_8(__csr_num + 0, __val) \ - switchcase_csr_read_8(__csr_num + 8, __val) -#define switchcase_csr_read_32(__csr_num, __val) \ - switchcase_csr_read_16(__csr_num + 0, __val) \ - switchcase_csr_read_16(__csr_num + 16, __val) -#define switchcase_csr_read_64(__csr_num, __val) \ - switchcase_csr_read_32(__csr_num + 0, __val) \ - switchcase_csr_read_32(__csr_num + 32, __val) - - unsigned long ret = 0; - - switch (csr_num) { - switchcase_csr_read_16(CSR_PMPCFG0, ret) - switchcase_csr_read_64(CSR_PMPADDR0, ret) - switchcase_csr_read(CSR_MCYCLE, ret) - switchcase_csr_read(CSR_MINSTRET, ret) - switchcase_csr_read(CSR_MHPMCOUNTER3, ret) - switchcase_csr_read_4(CSR_MHPMCOUNTER4, ret) - switchcase_csr_read_8(CSR_MHPMCOUNTER8, ret) - switchcase_csr_read_16(CSR_MHPMCOUNTER16, ret) - switchcase_csr_read(CSR_MCOUNTINHIBIT, ret) - switchcase_csr_read(CSR_MHPMEVENT3, ret) - switchcase_csr_read_4(CSR_MHPMEVENT4, ret) - switchcase_csr_read_8(CSR_MHPMEVENT8, ret) - switchcase_csr_read_16(CSR_MHPMEVENT16, ret) -#if __riscv_xlen == 32 - switchcase_csr_read(CSR_MCYCLEH, ret) - switchcase_csr_read(CSR_MINSTRETH, ret) - switchcase_csr_read(CSR_MHPMCOUNTER3H, ret) - switchcase_csr_read_4(CSR_MHPMCOUNTER4H, ret) - switchcase_csr_read_8(CSR_MHPMCOUNTER8H, ret) - switchcase_csr_read_16(CSR_MHPMCOUNTER16H, ret) - /** - * The CSR range MHPMEVENT[3-16]H are available only if sscofpmf - * extension is present. The caller must ensure that. - */ - switchcase_csr_read(CSR_MHPMEVENT3H, ret) - switchcase_csr_read_4(CSR_MHPMEVENT4H, ret) - switchcase_csr_read_8(CSR_MHPMEVENT8H, ret) - switchcase_csr_read_16(CSR_MHPMEVENT16H, ret) -#endif - - default: - sbi_panic("%s: Unknown CSR %#x", __func__, csr_num); - break; - }; - - return ret; - -#undef switchcase_csr_read_64 -#undef switchcase_csr_read_32 -#undef switchcase_csr_read_16 -#undef switchcase_csr_read_8 -#undef switchcase_csr_read_4 -#undef switchcase_csr_read_2 -#undef switchcase_csr_read + typedef unsigned long (*read_f)(void); + opcode_buff[0] = (csr_num << 20) | 0x00002573; /* csrr a0, csr */ + opcode_buff[1] = 0x00008067; /* ret */ + return ((read_f)opcode_buff)(); } void csr_write_num(int csr_num, unsigned long val) { -#define switchcase_csr_write(__csr_num, __val) \ - case __csr_num: \ - csr_write(__csr_num, __val); \ - break; -#define switchcase_csr_write_2(__csr_num, __val) \ - switchcase_csr_write(__csr_num + 0, __val) \ - switchcase_csr_write(__csr_num + 1, __val) -#define switchcase_csr_write_4(__csr_num, __val) \ - switchcase_csr_write_2(__csr_num + 0, __val) \ - switchcase_csr_write_2(__csr_num + 2, __val) -#define switchcase_csr_write_8(__csr_num, __val) \ - switchcase_csr_write_4(__csr_num + 0, __val) \ - switchcase_csr_write_4(__csr_num + 4, __val) -#define switchcase_csr_write_16(__csr_num, __val) \ - switchcase_csr_write_8(__csr_num + 0, __val) \ - switchcase_csr_write_8(__csr_num + 8, __val) -#define switchcase_csr_write_32(__csr_num, __val) \ - switchcase_csr_write_16(__csr_num + 0, __val) \ - switchcase_csr_write_16(__csr_num + 16, __val) -#define switchcase_csr_write_64(__csr_num, __val) \ - switchcase_csr_write_32(__csr_num + 0, __val) \ - switchcase_csr_write_32(__csr_num + 32, __val) - - switch (csr_num) { - switchcase_csr_write_16(CSR_PMPCFG0, val) - switchcase_csr_write_64(CSR_PMPADDR0, val) - switchcase_csr_write(CSR_MCYCLE, val) - switchcase_csr_write(CSR_MINSTRET, val) - switchcase_csr_write(CSR_MHPMCOUNTER3, val) - switchcase_csr_write_4(CSR_MHPMCOUNTER4, val) - switchcase_csr_write_8(CSR_MHPMCOUNTER8, val) - switchcase_csr_write_16(CSR_MHPMCOUNTER16, val) -#if __riscv_xlen == 32 - switchcase_csr_write(CSR_MCYCLEH, val) - switchcase_csr_write(CSR_MINSTRETH, val) - switchcase_csr_write(CSR_MHPMCOUNTER3H, val) - switchcase_csr_write_4(CSR_MHPMCOUNTER4H, val) - switchcase_csr_write_8(CSR_MHPMCOUNTER8H, val) - switchcase_csr_write_16(CSR_MHPMCOUNTER16H, val) - switchcase_csr_write(CSR_MHPMEVENT3H, val) - switchcase_csr_write_4(CSR_MHPMEVENT4H, val) - switchcase_csr_write_8(CSR_MHPMEVENT8H, val) - switchcase_csr_write_16(CSR_MHPMEVENT16H, val) -#endif - switchcase_csr_write(CSR_MCOUNTINHIBIT, val) - switchcase_csr_write(CSR_MHPMEVENT3, val) - switchcase_csr_write_4(CSR_MHPMEVENT4, val) - switchcase_csr_write_8(CSR_MHPMEVENT8, val) - switchcase_csr_write_16(CSR_MHPMEVENT16, val) - - default: - sbi_panic("%s: Unknown CSR %#x", __func__, csr_num); - break; - }; - -#undef switchcase_csr_write_64 -#undef switchcase_csr_write_32 -#undef switchcase_csr_write_16 -#undef switchcase_csr_write_8 -#undef switchcase_csr_write_4 -#undef switchcase_csr_write_2 -#undef switchcase_csr_write + typedef void (*write_f)(unsigned long val); + opcode_buff[0] = (csr_num << 20) | 0x00051073; /* csrw csr, a0 */ + opcode_buff[1] = 0x00008067; /* ret */ + ((write_f)opcode_buff)(val); } static unsigned long ctz(unsigned long x)