From patchwork Thu Feb 22 14:38:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 876722 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3znH706fpLz9sVw for ; Fri, 23 Feb 2018 01:39:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932730AbeBVOjX (ORCPT ); Thu, 22 Feb 2018 09:39:23 -0500 Received: from mout.perfora.net ([74.208.4.194]:34079 "EHLO mout.perfora.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932675AbeBVOjW (ORCPT ); Thu, 22 Feb 2018 09:39:22 -0500 Received: from localhost.localdomain.toradex.int ([46.140.72.82]) by mrelay.perfora.net (mreueus003 [74.208.5.2]) with ESMTPA (Nemesis) id 0Lx5zT-1eiMa10ZYn-016ePd; Thu, 22 Feb 2018 15:38:32 +0100 From: Marcel Ziswiler To: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, Dmitry Osipenko Cc: Marcel Ziswiler , Thierry Reding , Jonathan Hunter , linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland , Russell King , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2] ARM: tegra: fix ulpi regression on tegra20 Date: Thu, 22 Feb 2018 15:38:25 +0100 Message-Id: <20180222143825.1517-1-marcel@ziswiler.com> X-Mailer: git-send-email 2.14.3 X-Provags-ID: V03:K0:7JWEIyTJJ+6LX+0UvjV56zkDMMsYqLwMdjiSYtVhc5YC0QElClT 6ni6kZwy5DKqyovUhsbsSBM5Wta9w6S2EPg7ZAZOi/vvqfhM8afpH3kU70aK4Lg05luKXM2 fbqNbA+1C49Lcqq3GSO5S2Z08ElYUJc/dd3IwPMoEav8GVi0rDKRWEfxJCaPtgqTkbY4VXL D+f8AVz8ZbQerElUJoShg== X-UI-Out-Filterresults: notjunk:1; V01:K0:BwTCNeIyN7g=:dXHpvtoBkr9XbcRVOGhUFe TUDk1N1/Sg2WBuwC0tfPOANVokZi400N8PJybLQHBFzQiF+n52broT45AtrC3mO6QSf3U62+r B0VnPvf/35R0WeS46+XJ7OJVylUcIASu8kfUP37zmRNMjcR7FkjI6mhIYoWTyVEtOdveGidjl MCMDmxjwVwappx+GSJmTtlZ0V+XctOtfZfWbsMhTIxeAZgARzflpUXqOk3ME1GLu/EUezALCJ DSBv3tT5tZBl31QTk/nsaB3vxSkY62Pu5k+L95lu3NSVJawNGXA7mideLy5bze/O8igDCLEji wN3D/0VkIPP7eJyl7S9bdjZHO9FZJhHMiBkeCzksFbBl3msc9jPBucFoeGNa6e9ch2ZQthzUp +pWyoPfu8wqETbkx3PDDdy7TROpYVYBPoO8st9P4LLfwL15d8UGqLRjH+4ytXwjHA0Dt1Fm5x aL0zKi7WVPRfxTPq1NDBZbx5P6BA+ZhlDMCfJ937OreldLHaOve/jFWnp99ChgTsA8yxqz+y7 1oSbFZ/Yq7u9Hcm9rGB9v9icAuLW6qkXkMrwNQ6ejScufrWgjwKfr7fq6AQtjeEpBex555V8b 2+UqXLtbm0yKHTkYnXiU1sCH0nY6GDLGwxzX2FhvWe5UtdUZ1fQayoFVTJWA9cGi3bQUsOFUX kjJ+8qQJWu5BoFbtzcK5AsEQEzowDCcaERTE87J1ANvtU6Z/KBjUVBJOgdGSYMlo2JOmgiI9r DJCkQCHhMFOs7phKWEKfyJ2eEYrBVJzlpJv2Og== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Marcel Ziswiler Since commit f8f8f1d04494 ("clk: Don't touch hardware when reparenting during registration") ULPI has been broken on Tegra20 leading to the following error message during boot: [ 1.974698] ulpi_phy_power_on: ulpi write failed [ 1.979384] tegra-ehci c5004000.usb: Failed to power on the phy [ 1.985434] tegra-ehci: probe of c5004000.usb failed with error -110 Debugging through the changes and finally also consulting the TRM revealed that rather than the CDEV2 clock off OSC requiring such pin muxing actually the PLL_P_OUT4 clock is in use. It looks like so far it just worked by chance of that one having been enabled which Stephen's commit now changed when reparenting sclk away from pll_p_out4 leaving that one disabled. Fix this by properly assigning the PLL_P_OUT4 clock as the ULPI PHY clock. Signed-off-by: Marcel Ziswiler Reviewed-by: Dmitry Osipenko Reviewed-by: Rob Herring --- Changes in v2: - Updated device tree binding documentation as well. - CCing Dmitry as well. Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt | 4 +++- arch/arm/boot/dts/tegra20.dtsi | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt index a9aa79fb90ed..1aa6f2674af5 100644 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt @@ -21,7 +21,9 @@ Required properties : - timer: The timeout clock (clk_m). Present if phy_type == utmi. - utmi-pads: The clock needed to access the UTMI pad control registers. Present if phy_type == utmi. - - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2). + - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2 + with pad group aka "nvidia,pins" cdev2 and pin mux option config aka + "nvidia,function" pllp_out4). Present if phy_type == ulpi, and ULPI link mode is in use. - resets : Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 864a95872b8d..e05b6bb2599f 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -741,7 +741,7 @@ phy_type = "ulpi"; clocks = <&tegra_car TEGRA20_CLK_USB2>, <&tegra_car TEGRA20_CLK_PLL_U>, - <&tegra_car TEGRA20_CLK_CDEV2>; + <&tegra_car TEGRA20_CLK_PLL_P_OUT4>; clock-names = "reg", "pll_u", "ulpi-link"; resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads";