From patchwork Sun May 1 12:23:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1624887 X-Patchwork-Delegate: van.freenix@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=vE8HmPRP; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KrlmV5trrz9s5V for ; Sun, 1 May 2022 22:25:14 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EBBAE83F0E; Sun, 1 May 2022 14:24:58 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="vE8HmPRP"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A5DD883BBF; Sun, 1 May 2022 14:24:54 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0C12B83C8C for ; Sun, 1 May 2022 14:24:51 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 86049B80D0B; Sun, 1 May 2022 12:24:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 24EF0C385AA; Sun, 1 May 2022 12:24:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651407889; bh=DWmnemDRCNo3IEiuP/ERSJlYTYHNG4+eunTXStULRGo=; h=From:To:Cc:Subject:Date:From; b=vE8HmPRPUef13BbmHFDez8i0Z7E4rfXXETtZu9LBKLfktk+/xc1T0iQiaTZIZypTm FtWe9BvzyHlGEcxLSd6/+Tn6+kSe1+33jU4h4Em8kPeS8O7A8Top2Us+eLSfIIS5YQ w8uZcrJScpwob+I+TGzz+GE7vlV4mBzY8Pg0U1syjmmidVfj34TY2zdcVtUCkI590K yNBO4HiaYDEmB8/54z1f9rEmiaVn0LLW5UxkwVRKZBeHKKSnevYrE6iyNg7OL8karE ggCWgqH1RoV4UT90SCj9gQVawgHx2HNy90Dy+XpmWwd0xL4aXuDY+9zCHg22KWKQ8j DKZRf+m6hsHyw== Received: by pali.im (Postfix) id 596DB942; Sun, 1 May 2022 14:24:45 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Priyanka Jain , Sinan Akman Cc: u-boot@lists.denx.de Subject: [PATCH 1/3] board: freescale: p1_p2_rdb_pc: Add workaround for board reset reboot loop Date: Sun, 1 May 2022 14:23:12 +0200 Message-Id: <20220501122314.32626-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean CPLD's system reset register on P1/P2 RDB boards is not autocleared after flipping it. If this register is set to one then CPLD triggers reset of CPU in few ms. This means that trying to reset board via CPLD system reset register cause reboot loop. To prevent this reboot loop, the only workaround is to try to clear CPLD's system reset register as early as possible. U-Boot is already doing it in its board_early_init_f() function, which seems to be enough as register is cleared prior CPLD triggers another reset. But board_early_init_f() is not called from SPL and therefore usage of SPL can cause reboot loop. To prevent reboot loop when using SPL, calls board_early_init_f() function in SPL too. For accessing CPLD memory space it is needed to have CPLD entry in TLB. With this change it is possible to trigger board reset via CPLD's system reset register on P2020 RDB board. Signed-off-by: Pali Rohár --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 10 ++++++++++ board/freescale/p1_p2_rdb_pc/spl.c | 6 ++++++ board/freescale/p1_p2_rdb_pc/tlb.c | 2 +- 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 7b168fa091b1..26ea8a525228 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -91,6 +91,16 @@ void board_cpld_init(void) out_8(&cpld_data->status_led, CPLD_STATUS_LED); out_8(&cpld_data->fxo_led, CPLD_FXO_LED); out_8(&cpld_data->fxs_led, CPLD_FXS_LED); + + /* + * CPLD's system reset register on P1/P2 RDB boards is not autocleared + * after flipping it. If this register is set to one then CPLD triggers + * reset of CPU in few ms. + * + * This means that trying to reset board via CPLD system reset register + * cause reboot loop. To prevent this reboot loop, the only workaround + * is to try to clear CPLD's system reset register as early as possible. + */ out_8(&cpld_data->system_rst, CPLD_SYS_RST); } diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 22156f2824ec..def28665960d 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -31,6 +31,12 @@ void board_init_f(ulong bootflag) u32 plat_ratio, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + /* + * Call board_early_init_f() as early as possible as it workarounds + * reboot loop due to broken CPLD state machine for reset line. + */ + board_early_init_f(); + console_init_f(); /* Set pmuxcr to allow both i2c1 and i2c2 */ diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 13f3a1edf68d..2d431d6d0d90 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif +#endif /* not SPL */ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#endif /* not SPL */ #ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ From patchwork Sun May 1 12:23:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1624886 X-Patchwork-Delegate: van.freenix@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=DtaMWVVI; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KrlmF198Tz9s5V for ; Sun, 1 May 2022 22:25:01 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D63D383C8C; Sun, 1 May 2022 14:24:55 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="DtaMWVVI"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id AF2D783F0E; Sun, 1 May 2022 14:24:53 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DF8EC83BBF for ; Sun, 1 May 2022 14:24:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 906DA60DDC; Sun, 1 May 2022 12:24:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D510FC385A9; Sun, 1 May 2022 12:24:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651407889; bh=2gddnlZft3Y66yjXTmSv0kz/K0R7arTtQ7OVcRAWuqk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DtaMWVVIOLlbkqXnk1XUpkQgjXXCeLgXdaOf01DglSjPCS3ug7ZRxkTZ/6jQDEc7s +gXEPuA4nBNB7n2Jkjk0H79fjjtAAcIRSfQ5n5pftUf4PwjQkGSNWPKd2pt1F0HFtX Dm+4i78dWB3JfA48nb0f5xoCqwGanbwEuuVV9Rh25bvzT/vlmmYJkwcSsrEV6vL2ZO tjiqaqVnF44LkC0+n/tBkfkY2159iYUdRzmK8ec/sgi0IYpcb6Z7G0WMTaW1iY6VB8 oWVRoQmDZBEm7lDtuaYrWTxTa9BD58I16mLm8e/BQQvfY/Dsfl/GJzfBk3pVfISuIs 8+nFZPTiHazxg== Received: by pali.im (Postfix) id 4B78896D; Sun, 1 May 2022 14:24:46 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Priyanka Jain , Sinan Akman Cc: u-boot@lists.denx.de Subject: [PATCH 2/3] board: freescale: p1_p2_rdb_pc: Add workaround for non-working watchdog Date: Sun, 1 May 2022 14:23:13 +0200 Message-Id: <20220501122314.32626-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220501122314.32626-1-pali@kernel.org> References: <20220501122314.32626-1-pali@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean If watchdog timer was already set to non-disabled value then it means that watchdog timer was already activated, has already expired and caused CPU reset. If this happened then due to CPLD firmware bug, writing to wd_cfg register has no effect and therefore it is not possible to reactivate watchdog timer again. Also if CPU was reset via watchdog then some peripherals like i2c do not work. Watchdog and i2c start working again after CPU reset via non-watchdog method. Implement this workaround (reset CPU when it was reset by watchdog) to make watchdog usable again. Watchdog timer logic on these P1/P2 RDB boards is connected to CPLD, not to SoC itself. Signed-off-by: Pali Rohár --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 26ea8a525228..24b5ec435e4e 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -86,6 +86,7 @@ struct cpld_data { void board_cpld_init(void) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + u8 prev_wd_cfg = in_8(&cpld_data->wd_cfg); out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); out_8(&cpld_data->status_led, CPLD_STATUS_LED); @@ -102,6 +103,23 @@ void board_cpld_init(void) * is to try to clear CPLD's system reset register as early as possible. */ out_8(&cpld_data->system_rst, CPLD_SYS_RST); + + /* + * If watchdog timer was already set to non-disabled value then it means + * that watchdog timer was already activated, has already expired and + * caused CPU reset. If this happened then due to CPLD firmware bug, + * writing to wd_cfg register has no effect and therefore it is not + * possible to reactivate watchdog timer again. Also if CPU was reset + * via watchdog then some peripherals like i2c do not work. Watchdog and + * i2c start working again after CPU reset via non-watchdog method. + * + * So in case watchdog timer register in CPLD was already enabled then + * disable it in CPLD and reset CPU which cause new boot. Watchdog timer + * is disabled few lines above, after reading CPLD previous value. + * This logic (disabling timer before reset) prevents reboot loop. + */ + if (prev_wd_cfg != CPLD_WD_CFG) + do_reset(NULL, 0, 0, NULL); } void board_gpio_init(void) From patchwork Sun May 1 12:23:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1624888 X-Patchwork-Delegate: van.freenix@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=fExSBeB3; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Krlmf590dz9s5V for ; Sun, 1 May 2022 22:25:22 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1E53B83F1F; Sun, 1 May 2022 14:25:02 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="fExSBeB3"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3C5EF83E0E; Sun, 1 May 2022 14:24:56 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D2F9A83F05 for ; Sun, 1 May 2022 14:24:51 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 7340BB80D3A; Sun, 1 May 2022 12:24:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F39E0C385AF; Sun, 1 May 2022 12:24:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651407890; bh=hbzQHpkgW2WLavzH1DgLJiwPjp4R/bp5hUDRNfPKcEs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fExSBeB3WCor2g1wuA/wjm/PNXf3oQwP8aocQhTUm0s3HnrCZIMxcYKs4bh8whqle tp7dxRQ6PMJVIG+CuypdSd7/Mhfp1xQW0Fp8DSJlNvJMmOeCWsMZ/ySAk3VMYdofiV 6huWkP4ozkIgyltg9JwHm4YyBV4ji+/40g/n3noWRbakV1gitVd69MYgFH5arqICIc WnxW1nXDvNvEQWGdgSOtChHOm4aYfcK+jc9pGmYxeQitKNvop2VhpC7Ew9qXovROB4 1ePdm+x1uSsjxOpRxxDVCo3Mllt4a55eHQSu1YyXJDL0J7GahEOe1U2uN54kHcajrP psWHG8rDC8nCA== Received: by pali.im (Postfix) id 528C7989; Sun, 1 May 2022 14:24:47 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Priyanka Jain , Sinan Akman Cc: u-boot@lists.denx.de Subject: [PATCH 3/3] board: freescale: p1_p2_rdb_pc: Implement board_reset() Date: Sun, 1 May 2022 14:23:14 +0200 Message-Id: <20220501122314.32626-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220501122314.32626-1-pali@kernel.org> References: <20220501122314.32626-1-pali@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Do board reset via CPLD's system reset register. Signed-off-by: Pali Rohár --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 24b5ec435e4e..53ff121d3b3d 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -83,6 +83,12 @@ struct cpld_data { #define CPLD_FXS_LED 0x0F #define CPLD_SYS_RST 0x00 +void board_reset(void) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + out_8(&cpld_data->system_rst, 1); +} + void board_cpld_init(void) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);