From patchwork Wed Feb 21 15:16:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 876148 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zmh1r0m7rz9rxj for ; Thu, 22 Feb 2018 02:17:51 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B09B1C21F01; Wed, 21 Feb 2018 15:17:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E7DCFC21EEB; Wed, 21 Feb 2018 15:17:01 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A7DE7C21C50; Wed, 21 Feb 2018 15:16:59 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) by lists.denx.de (Postfix) with ESMTPS id 92954C21E45 for ; Wed, 21 Feb 2018 15:16:58 +0000 (UTC) Received: from localhost.localdomain.toradex.int ([46.140.72.82]) by mrelay.perfora.net (mreueus001 [74.208.5.2]) with ESMTPA (Nemesis) id 0LpMWp-1eIDf336hh-00fDe8; Wed, 21 Feb 2018 16:16:49 +0100 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Wed, 21 Feb 2018 16:16:40 +0100 Message-Id: <20180221151641.28350-1-marcel@ziswiler.com> X-Mailer: git-send-email 2.14.3 X-Provags-ID: V03:K0:yMA0J0u9kUkntGXYJ93pYsrTTTi8iNQVeHJHi0kKB9i8DuB1xWt HwSzGhFQXaOnZtBd52AEzDdjydiWrsNq+Q61MYvZAFbVd42ko+PPc8Jjsk39ZEUn8OSbd10 DfSGQBS7Tb6VreTVs2gY/B3TsHpD5Yvcjx3rGozvSMGF7qu30SNu5XhH0XQQAOV9xdAnhCq MdSjxFnRp7rh7F8SHHjSw== X-UI-Out-Filterresults: notjunk:1; V01:K0:J2rsld0Jmeg=:qTYyrUP5lquN+R/ThIuOad 1BFY4es/fe8Xot0f1EMVggcNqe+Jcb787yvGuNr+9Efn8bg8Wp3LsbmfoPTFGQqT81zuM7ebc I8VioHuatG1+D99OCLhkdWBBJsS4HcjouIu9M72sGNB/L84+U7FSQa2gTwKzFbU3pUrkAXE+K zCweIjEDyFdLrYLHP8KEykcLgx6GfwcvSJzSaZYEj7JR4oE/dP4zqlbIu0/Se7pc1w3yZvJx5 f2eDdzA2l8ZebzRYRdBMg0C1JQdYTQX//60ISbZ5os0etAa48Jus85NbGOYALShJl8UkhG14d MBppC1qMUxo8IYd8LMndZEKn53vhu6U+9NB/XhvsB+cjgNaIOQ6n1Cwk0mAqssASbcBWktsRG iQyORjPGnWEZe6OR/KfxM9c993Uf8v1FLGr9WzzPPpA6NympdQG/7mQeztoowZ6uglIelLtw3 IchWagBq7eprUtzA/1EphVpuvoDjXsOeck3RMf5krnYxY27XgCdQzJQIiY9ckD+/vLhI1AKsA pt2Qlgacp7x802dZLzlOwH1XK4tkKMI4/NsoLo1armW43ZSGL0F3XrdOWwxrxWd5LeXdeyjbc 1dEQ1MeSuRsqnU1LtV3PJ3tccAHp0k2mhgAKam01E95VROlIe8Lqed0RjaTVlmOT2E3Maw2NQ YwhWZnBv2NDk2FINbYWdgBtE0pRcOWjfp2HqsKS44QGqFFe7uzxAxnEbRM9N0JrBT2UqElxBZ MkzUx2PvGbhhzj6FT3qjSocxw0JxNmeU1GBARw== Cc: Stephen Warren , Marcel Ziswiler , Scott Wood , Tom Warren , Scott Wood Subject: [U-Boot] [PATCH 1/2] mtd: nand: tegra: convert to driver model and live tree X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Marcel Ziswiler The Tegra NAND driver recently got broken by ongoing driver model resp. live tree migration work: NAND: Could not decode nand-flash in device tree Tegra NAND init failed 0 MiB A patch for NAND uclass support was proposed about a year ago: https://patchwork.ozlabs.org/patch/722282/ It was not merged and I do not see on-going work for this. This commit just provides a driver model probe hook to retrieve further configuration from the live device tree. As there is no NAND ulass as of yet (ab)using UCLASS_MISC. Once UCLASS_NAND is supported, it would be possible to migrate to it. Signed-off-by: Marcel Ziswiler Reviewed-by: Simon Glass --- drivers/mtd/nand/tegra_nand.c | 98 ++++++++++++++++++++++++------------------- 1 file changed, 55 insertions(+), 43 deletions(-) diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c index c03c9cb178..405018018c 100644 --- a/drivers/mtd/nand/tegra_nand.c +++ b/drivers/mtd/nand/tegra_nand.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "tegra_nand.h" DECLARE_GLOBAL_DATA_PTR; @@ -29,6 +30,13 @@ DECLARE_GLOBAL_DATA_PTR; /* ECC bytes to be generated for tag data */ #define TAG_ECC_BYTES 4 +static const struct udevice_id tegra_nand_dt_ids[] = { + { + .compatible = "nvidia,tegra20-nand", + }, + { /* sentinel */ } +}; + /* 64 byte oob block info for large page (== 2KB) device * * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC: @@ -91,9 +99,11 @@ struct nand_drv { struct fdt_nand config; }; -static struct nand_drv nand_ctrl; -static struct mtd_info *our_mtd; -static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; +struct tegra_nand_info { + struct udevice *dev; + struct nand_drv nand_ctrl; + struct nand_chip nand_chip; +}; /** * Wait for command completion @@ -453,8 +463,8 @@ static void stop_command(struct nand_ctlr *reg) * @param *reg_val address of reg_val * @return 0 if ok, -1 on error */ -static int set_bus_width_page_size(struct fdt_nand *config, - u32 *reg_val) +static int set_bus_width_page_size(struct mtd_info *our_mtd, + struct fdt_nand *config, u32 *reg_val) { if (config->width == 8) *reg_val = CFG_BUS_WIDTH_8BIT; @@ -514,7 +524,7 @@ static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip, info = (struct nand_drv *)nand_get_controller_data(chip); config = &info->config; - if (set_bus_width_page_size(config, ®_val)) + if (set_bus_width_page_size(mtd, config, ®_val)) return -EINVAL; /* Need to be 4-byte aligned */ @@ -722,7 +732,7 @@ static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip, if (((int)chip->oob_poi) & 0x03) return -EINVAL; info = (struct nand_drv *)nand_get_controller_data(chip); - if (set_bus_width_page_size(&info->config, ®_val)) + if (set_bus_width_page_size(mtd, &info->config, ®_val)) return -EINVAL; stop_command(info->reg); @@ -883,51 +893,39 @@ static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT], /** * Decode NAND parameters from the device tree * - * @param blob Device tree blob - * @param node Node containing "nand-flash" compatible node + * @param dev Driver model device + * @param config Device tree NAND configuration * @return 0 if ok, -ve on error (FDT_ERR_...) */ -static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config) +static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config) { int err; - config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg"); - config->enabled = fdtdec_get_is_enabled(blob, node); - config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8); - err = gpio_request_by_name_nodev(offset_to_ofnode(node), - "nvidia,wp-gpios", 0, &config->wp_gpio, GPIOD_IS_OUT); + config->reg = (struct nand_ctlr *)dev_read_addr(dev); + config->enabled = dev_read_enabled(dev); + config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8); + err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio, + GPIOD_IS_OUT); if (err) return err; - err = fdtdec_get_int_array(blob, node, "nvidia,timing", - config->timing, FDT_NAND_TIMING_COUNT); + err = dev_read_u32_array(dev, "nvidia,timing", config->timing, + FDT_NAND_TIMING_COUNT); if (err < 0) return err; - /* Now look up the controller and decode that */ - node = fdt_next_node(blob, node, NULL); - if (node < 0) - return node; - return 0; } -/** - * Board-specific NAND initialization - * - * @param nand nand chip info structure - * @return 0, after initialized, -1 on error - */ -int tegra_nand_init(struct nand_chip *nand, int devnum) +static int tegra_probe(struct udevice *dev) { - struct nand_drv *info = &nand_ctrl; + struct tegra_nand_info *tegra = dev_get_priv(dev); + struct nand_chip *nand = &tegra->nand_chip; + struct nand_drv *info = &tegra->nand_ctrl; struct fdt_nand *config = &info->config; - int node, ret; + struct mtd_info *our_mtd; + int ret; - node = fdtdec_next_compatible(gd->fdt_blob, 0, - COMPAT_NVIDIA_TEGRA20_NAND); - if (node < 0) - return -1; - if (fdt_decode_nand(gd->fdt_blob, node, config)) { + if (fdt_decode_nand(dev, config)) { printf("Could not decode nand-flash in device tree\n"); return -1; } @@ -950,7 +948,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum) nand->ecc.strength = 1; nand->select_chip = nand_select_chip; nand->dev_ready = nand_dev_ready; - nand_set_controller_data(nand, &nand_ctrl); + nand_set_controller_data(nand, &tegra->nand_ctrl); /* Disable subpage writes as we do not provide ecc->hwctl */ nand->options |= NAND_NO_SUBPAGE_WRITE; @@ -975,17 +973,31 @@ int tegra_nand_init(struct nand_chip *nand, int devnum) if (ret) return ret; - ret = nand_register(devnum, our_mtd); - if (ret) + ret = nand_register(0, our_mtd); + if (ret) { + dev_err(dev, "Failed to register MTD: %d\n", ret); return ret; + } return 0; } +U_BOOT_DRIVER(tegra_nand) = { + .name = "tegra-nand", + .id = UCLASS_MISC, + .of_match = tegra_nand_dt_ids, + .probe = tegra_probe, + .priv_auto_alloc_size = sizeof(struct tegra_nand_info), +}; + void board_nand_init(void) { - struct nand_chip *nand = &nand_chip[0]; - - if (tegra_nand_init(nand, 0)) - puts("Tegra NAND init failed\n"); + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(tegra_nand), &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize %s. (error %d)\n", dev->name, + ret); } From patchwork Wed Feb 21 15:16:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 876147 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zmh116WPkz9rxp for ; Thu, 22 Feb 2018 02:17:09 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6E09EC21E73; Wed, 21 Feb 2018 15:17:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EA70AC21E39; Wed, 21 Feb 2018 15:17:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 43D38C21E50; Wed, 21 Feb 2018 15:16:59 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.197]) by lists.denx.de (Postfix) with ESMTPS id BB874C21E39 for ; Wed, 21 Feb 2018 15:16:56 +0000 (UTC) Received: from localhost.localdomain.toradex.int ([46.140.72.82]) by mrelay.perfora.net (mreueus001 [74.208.5.2]) with ESMTPA (Nemesis) id 0Lu5Nw-1ef8Df3oXu-011PE7; Wed, 21 Feb 2018 16:16:50 +0100 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Wed, 21 Feb 2018 16:16:41 +0100 Message-Id: <20180221151641.28350-2-marcel@ziswiler.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180221151641.28350-1-marcel@ziswiler.com> References: <20180221151641.28350-1-marcel@ziswiler.com> X-Provags-ID: V03:K0:D1NFRx1kg9WNPrlG81WFbMrt9L5yBfrbvcfNuW7/W/n5RhegTPz sluGvmZaj2GQzqvOYbswmT0AuYhQCMzyVC6Pz5t8V/X9yq62Np77GeDmAYwPgM0nJMdyJvA 75j1NOD1s95pE796m3XJSXe2Cmc1ufdYj1RqRfZib3OT1CjEKcR7AkPV/KWIH+AxNWcVqTr lZHhvRNnwdKTRIr0HpDQg== X-UI-Out-Filterresults: notjunk:1; V01:K0:Le/h1W++s6A=:omf1WAYy5Kvs81lhKqKWYO Ea7Nn9DT70HRgG3/GDsmENuUaJit3Xxn/rAkVNbjLMsMtEPc4VmamM5BjB5RuJGcyMDASpwZv 5b3rWfVQS4r3eGBtKelwVPYAs6cDVPyRRQLaR6qdubAP3iKreddBXLX87DIjM3L5nV5Xur5rA a/hgOuQGN+jspvmgPfn7whyskL8LLX17DGqeETwG6CQIRINdQux1YEmknkSQeKp06TiWVVPz2 uISGBDSFOhLANG+wj0YfWaBoRrfgv7DrBIb0cC05uXQG1Fa+pHErltAgB/WZcZ5i8opKaqD56 30Oeq9xhqJkcSjQg/yRBW2Y4LtwNv988f7fwxaeJ9HxADzy0V0uoBIFhpWV80EBfvK11GmCpk ePHgziHweiKhLx8BckGOvJjRO0f8kErPGwHvh5+Aw98F0UFvDt5/zhXOz01gxXzcW0dfxtD+r qLJaCskmoY9Zy/GcJiGdhjjM/w6FFE6swkVXZOq89nOIM64ROlwFT4RoqP3j/Lqu/CwkHevAD uiU5A4FeENpwPfHAXefnc04rZlSaNmpVlk7kDLjc/P8WecUxKCRJq9qrTqcFDT8DSKC+cAUOr sIsp/oU/CE9Qd8RlQ/ILF7Xy4Ay8subQv+H08lQQ5UwOfos9/O2ZTJa4lz67bvzP69QuwIcwi qPlkcBD3tz+ua4BXWBGxgPBTYjHltcBH6a57N+5P60BPD9NeuBgavTK8tmEy2Ec2NCr7zxos/ RtsLoUL2RsfeEWnZCpWWJ3V6DYD9PQqER06wsA== Cc: Marcel Ziswiler , Tom Warren Subject: [U-Boot] [PATCH 2/2] configs: harmony: enable live tree, mtd and ubi X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Marcel Ziswiler U-Boot on Harmony recently got broken by ongoing driver model resp. live tree migration work: U-Boot 2018.03-rc3 (Feb 21 2018 - 15:43:08 +0100) TEGRA20 Model: NVIDIA Tegra20 Harmony evaluation board Board: NVIDIA Harmony DRAM: 1 GiB Video device 'dc@54200000' cannot allocate frame buffer memory -ensure the device is set up before relocation Error binding driver 'tegra_lcd': -28 Some drivers failed to bind Error binding driver 'generic_simple_bus': -28 Some drivers failed to bind initcall sequence 3ffa86d0 failed at call 00121dc0 (err=-28) This commit fixes this by enabling live tree, MTD and UBI for Harmony as well. Signed-off-by: Marcel Ziswiler --- configs/harmony_defconfig | 5 +++++ include/configs/harmony.h | 4 ++++ 2 files changed, 9 insertions(+) diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index 33b3ba5fce..1d1a158691 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -18,14 +18,19 @@ CONFIG_CMD_USB=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_MTDIDS_DEFAULT="nand0=tegra_nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=tegra_nand:2m(u-boot)ro,1m(u-boot-env),1m(cfgblock)ro,-(ubi)" +CONFIG_CMD_UBI=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_LIVE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SPL_DM=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y +CONFIG_MTD_UBI_FASTMAP=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/include/configs/harmony.h b/include/configs/harmony.h index 9a0b1aff24..59fd6c4eb5 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -30,6 +30,10 @@ #define CONFIG_TEGRA_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 +/* Dynamic MTD partition support */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ + /* Environment in NAND (which is 512M), aligned to start of last sector */ #define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */