From patchwork Sat Apr 9 19:55:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 1615341 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=svanheule.net header.i=@svanheule.net header.a=rsa-sha256 header.s=mail1707 header.b=MFqYIlk3; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4KbR1K2tQXz9sCq for ; Sun, 10 Apr 2022 06:05:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229929AbiDIUHL (ORCPT ); Sat, 9 Apr 2022 16:07:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230102AbiDIUHI (ORCPT ); Sat, 9 Apr 2022 16:07:08 -0400 Received: from polaris.svanheule.net (polaris.svanheule.net [IPv6:2a00:c98:2060:a004:1::200]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB2A047AD7 for ; Sat, 9 Apr 2022 13:05:00 -0700 (PDT) Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:eaf9:8401:9d41:ea18:e395:a08d]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 39A072C4653; Sat, 9 Apr 2022 21:55:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1649534159; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XPHDw3Kn6paq26RqJYO+850bOj9HsiGkdLK+KjbbhMQ=; b=MFqYIlk3KrXbM6hnuqutSH4942YHk2W3DEQ8Dj9KoEfpLF2DbX6s1oJbRycxwli7zNd6la gCCrGNg5hPKbEgSbYhpLYbvaiVAKuPlUeRmr1cp+a2A05QdkZA2RD0NTpU+o6bwq0vWuQf ZHJNtAopa1hxcCPifwYhJeRQSkjToXkyCAGSNJyxD1Ge0PvgkeDWwMbONmFunkE1xxuXJr 8v2jaOY7id61jKtwh+BLPxM0diVL2BA7WRQGkDWRAtWTPj3L+bQzO0oqiN900tBkNeUJlb +B/xbWU/b3hYSfnBGVn+/qmfAUdiYAZmYOwMbJWaQVahFzZDx6DykvwFB3Y6oQ== From: Sander Vanheule To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sander Vanheule , Bert Vermeulen , linux-kernel@vger.kernel.org Subject: [PATCH v1 1/6] dt-bindings: gpio: realtek-otto: Add rtl9300 compatible Date: Sat, 9 Apr 2022 21:55:46 +0200 Message-Id: <7dfad6c63cea64ccd84907f1cf9f7c9c6d1ce3e9.1649533972.git.sander@svanheule.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the "realtek,rlt9300-gpio", "realtek,otto-gpio" compatible for GPIO nodes on the RTL930x SoC series. This SoC requires an extra register range, defining the interrupt CPU mapping registers. Signed-off-by: Sander Vanheule Reviewed-by: Krzysztof Kozlowski --- .../bindings/gpio/realtek,otto-gpio.yaml | 33 +++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml b/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml index 100f20cebd76..3c511e9af377 100644 --- a/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml @@ -28,10 +28,10 @@ properties: - enum: - realtek,rtl8380-gpio - realtek,rtl8390-gpio + - realtek,rtl9300-gpio - const: realtek,otto-gpio - reg: - maxItems: 1 + reg: true "#gpio-cells": const: 2 @@ -50,6 +50,23 @@ properties: interrupts: maxItems: 1 +if: + properties: + compatible: + contains: + const: realtek,rtl9300-gpio +then: + properties: + reg: + items: + - description: GPIO and interrupt control + - description: interrupt CPU map +else: + properties: + reg: + items: + - description: GPIO and interrupt control + required: - compatible - reg @@ -74,5 +91,17 @@ examples: interrupt-parent = <&rtlintc>; interrupts = <23>; }; + - | + gpio@3300 { + compatible = "realtek,rtl9300-gpio", "realtek,otto-gpio"; + reg = <0x3300 0x1c>, <0x3338 0x8>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <24>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&rtlintc>; + interrupts = <13>; + }; ... From patchwork Sat Apr 9 19:55:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 1615340 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=svanheule.net header.i=@svanheule.net header.a=rsa-sha256 header.s=mail1707 header.b=8W9kwhRr; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4KbR1J5K9zz9sDX for ; Sun, 10 Apr 2022 06:05:08 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229899AbiDIUHJ (ORCPT ); Sat, 9 Apr 2022 16:07:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230023AbiDIUHH (ORCPT ); Sat, 9 Apr 2022 16:07:07 -0400 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E648649692 for ; Sat, 9 Apr 2022 13:04:58 -0700 (PDT) Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:eaf9:8401:9d41:ea18:e395:a08d]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 277172C4654; Sat, 9 Apr 2022 21:55:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1649534160; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uRGo5vYh4KWsfFxzH88QOPhI+uf6Yg6jZrVcj/clFBU=; b=8W9kwhRrYgwwuuUK1PT2+L4fu52pQ89W85oReU8nv53sYrP7eODvVf8p1BPkTTol0tyQ+b UEZehX9TAeULharZ498D6I/dvpl9Q/b0s3Q0IRofbeXCoJR2CQpIps2SoEHfz47Tb/ALUx 14cXn42Tm2z3wJjQhhSBOFrJs/FgPTQxD87jyNRQWVh+dbQTaFdpDH2+C9MeG8zAgWbaTk Svr8epFEgV6u8YHrZBT19woAvHCCuru7HGofYCbFnJ7a+3tyiidywFe4Uzbp5EREXcoBYq 1alWOLHTOfdXlOJYW6TRy1gznuVqDH35F7fr5ioVqZ0GM3rSs5Kar7iVYLSvyw== From: Sander Vanheule To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sander Vanheule , Bert Vermeulen , linux-kernel@vger.kernel.org Subject: [PATCH v1 2/6] gpio: realtek-otto: Support reversed port layouts Date: Sat, 9 Apr 2022 21:55:47 +0200 Message-Id: <7105ae382d7b328102f66b39ffd7c94998e85265.1649533972.git.sander@svanheule.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The GPIO port layout on the RTL930x SoC series is reversed compared to the RTL838x and RTL839x SoC series. Add new port offset calculator functions to ensure the correct order is used when reading port IRQ data, and ensure bgpio uses the right byte ordering. Signed-off-by: Sander Vanheule Reviewed-by: Linus Walleij --- drivers/gpio/gpio-realtek-otto.c | 55 +++++++++++++++++++++++++++++--- 1 file changed, 51 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-realtek-otto.c b/drivers/gpio/gpio-realtek-otto.c index bd75401b549d..c838ad8ce55f 100644 --- a/drivers/gpio/gpio-realtek-otto.c +++ b/drivers/gpio/gpio-realtek-otto.c @@ -58,6 +58,8 @@ struct realtek_gpio_ctrl { raw_spinlock_t lock; u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK]; u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK]; + unsigned int (*port_offset_u8)(unsigned int port); + unsigned int (*port_offset_u16)(unsigned int port); }; /* Expand with more flags as devices with other quirks are added */ @@ -69,6 +71,11 @@ enum realtek_gpio_flags { * line the IRQ handler was assigned to, causing uncaught interrupts. */ GPIO_INTERRUPTS_DISABLED = BIT(0), + /* + * Port order is reversed, meaning DCBA register layout for 1-bit + * fields, and [BA, DC] for 2-bit fields. + */ + GPIO_PORTS_REVERSED = BIT(1), }; static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data) @@ -86,21 +93,50 @@ static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data) * port. The two interrupt mask registers store two bits per GPIO, so use u16 * values. */ +static unsigned int realtek_gpio_port_offset_u8(unsigned int port) +{ + return port; +} + +static unsigned int realtek_gpio_port_offset_u16(unsigned int port) +{ + return 2 * port; +} + +/* + * Reversed port order register access + * + * For registers with one bit per GPIO, all ports are stored as u8-s in one + * register in reversed order. The two interrupt mask registers store two bits + * per GPIO, so use u16 values. The first register contains ports 1 and 0, the + * second ports 3 and 2. + */ +static unsigned int realtek_gpio_port_offset_u8_rev(unsigned int port) +{ + return 3 - port; +} + +static unsigned int realtek_gpio_port_offset_u16_rev(unsigned int port) +{ + return 2 * (port ^ 1); +} + static void realtek_gpio_write_imr(struct realtek_gpio_ctrl *ctrl, unsigned int port, u16 irq_type, u16 irq_mask) { - iowrite16(irq_type & irq_mask, ctrl->base + REALTEK_GPIO_REG_IMR + 2 * port); + iowrite16(irq_type & irq_mask, + ctrl->base + REALTEK_GPIO_REG_IMR + ctrl->port_offset_u16(port)); } static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl, unsigned int port, u8 mask) { - iowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + port); + iowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port)); } static u8 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl, unsigned int port) { - return ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + port); + return ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port)); } /* Set the rising and falling edge mask bits for a GPIO port pin */ @@ -250,6 +286,7 @@ MODULE_DEVICE_TABLE(of, realtek_gpio_of_match); static int realtek_gpio_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + unsigned long bgpio_flags; unsigned int dev_flags; struct gpio_irq_chip *girq; struct realtek_gpio_ctrl *ctrl; @@ -277,10 +314,20 @@ static int realtek_gpio_probe(struct platform_device *pdev) raw_spin_lock_init(&ctrl->lock); + if (dev_flags & GPIO_PORTS_REVERSED) { + bgpio_flags = 0; + ctrl->port_offset_u8 = realtek_gpio_port_offset_u8_rev; + ctrl->port_offset_u16 = realtek_gpio_port_offset_u16_rev; + } else { + bgpio_flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER; + ctrl->port_offset_u8 = realtek_gpio_port_offset_u8; + ctrl->port_offset_u16 = realtek_gpio_port_offset_u16; + } + err = bgpio_init(&ctrl->gc, dev, 4, ctrl->base + REALTEK_GPIO_REG_DATA, NULL, NULL, ctrl->base + REALTEK_GPIO_REG_DIR, NULL, - BGPIOF_BIG_ENDIAN_BYTE_ORDER); + bgpio_flags); if (err) { dev_err(dev, "unable to init generic GPIO"); return err; From patchwork Sat Apr 9 19:55:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 1615338 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=svanheule.net header.i=@svanheule.net header.a=rsa-sha256 header.s=mail1707 header.b=hv3nAX3I; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4KbR1H2NrBz9sCq for ; Sun, 10 Apr 2022 06:05:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229455AbiDIUHI (ORCPT ); Sat, 9 Apr 2022 16:07:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229892AbiDIUHH (ORCPT ); Sat, 9 Apr 2022 16:07:07 -0400 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C19344889E for ; Sat, 9 Apr 2022 13:04:58 -0700 (PDT) Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:eaf9:8401:9d41:ea18:e395:a08d]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id B7EDD2C4655; Sat, 9 Apr 2022 21:56:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1649534161; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ADyb9IacFCFsKePa1Pnrn2WIbPbzJAembwxCqsyNT6Y=; b=hv3nAX3IG4jyqCSOo/JHSAnXRto7ZgEvsHoITR2mYA6mTHEF+3J2P6yDdKC8oItL10F6l0 Hx2gWzNrPdOAiZ6k9toMU/Kwx8iLYe4u88rFwBLPgxbOyFiukVeeB+IMWXbvSj5dIHp4Wj +4Oh4s99kOfn5wzC2Dpm4W9Jjs8/gPoHDscXSLTH1GscjXIYLuTt8gj8i+28v/RdKZ081K Adv7/G2YCUd9McmlhthWtviY7RSBw/E3TLoAOWJJ/oM8rQUQxm6ERhLYCRHyG0eucY+v1l WurKnKvT6ay20OST7NEY/EkzezMj+uc18olSixhLcdfh4cuVneRWXXm8OqXI3Q== From: Sander Vanheule To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sander Vanheule , Bert Vermeulen , linux-kernel@vger.kernel.org Subject: [PATCH v1 3/6] gpio: realtek-otto: Support per-cpu interrupts Date: Sat, 9 Apr 2022 21:55:48 +0200 Message-Id: <8d4e0848f233c2c1b98aa141741c61d95cd3843f.1649533972.git.sander@svanheule.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On SoCs with multiple cores, it is possible that the GPIO interrupt controller supports assigning specific pins to one or more cores. IRQ balancing can be performed on a line-by-line basis if the parent interrupt is routed to all available cores, which is the default upon initialisation. Signed-off-by: Sander Vanheule --- drivers/gpio/gpio-realtek-otto.c | 75 +++++++++++++++++++++++++++++++- 1 file changed, 74 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-realtek-otto.c b/drivers/gpio/gpio-realtek-otto.c index c838ad8ce55f..dd1b7656d23a 100644 --- a/drivers/gpio/gpio-realtek-otto.c +++ b/drivers/gpio/gpio-realtek-otto.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only #include +#include #include #include #include @@ -55,6 +56,8 @@ struct realtek_gpio_ctrl { struct gpio_chip gc; void __iomem *base; + void __iomem *cpumask_base; + struct cpumask cpu_irq_maskable; raw_spinlock_t lock; u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK]; u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK]; @@ -76,6 +79,11 @@ enum realtek_gpio_flags { * fields, and [BA, DC] for 2-bit fields. */ GPIO_PORTS_REVERSED = BIT(1), + /* + * Interrupts can be enabled per cpu. This requires a secondary IO + * range, where the per-cpu enable masks are located. + */ + GPIO_INTERRUPTS_PER_CPU = BIT(2), }; static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data) @@ -247,14 +255,61 @@ static void realtek_gpio_irq_handler(struct irq_desc *desc) chained_irq_exit(irq_chip, desc); } +static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl, + unsigned int port, int cpu) +{ + return ctrl->cpumask_base + ctrl->port_offset_u8(port) + + REALTEK_GPIO_PORTS_PER_BANK * cpu; +} + +static int realtek_gpio_irq_set_affinity(struct irq_data *data, + const struct cpumask *dest, bool force) +{ + struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); + unsigned int line = irqd_to_hwirq(data); + unsigned int port = line / 8; + unsigned int port_pin = line % 8; + void __iomem *irq_cpu_mask; + unsigned long flags; + int cpu; + u8 v; + + if (!ctrl->cpumask_base) + return -ENXIO; + + raw_spin_lock_irqsave(&ctrl->lock, flags); + + for_each_cpu(cpu, &ctrl->cpu_irq_maskable) { + irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, port, cpu); + v = ioread8(irq_cpu_mask); + + if (cpumask_test_cpu(cpu, dest)) + v |= BIT(port_pin); + else + v &= ~BIT(port_pin); + + iowrite8(v, irq_cpu_mask); + } + + raw_spin_unlock_irqrestore(&ctrl->lock, flags); + + irq_data_update_effective_affinity(data, dest); + + return 0; +} + static int realtek_gpio_irq_init(struct gpio_chip *gc) { struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); unsigned int port; + int cpu; for (port = 0; (port * 8) < gc->ngpio; port++) { realtek_gpio_write_imr(ctrl, port, 0, 0); realtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0)); + + for_each_cpu(cpu, &ctrl->cpu_irq_maskable) + iowrite8(GENMASK(7, 0), realtek_gpio_irq_cpu_mask(ctrl, port, cpu)); } return 0; @@ -266,6 +321,7 @@ static struct irq_chip realtek_gpio_irq_chip = { .irq_mask = realtek_gpio_irq_mask, .irq_unmask = realtek_gpio_irq_unmask, .irq_set_type = realtek_gpio_irq_set_type, + .irq_set_affinity = realtek_gpio_irq_set_affinity, }; static const struct of_device_id realtek_gpio_of_match[] = { @@ -290,8 +346,10 @@ static int realtek_gpio_probe(struct platform_device *pdev) unsigned int dev_flags; struct gpio_irq_chip *girq; struct realtek_gpio_ctrl *ctrl; + struct resource *res; u32 ngpios; - int err, irq; + unsigned int nr_cpus; + int cpu, err, irq; ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); if (!ctrl) @@ -352,6 +410,21 @@ static int realtek_gpio_probe(struct platform_device *pdev) girq->init_hw = realtek_gpio_irq_init; } + cpumask_clear(&ctrl->cpu_irq_maskable); + + if ((dev_flags & GPIO_INTERRUPTS_PER_CPU) && irq > 0) { + ctrl->cpumask_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); + if (IS_ERR(ctrl->cpumask_base)) + return dev_err_probe(dev, PTR_ERR(ctrl->cpumask_base), + "missing CPU IRQ mask registers"); + + nr_cpus = resource_size(res) / REALTEK_GPIO_PORTS_PER_BANK; + nr_cpus = min(nr_cpus, num_present_cpus()); + + for (cpu = 0; cpu < nr_cpus; cpu++) + cpumask_set_cpu(cpu, &ctrl->cpu_irq_maskable); + } + return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); } From patchwork Sat Apr 9 19:55:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 1615339 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=svanheule.net header.i=@svanheule.net header.a=rsa-sha256 header.s=mail1707 header.b=4PvsXEwV; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4KbR1J0KVPz9sCq for ; Sun, 10 Apr 2022 06:05:08 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230195AbiDIUHJ (ORCPT ); Sat, 9 Apr 2022 16:07:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229952AbiDIUHH (ORCPT ); Sat, 9 Apr 2022 16:07:07 -0400 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B61384926C for ; Sat, 9 Apr 2022 13:04:58 -0700 (PDT) Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:eaf9:8401:9d41:ea18:e395:a08d]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 8AD942C4656; Sat, 9 Apr 2022 21:56:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1649534161; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lsZorXZYXlyDl5x1CMnRj2fHFtwWcfNYaAsfL8MAYPk=; b=4PvsXEwV1luETKxiPwzE0idp+FXUs+RF4rwJQJA4LJz3ajSzf/cgngbcD0A6kRUyQuS6gO uzU8OkdacJ/qZwTLs6ZxP5q6HqqzoBr011SVToTdAnmpUWYWleG4zQjaMb83qdhXCCNnjo cu/oJajM7IKfeY7Y8EPlh2QUpnTV1F+gMQaYkr3OFes8ZOrYCwMQcT7mugHubThOLzRQtT nU0UDN5Z3Oxg7XxHAkaDVWv5Y7utdkb/3TfCojRtMYh/+aEJRsWM+/ykbxHBJBJLIcWJ7g wb7ybAwz1Cj+xV27Cjvegd9W/1KFi3rChOCwFT5PKgrRN6BDdrQElNA9Y1tutg== From: Sander Vanheule To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sander Vanheule , Bert Vermeulen , linux-kernel@vger.kernel.org Subject: [PATCH v1 4/6] gpio: realtek-otto: Add RTL930x support Date: Sat, 9 Apr 2022 21:55:49 +0200 Message-Id: <0b8a8a927d998bbdceac7638d812790604f4d810.1649533972.git.sander@svanheule.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The RTL930x SoC series has support for 24 GPIOs, with the port order reversed compared to RTL838x and RTL839x. The RTL930x series also has two CPUs (VPEs) and can distribute individual GPIO interrupts between them. Signed-off-by: Sander Vanheule --- drivers/gpio/gpio-realtek-otto.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpio/gpio-realtek-otto.c b/drivers/gpio/gpio-realtek-otto.c index dd1b7656d23a..3ddaa17accff 100644 --- a/drivers/gpio/gpio-realtek-otto.c +++ b/drivers/gpio/gpio-realtek-otto.c @@ -335,6 +335,10 @@ static const struct of_device_id realtek_gpio_of_match[] = { { .compatible = "realtek,rtl8390-gpio", }, + { + .compatible = "realtek,rtl9300-gpio", + .data = (void *)(GPIO_PORTS_REVERSED | GPIO_INTERRUPTS_PER_CPU) + }, {} }; MODULE_DEVICE_TABLE(of, realtek_gpio_of_match); From patchwork Sat Apr 9 19:55:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 1615342 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=svanheule.net header.i=@svanheule.net header.a=rsa-sha256 header.s=mail1707 header.b=yulkC0mL; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4KbR1L23pdz9sCq for ; Sun, 10 Apr 2022 06:05:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230007AbiDIUHN (ORCPT ); Sat, 9 Apr 2022 16:07:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229812AbiDIUHJ (ORCPT ); Sat, 9 Apr 2022 16:07:09 -0400 Received: from polaris.svanheule.net (polaris.svanheule.net [IPv6:2a00:c98:2060:a004:1::200]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88CCD2DD6D for ; Sat, 9 Apr 2022 13:05:01 -0700 (PDT) Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:eaf9:8401:9d41:ea18:e395:a08d]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 319742C4657; Sat, 9 Apr 2022 21:56:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1649534162; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xkfs1gHO5sgAn4raphVRPtE947SinFm+RwKVlazXeBM=; b=yulkC0mLCL9H8dfj88+37waAQabf2/mlTI1o3iV8bw8MjkyLQqkTJbglX+qN+cnmzffJV6 Fhabzw0N27syJwzbsfrv+eA6InEoAyWjpJ727JYIFz859Hu9sZQMrioB/JMbl5xT/FSpdN pI6of76Ovu+4KVUKdc7jxXcyCVCgGm9L4c4Nt3yf5UFhixETO9l3RXqF0hCW6jzTpZzgtV YKkYGOJXqDU8VFyn73lxLkMDsaUYrfNDYLapw3P0Rbw6pXekNt77Pw/BIw/lIvC4MF8oK7 e6CDrFTbliCIxBbsvpmB58SWrZqIpU0f34f0uULWg4qlrk5j64G8KFYX+lnfGQ== From: Sander Vanheule To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sander Vanheule , Bert Vermeulen , linux-kernel@vger.kernel.org Subject: [PATCH v1 5/6] dt-bindings: gpio: realtek-otto: Add rtl9310 compatible Date: Sat, 9 Apr 2022 21:55:50 +0200 Message-Id: <380b17f04e127351b83d7f4d7db22d4f58aebcbd.1649533972.git.sander@svanheule.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the "realtek,rlt9310-gpio", "realtek,otto-gpio" compatible for GPIO nodes on the RTL931x SoC series. Signed-off-by: Sander Vanheule Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml b/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml index 3c511e9af377..39fd959c45d2 100644 --- a/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml @@ -29,6 +29,7 @@ properties: - realtek,rtl8380-gpio - realtek,rtl8390-gpio - realtek,rtl9300-gpio + - realtek,rtl9310-gpio - const: realtek,otto-gpio reg: true From patchwork Sat Apr 9 19:55:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 1615337 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=svanheule.net header.i=@svanheule.net header.a=rsa-sha256 header.s=mail1707 header.b=9ehHVlFq; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4KbR1G4Nsyz9sFt for ; Sun, 10 Apr 2022 06:05:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230088AbiDIUHI (ORCPT ); Sat, 9 Apr 2022 16:07:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229915AbiDIUHH (ORCPT ); Sat, 9 Apr 2022 16:07:07 -0400 X-Greylist: delayed 535 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Sat, 09 Apr 2022 13:04:58 PDT Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48A2A47AD1 for ; Sat, 9 Apr 2022 13:04:58 -0700 (PDT) Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:eaf9:8401:9d41:ea18:e395:a08d]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id B80232C4658; Sat, 9 Apr 2022 21:56:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1649534163; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=i+chAUdJiBzKs88jdausmSCxwbTjomag1w6qWW/Hank=; b=9ehHVlFq8F/jG3mofWNO7ADtxpJpI5BxrxNHr/PEVNVyorURuUdaAukDEKP20F6t6kEeZp 1nCrHM9POUVWNFhcuhlKa0AS/iqyu13oRS3xmyN8cZ9zp6VGjyyeSmTbGuVDfrELmJJvth WsRP0fcXUjBaGbXQNk4b4t/QDdacI4OYb3vFFTzXHQFDukbiHmnliV/27m0SVj5yVZ6lop v8TLHMOCTI/e/ryzyux9G3XSJkPVlWAghJlisz6i71C8e9ej0vWu/9/dJkImumHQkfYAD+ NTveQZ3Ua+Ej8rdkIkOYfPnCTxpFTee2WB0myyRwzQMjrw74xZ0aKBw2IAc0xg== From: Sander Vanheule To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sander Vanheule , Bert Vermeulen , linux-kernel@vger.kernel.org Subject: [PATCH v1 6/6] gpio: realtek-otto: Add RTL931x support Date: Sat, 9 Apr 2022 21:55:51 +0200 Message-Id: <56ee532f99b197b431ede9a3179b0d6e826d196b.1649533972.git.sander@svanheule.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The RTL931x SoC series has support for 32 GPIOs, although not all lines may be broken out to a physical pad. The GPIO bank's parent interrupt can be routed to either or both of the SoC's CPU cores by the GIC. Line-by-line IRQ balancing is not possible on these SoCs. Signed-off-by: Sander Vanheule --- drivers/gpio/gpio-realtek-otto.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpio/gpio-realtek-otto.c b/drivers/gpio/gpio-realtek-otto.c index 3ddaa17accff..c52b2cb1acae 100644 --- a/drivers/gpio/gpio-realtek-otto.c +++ b/drivers/gpio/gpio-realtek-otto.c @@ -339,6 +339,9 @@ static const struct of_device_id realtek_gpio_of_match[] = { .compatible = "realtek,rtl9300-gpio", .data = (void *)(GPIO_PORTS_REVERSED | GPIO_INTERRUPTS_PER_CPU) }, + { + .compatible = "realtek,rtl9310-gpio", + }, {} }; MODULE_DEVICE_TABLE(of, realtek_gpio_of_match);