From patchwork Sun Mar 20 10:01:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Haifeng X-Patchwork-Id: 1607418 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KLwhp1R4Nz9s8s for ; Sun, 20 Mar 2022 22:37:30 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3C291839C6; Sun, 20 Mar 2022 12:37:09 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=timesintelli.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 5DB2B8399C; Sun, 20 Mar 2022 11:01:47 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 Received: from out28-74.mail.aliyun.com (out28-74.mail.aliyun.com [115.124.28.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8015D8392F for ; Sun, 20 Mar 2022 11:01:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=timesintelli.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=haifeng.li@timesintelli.com X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1233893|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0141626-0.0037561-0.982081; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047208; MF=haifeng.li@timesintelli.com; NM=1; PH=DS; RN=4; RT=4; SR=0; TI=SMTPD_---.N8U2XUe_1647770482; Received: from localhost.localdomain(mailfrom:haifeng.li@timesintelli.com fp:SMTPD_---.N8U2XUe_1647770482) by smtp.aliyun-inc.com(33.38.168.42); Sun, 20 Mar 2022 18:01:27 +0800 From: Haifeng Li To: dinguyen@kernel.org, u-boot@lists.denx.de, trini@konsulko.com Cc: Haifeng Li Subject: [PATCH v2 1/1] cache: l2x0: Fix incorrect behavior if the latency is 1 cycle Date: Sun, 20 Mar 2022 18:01:20 +0800 Message-Id: <20220320100120.23524-1-haifeng.li@timesintelli.com> X-Mailer: git-send-email 2.17.1 X-Mailman-Approved-At: Sun, 20 Mar 2022 12:37:05 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean According to the PL310 TRM, 0 in the latency fields(setup/read/write) indicates 1 cycle of latency for Tag and Data RAM latency control registers. If we want to set 1 cycle of latency, we need to clear the field actually. The TRM is as below: https://developer.arm.com/documentation/ddi0246/h/programmers-model/register-descriptions/tag-and-data-ram-latency-control-registers Signed-off-by: Haifeng Li --- drivers/cache/cache-l2x0.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c index a1556fbf17..16b583ddd2 100644 --- a/drivers/cache/cache-l2x0.c +++ b/drivers/cache/cache-l2x0.c @@ -38,19 +38,27 @@ static void l2c310_of_parse_and_init(struct udevice *dev) writel(saved_reg, ®s->pl310_aux_ctrl); - saved_reg = readl(®s->pl310_tag_latency_ctrl); - if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3)) + if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3)) { + saved_reg = readl(®s->pl310_tag_latency_ctrl); + clrbits_le32(&saved_reg, L310_LATENCY_CTRL_WR(7) | + L310_LATENCY_CTRL_RD(7) | + L310_LATENCY_CTRL_SETUP(7)); saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) | L310_LATENCY_CTRL_WR(tag[1] - 1) | L310_LATENCY_CTRL_SETUP(tag[2] - 1); - writel(saved_reg, ®s->pl310_tag_latency_ctrl); + writel(saved_reg, ®s->pl310_tag_latency_ctrl); + } - saved_reg = readl(®s->pl310_data_latency_ctrl); - if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3)) + if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3)) { + saved_reg = readl(®s->pl310_data_latency_ctrl); + clrbits_le32(&saved_reg, L310_LATENCY_CTRL_WR(7) | + L310_LATENCY_CTRL_RD(7) | + L310_LATENCY_CTRL_SETUP(7)); saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) | L310_LATENCY_CTRL_WR(tag[1] - 1) | L310_LATENCY_CTRL_SETUP(tag[2] - 1); - writel(saved_reg, ®s->pl310_data_latency_ctrl); + writel(saved_reg, ®s->pl310_data_latency_ctrl); + } /* Enable the L2 cache */ setbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);