From patchwork Wed Mar 16 11:55:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1606120 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4KJTJ228r1z9sCq for ; Wed, 16 Mar 2022 22:56:02 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355502AbiCPL5O (ORCPT ); Wed, 16 Mar 2022 07:57:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237146AbiCPL5O (ORCPT ); Wed, 16 Mar 2022 07:57:14 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id F22545EDF8; Wed, 16 Mar 2022 04:55:59 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.90,186,1643641200"; d="scan'208";a="113695417" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 16 Mar 2022 20:55:59 +0900 Received: from localhost.localdomain (unknown [10.226.92.179]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 296EE40078CD; Wed, 16 Mar 2022 20:55:56 +0900 (JST) From: Biju Das To: Mauro Carvalho Chehab , Rob Herring Cc: Biju Das , Laurent Pinchart , Kieran Bingham , linux-media@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH v6 1/3] media: dt-bindings: media: renesas,vsp1: Document RZ/{G2L,V2L} VSPD bindings Date: Wed, 16 Mar 2022 11:55:49 +0000 Message-Id: <20220316115551.29222-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220316115551.29222-1-biju.das.jz@bp.renesas.com> References: <20220316115551.29222-1-biju.das.jz@bp.renesas.com> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document VSPD found in RZ/G2L and RZ/V2L family SoC's. VSPD block is similar to VSP2-D found on R-Car SoC's, but it does not have a version register and it has 3 clocks compared to 1 clock on vsp1 and vsp2. This patch introduces a new compatible 'renesas,rzg2l-vsp2' to handle these differences. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Reviewed-by: Krzysztof Kozlowski --- v5->v6: * Removed LCDC reference clock description * Changed the clock name from du.0->aclk v4->v5: * No change v3->v4: * No change v2->v3: * Added Rb tag from Krzysztof. v1->v2: * Changed compatible from vsp2-rzg2l->rzg2l-vsp2 RFC->v1: * Updated commit description * Changed compatible from vsp2-r9a07g044->vsp2-rzg2l * Defined the clocks * Clock max Items is based on SoC Compatible string RFC: * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-20-biju.das.jz@bp.renesas.com/ --- .../bindings/media/renesas,vsp1.yaml | 52 ++++++++++++++----- 1 file changed, 39 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml index 990e9c1dbc43..a236b266fa4b 100644 --- a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml +++ b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml @@ -19,6 +19,7 @@ properties: enum: - renesas,vsp1 # R-Car Gen2 and RZ/G1 - renesas,vsp2 # R-Car Gen3 and RZ/G2 + - renesas,rzg2l-vsp2 # RZ/G2L and RZ/V2L reg: maxItems: 1 @@ -26,8 +27,8 @@ properties: interrupts: maxItems: 1 - clocks: - maxItems: 1 + clocks: true + clock-names: true power-domains: maxItems: 1 @@ -50,17 +51,42 @@ required: additionalProperties: false -if: - properties: - compatible: - items: - - const: renesas,vsp1 -then: - properties: - renesas,fcp: false -else: - required: - - renesas,fcp +allOf: + - if: + properties: + compatible: + contains: + const: renesas,vsp1 + then: + properties: + renesas,fcp: false + else: + required: + - renesas,fcp + + - if: + properties: + compatible: + contains: + const: renesas,rzg2l-vsp2 + then: + properties: + clocks: + items: + - description: Main clock + - description: Register access clock + - description: Video clock + clock-names: + items: + - const: aclk + - const: pclk + - const: vclk + required: + - clock-names + else: + properties: + clocks: + maxItems: 1 examples: # R8A7790 (R-Car H2) VSP1-S