From patchwork Thu Mar 3 12:13:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1600307 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4K8VJj5VJyz9sGF for ; Thu, 3 Mar 2022 23:13:57 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233089AbiCCMOk (ORCPT ); Thu, 3 Mar 2022 07:14:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233079AbiCCMOk (ORCPT ); Thu, 3 Mar 2022 07:14:40 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7E40AB0D20; Thu, 3 Mar 2022 04:13:54 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.90,151,1643641200"; d="scan'208";a="113048362" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 03 Mar 2022 21:13:53 +0900 Received: from localhost.localdomain (unknown [10.226.93.138]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id DFE9542F4DBC; Thu, 3 Mar 2022 21:13:51 +0900 (JST) From: Biju Das To: Rob Herring Cc: Biju Das , Geert Uytterhoeven , Lad Prabhakar , devicetree@vger.kernel.org, Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC Date: Thu, 3 Mar 2022 12:13:40 +0000 Message-Id: <20220303121346.4769-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220303121346.4769-1-biju.das.jz@bp.renesas.com> References: <20220303121346.4769-1-biju.das.jz@bp.renesas.com> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT binding documentation for SYSC controller found on RZ/G2UL SoC's. SYSC controller found on the RZ/G2UL SoC is almost identical to one found on the RZ/G2L SoC's only difference being that the RZ/G2UL has only CA55 core0 reset vector address configuration register. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- .../devicetree/bindings/power/renesas,rzg2l-sysc.yaml | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml index bb433e75a0ee..ce372378ff97 100644 --- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml @@ -4,14 +4,14 @@ $id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Renesas RZ/{G2L,V2L} System Controller (SYSC) +title: Renesas RZ/{G2L, G2UL, V2L} System Controller (SYSC) maintainers: - Geert Uytterhoeven description: - The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI - and supports following functions, + The RZ/{G2L, G2UL, V2L} System Controller (SYSC) performs system control of + the LSI and supports following functions, - External terminal state capture function - 34-bit address space access function - Low power consumption control @@ -20,8 +20,9 @@ description: properties: compatible: enum: - - renesas,r9a07g044-sysc # RZ/G2{L,LC} - - renesas,r9a07g054-sysc # RZ/V2L + - renesas,r9a07g043u-sysc # RZ/G2UL + - renesas,r9a07g044-sysc # RZ/G2{L,LC} + - renesas,r9a07g054-sysc # RZ/V2L reg: maxItems: 1 From patchwork Thu Mar 3 12:13:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1600308 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4K8VJm73sBz9sG6 for ; Thu, 3 Mar 2022 23:14:00 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233101AbiCCMOo (ORCPT ); Thu, 3 Mar 2022 07:14:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231876AbiCCMOo (ORCPT ); Thu, 3 Mar 2022 07:14:44 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 31555156C50; Thu, 3 Mar 2022 04:13:58 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.90,151,1643641200"; d="scan'208";a="112218610" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 03 Mar 2022 21:13:57 +0900 Received: from localhost.localdomain (unknown [10.226.93.138]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 340BF42F4DBC; Thu, 3 Mar 2022 21:13:56 +0900 (JST) From: Biju Das To: Rob Herring Cc: Biju Das , devicetree@vger.kernel.org, Geert Uytterhoeven , Chris Paterson , Biju Das , Prabhakar Mahadev Lad , linux-renesas-soc@vger.kernel.org Subject: [PATCH 3/7] dt-bindings: clock: Add R9A07G043U CPG Clock and Reset Definitions Date: Thu, 3 Mar 2022 12:13:42 +0000 Message-Id: <20220303121346.4769-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220303121346.4769-1-biju.das.jz@bp.renesas.com> References: <20220303121346.4769-1-biju.das.jz@bp.renesas.com> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also add Reset definitions referring to registers CPG_RST_* in Section 7.2.3 ("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev. 0.51, Nov. 2021). Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- include/dt-bindings/clock/r9a07g043u-cpg.h | 186 +++++++++++++++++++++ 1 file changed, 186 insertions(+) create mode 100644 include/dt-bindings/clock/r9a07g043u-cpg.h diff --git a/include/dt-bindings/clock/r9a07g043u-cpg.h b/include/dt-bindings/clock/r9a07g043u-cpg.h new file mode 100644 index 000000000000..447f0c2471d3 --- /dev/null +++ b/include/dt-bindings/clock/r9a07g043u-cpg.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__ + +#include + +/* R9A07G043U CPG Core Clocks */ +#define R9A07G043U_CLK_I 0 +#define R9A07G043U_CLK_I2 1 +#define R9A07G043U_CLK_S0 2 +#define R9A07G043U_CLK_SPI0 3 +#define R9A07G043U_CLK_SPI1 4 +#define R9A07G043U_CLK_SD0 5 +#define R9A07G043U_CLK_SD1 6 +#define R9A07G043U_CLK_M0 7 +#define R9A07G043U_CLK_M2 8 +#define R9A07G043U_CLK_M3 9 +#define R9A07G043U_CLK_HP 10 +#define R9A07G043U_CLK_TSU 11 +#define R9A07G043U_CLK_ZT 12 +#define R9A07G043U_CLK_P0 13 +#define R9A07G043U_CLK_P1 14 +#define R9A07G043U_CLK_P2 15 +#define R9A07G043U_CLK_AT 16 +#define R9A07G043U_OSCCLK 17 +#define R9A07G043U_CLK_P0_DIV2 18 + +/* R9A07G043U Module Clocks */ +#define R9A07G043U_CA55_SCLK 0 +#define R9A07G043U_CA55_PCLK 1 +#define R9A07G043U_CA55_ATCLK 2 +#define R9A07G043U_CA55_GICCLK 3 +#define R9A07G043U_CA55_PERICLK 4 +#define R9A07G043U_CA55_ACLK 5 +#define R9A07G043U_CA55_TSCLK 6 +#define R9A07G043U_GIC600_GICCLK 7 +#define R9A07G043U_IA55_CLK 8 +#define R9A07G043U_IA55_PCLK 9 +#define R9A07G043U_MHU_PCLK 10 +#define R9A07G043U_SYC_CNT_CLK 11 +#define R9A07G043U_DMAC_ACLK 12 +#define R9A07G043U_DMAC_PCLK 13 +#define R9A07G043U_OSTM0_PCLK 14 +#define R9A07G043U_OSTM1_PCLK 15 +#define R9A07G043U_OSTM2_PCLK 16 +#define R9A07G043U_MTU_X_MCK_MTU3 17 +#define R9A07G043U_POE3_CLKM_POE 18 +#define R9A07G043U_WDT0_PCLK 19 +#define R9A07G043U_WDT0_CLK 20 +#define R9A07G043U_WDT2_PCLK 21 +#define R9A07G043U_WDT2_CLK 22 +#define R9A07G043U_SPI_CLK2 23 +#define R9A07G043U_SPI_CLK 24 +#define R9A07G043U_SDHI0_IMCLK 25 +#define R9A07G043U_SDHI0_IMCLK2 26 +#define R9A07G043U_SDHI0_CLK_HS 27 +#define R9A07G043U_SDHI0_ACLK 28 +#define R9A07G043U_SDHI1_IMCLK 29 +#define R9A07G043U_SDHI1_IMCLK2 30 +#define R9A07G043U_SDHI1_CLK_HS 31 +#define R9A07G043U_SDHI1_ACLK 32 +#define R9A07G043U_ISU_ACLK 33 +#define R9A07G043U_ISU_PCLK 34 +#define R9A07G043U_CRU_SYSCLK 35 +#define R9A07G043U_CRU_VCLK 36 +#define R9A07G043U_CRU_PCLK 37 +#define R9A07G043U_CRU_ACLK 38 +#define R9A07G043U_LCDC_CLK_A 39 +#define R9A07G043U_LCDC_CLK_P 40 +#define R9A07G043U_LCDC_CLK_D 41 +#define R9A07G043U_SSI0_PCLK2 42 +#define R9A07G043U_SSI0_PCLK_SFR 43 +#define R9A07G043U_SSI1_PCLK2 44 +#define R9A07G043U_SSI1_PCLK_SFR 45 +#define R9A07G043U_SSI2_PCLK2 46 +#define R9A07G043U_SSI2_PCLK_SFR 47 +#define R9A07G043U_SSI3_PCLK2 48 +#define R9A07G043U_SSI3_PCLK_SFR 49 +#define R9A07G043U_SRC_CLKP 50 +#define R9A07G043U_USB_U2H0_HCLK 51 +#define R9A07G043U_USB_U2H1_HCLK 52 +#define R9A07G043U_USB_U2P_EXR_CPUCLK 53 +#define R9A07G043U_USB_PCLK 54 +#define R9A07G043U_ETH0_CLK_AXI 55 +#define R9A07G043U_ETH0_CLK_CHI 56 +#define R9A07G043U_ETH1_CLK_AXI 57 +#define R9A07G043U_ETH1_CLK_CHI 58 +#define R9A07G043U_I2C0_PCLK 59 +#define R9A07G043U_I2C1_PCLK 60 +#define R9A07G043U_I2C2_PCLK 61 +#define R9A07G043U_I2C3_PCLK 62 +#define R9A07G043U_SCIF0_CLK_PCK 63 +#define R9A07G043U_SCIF1_CLK_PCK 64 +#define R9A07G043U_SCIF2_CLK_PCK 65 +#define R9A07G043U_SCIF3_CLK_PCK 66 +#define R9A07G043U_SCIF4_CLK_PCK 67 +#define R9A07G043U_SCI0_CLKP 68 +#define R9A07G043U_SCI1_CLKP 69 +#define R9A07G043U_IRDA_CLKP 70 +#define R9A07G043U_RSPI0_CLKB 71 +#define R9A07G043U_RSPI1_CLKB 72 +#define R9A07G043U_RSPI2_CLKB 73 +#define R9A07G043U_CANFD_PCLK 74 +#define R9A07G043U_GPIO_HCLK 75 +#define R9A07G043U_ADC_ADCLK 76 +#define R9A07G043U_ADC_PCLK 77 +#define R9A07G043U_TSU_PCLK 78 + +/* R9A07G043U Resets */ +#define R9A07G043U_CA55_RST_1_0 0 +#define R9A07G043U_CA55_RST_1_1 1 +#define R9A07G043U_CA55_RST_3_0 2 +#define R9A07G043U_CA55_RST_3_1 3 +#define R9A07G043U_CA55_RST_4 4 +#define R9A07G043U_CA55_RST_5 5 +#define R9A07G043U_CA55_RST_6 6 +#define R9A07G043U_CA55_RST_7 7 +#define R9A07G043U_CA55_RST_8 8 +#define R9A07G043U_CA55_RST_9 9 +#define R9A07G043U_CA55_RST_10 10 +#define R9A07G043U_CA55_RST_11 11 +#define R9A07G043U_CA55_RST_12 12 +#define R9A07G043U_GIC600_GICRESET_N 13 +#define R9A07G043U_GIC600_DBG_GICRESET_N 14 +#define R9A07G043U_IA55_RESETN 15 +#define R9A07G043U_MHU_RESETN 16 +#define R9A07G043U_DMAC_ARESETN 17 +#define R9A07G043U_DMAC_RST_ASYNC 18 +#define R9A07G043U_SYC_RESETN 19 +#define R9A07G043U_OSTM0_PRESETZ 20 +#define R9A07G043U_OSTM1_PRESETZ 21 +#define R9A07G043U_OSTM2_PRESETZ 22 +#define R9A07G043U_MTU_X_PRESET_MTU3 23 +#define R9A07G043U_POE3_RST_M_REG 24 +#define R9A07G043U_WDT0_PRESETN 25 +#define R9A07G043U_WDT2_PRESETN 26 +#define R9A07G043U_SPI_RST 27 +#define R9A07G043U_SDHI0_IXRST 28 +#define R9A07G043U_SDHI1_IXRST 29 +#define R9A07G043U_ISU_ARESETN 30 +#define R9A07G043U_ISU_PRESETN 31 +#define R9A07G043U_CRU_CMN_RSTB 32 +#define R9A07G043U_CRU_PRESETN 33 +#define R9A07G043U_CRU_ARESETN 34 +#define R9A07G043U_SRC_RST 35 +#define R9A07G043U_USB_U2H0_HRESETN 36 +#define R9A07G043U_USB_U2H1_HRESETN 37 +#define R9A07G043U_USB_U2P_EXL_SYSRST 38 +#define R9A07G043U_USB_PRESETN 39 +#define R9A07G043U_I2C0_MRST 40 +#define R9A07G043U_I2C1_MRST 41 +#define R9A07G043U_I2C2_MRST 42 +#define R9A07G043U_I2C3_MRST 43 +#define R9A07G043U_SCI0_RST 44 +#define R9A07G043U_SCI1_RST 45 +#define R9A07G043U_IRDA_RST 46 +#define R9A07G043U_RSPI0_RST 46 +#define R9A07G043U_RSPI1_RST 48 +#define R9A07G043U_RSPI2_RST 49 +#define R9A07G043U_CANFD_RSTP_N 50 +#define R9A07G043U_CANFD_RSTC_N 51 +#define R9A07G043U_GPIO_RSTN 52 +#define R9A07G043U_GPIO_PORT_RESETN 53 +#define R9A07G043U_GPIO_SPARE_RESETN 54 +#define R9A07G043U_TSU_PRESETN 55 +#define R9A07G043U_SSI0_RST_M2_REG 56 +#define R9A07G043U_SSI1_RST_M2_REG 57 +#define R9A07G043U_SSI2_RST_M2_REG 58 +#define R9A07G043U_ETH0_RST_HW_N 59 +#define R9A07G043U_SCIF0_RST_SYSTEM_N 60 +#define R9A07G043U_SCIF1_RST_SYSTEM_N 61 +#define R9A07G043U_SCIF2_RST_SYSTEM_N 62 +#define R9A07G043U_SCIF3_RST_SYSTEM_N 63 + +/* Type-1 Specific */ +#define R9A07G043U_SSI3_RST_M2_REG 64 +#define R9A07G043U_ETH1_RST_HW_N 65 +#define R9A07G043U_SCIF4_RST_SYSTEM_N 66 +#define R9A07G043U_ADC_PRESETN 67 +#define R9A07G043U_ADC_ADRST_N 68 +#define R9A07G043U_LCDC_RESET_N 69 + +#endif /* __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__ */ From patchwork Thu Mar 3 12:13:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1600309 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4K8VJq1w81z9sG6 for ; Thu, 3 Mar 2022 23:14:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233094AbiCCMOq (ORCPT ); Thu, 3 Mar 2022 07:14:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231876AbiCCMOq (ORCPT ); Thu, 3 Mar 2022 07:14:46 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 01E43157216; Thu, 3 Mar 2022 04:14:00 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.90,151,1643641200"; d="scan'208";a="112218619" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 03 Mar 2022 21:14:00 +0900 Received: from localhost.localdomain (unknown [10.226.93.138]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 6C8FC42F4DB2; Thu, 3 Mar 2022 21:13:58 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd , Rob Herring Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH 4/7] dt-bindings: clock: renesas: Document RZ/G2UL SoC Date: Thu, 3 Mar 2022 12:13:43 +0000 Message-Id: <20220303121346.4769-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220303121346.4769-1-biju.das.jz@bp.renesas.com> References: <20220303121346.4769-1-biju.das.jz@bp.renesas.com> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the device tree binding for the Renesas RZ/G2UL Type-1 and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1 SoC. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- .../devicetree/bindings/clock/renesas,rzg2l-cpg.yaml | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index bd3af8fc616b..256258025c26 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -4,13 +4,13 @@ $id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode +title: Renesas RZ/{G2L,G2UL,V2L} Clock Pulse Generator / Module Standby Mode maintainers: - Geert Uytterhoeven description: | - On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module + On Renesas RZ/{G2L,G2UL,V2L} SoC, the CPG (Clock Pulse Generator) and Module Standby Mode share the same register block. They provide the following functionalities: @@ -23,8 +23,9 @@ description: | properties: compatible: enum: - - renesas,r9a07g044-cpg # RZ/G2{L,LC} - - renesas,r9a07g054-cpg # RZ/V2L + - renesas,r9a07g043u-cpg # RZ/G2UL{Type-1,Type-2} + - renesas,r9a07g044-cpg # RZ/G2{L,LC} + - renesas,r9a07g054-cpg # RZ/V2L reg: maxItems: 1