From patchwork Fri Jan 21 07:53:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qin Jian X-Patchwork-Id: 1582462 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JgBYt66v3z9sCD for ; Fri, 21 Jan 2022 18:57:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379279AbiAUH5h (ORCPT ); Fri, 21 Jan 2022 02:57:37 -0500 Received: from mx1.cqplus1.com ([113.204.237.245]:55776 "EHLO mx1.cqplus1.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349271AbiAUH4q (ORCPT ); Fri, 21 Jan 2022 02:56:46 -0500 X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by mx1.cqplus1.com with MailGates ESMTP Server V5.0(24938:0:AUTH_RELAY) (envelope-from ); Fri, 21 Jan 2022 15:53:23 +0800 (CST) From: Qin Jian To: robh+dt@kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, linux@armlinux.org.uk, broonie@kernel.org, arnd@arndb.de, stefan.wahren@i2se.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, wells.lu@sunplus.com, Qin Jian , Rob Herring Subject: [PATCH v8 01/10] dt-bindings: vendor-prefixes: Add Sunplus Date: Fri, 21 Jan 2022 15:53:09 +0800 Message-Id: <2e74a1339a5ea54d92fdc4d1998a2b169e23b82b.1642751015.git.qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add vendor prefix for Sunplus Technology Co., Ltd. (http://www.sunplus.com) Acked-by: Rob Herring Signed-off-by: Qin Jian --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index a867f7102..50d4ee5ac 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1131,6 +1131,8 @@ patternProperties: description: Summit microelectronics "^sunchip,.*": description: Shenzhen Sunchip Technology Co., Ltd + "^sunplus,.*": + description: Sunplus Technology Co., Ltd. "^SUNW,.*": description: Sun Microsystems, Inc "^supermicro,.*": From patchwork Fri Jan 21 07:53:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qin Jian X-Patchwork-Id: 1582463 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JgBYv1bYvz9s1l for ; Fri, 21 Jan 2022 18:57:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379343AbiAUH5h (ORCPT ); Fri, 21 Jan 2022 02:57:37 -0500 Received: from mx1.cqplus1.com ([113.204.237.245]:55768 "EHLO mx1.cqplus1.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379081AbiAUH4j (ORCPT ); Fri, 21 Jan 2022 02:56:39 -0500 X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by mx1.cqplus1.com with MailGates ESMTP Server V5.0(24938:0:AUTH_RELAY) (envelope-from ); Fri, 21 Jan 2022 15:53:23 +0800 (CST) From: Qin Jian To: robh+dt@kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, linux@armlinux.org.uk, broonie@kernel.org, arnd@arndb.de, stefan.wahren@i2se.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, wells.lu@sunplus.com, Qin Jian , Rob Herring Subject: [PATCH v8 02/10] dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards Date: Fri, 21 Jan 2022 15:53:10 +0800 Message-Id: <87cc20bb3ef747c4da89f9e60c0847532bb0a679.1642751015.git.qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This introduces bindings for boards based Sunplus SP7021 SoC. Reviewed-by: Rob Herring Signed-off-by: Qin Jian --- .../bindings/arm/sunplus,sp7021.yaml | 27 +++++++++++++++++++ MAINTAINERS | 7 +++++ 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml diff --git a/Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml b/Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml new file mode 100644 index 000000000..5b9985b73 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sunplus,sp7021.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 Boards Device Tree Bindings + +maintainers: + - qinjian + +description: | + ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC. + Wiki: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: sunplus,sp7021-achip + +additionalProperties: true + +... diff --git a/MAINTAINERS b/MAINTAINERS index e0bca0de0..6a5422f10 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2655,6 +2655,13 @@ F: drivers/clocksource/armv7m_systick.c N: stm32 N: stm +ARM/SUNPLUS SP7021 SOC SUPPORT +M: Qin Jian +L: linux-arm-kernel@lists.infradead.org (moderated for mon-subscribers) +S: Maintained +W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview +F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml + ARM/Synaptics SoC support M: Jisheng Zhang M: Sebastian Hesselbarth From patchwork Fri Jan 21 07:53:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qin Jian X-Patchwork-Id: 1582465 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JgBYw2ftfz9sCD for ; Fri, 21 Jan 2022 18:57:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379285AbiAUH5h (ORCPT ); Fri, 21 Jan 2022 02:57:37 -0500 Received: from mx1.cqplus1.com ([113.204.237.245]:55780 "EHLO mx1.cqplus1.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349221AbiAUH4q (ORCPT ); Fri, 21 Jan 2022 02:56:46 -0500 X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by mx1.cqplus1.com with MailGates ESMTP Server V5.0(24938:0:AUTH_RELAY) (envelope-from ); Fri, 21 Jan 2022 15:53:24 +0800 (CST) From: Qin Jian To: robh+dt@kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, linux@armlinux.org.uk, broonie@kernel.org, arnd@arndb.de, stefan.wahren@i2se.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, wells.lu@sunplus.com, Qin Jian , Rob Herring Subject: [PATCH v8 03/10] dt-bindings: reset: Add bindings for SP7021 reset driver Date: Fri, 21 Jan 2022 15:53:11 +0800 Message-Id: <6444261d9d4179839ce8f828a9814a057821082a.1642751015.git.qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation to describe Sunplus SP7021 reset driver bindings. Reviewed-by: Rob Herring Signed-off-by: Qin Jian --- .../bindings/reset/sunplus,reset.yaml | 38 ++++++++ MAINTAINERS | 2 + include/dt-bindings/reset/sp-sp7021.h | 97 +++++++++++++++++++ 3 files changed, 137 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/sunplus,reset.yaml create mode 100644 include/dt-bindings/reset/sp-sp7021.h diff --git a/Documentation/devicetree/bindings/reset/sunplus,reset.yaml b/Documentation/devicetree/bindings/reset/sunplus,reset.yaml new file mode 100644 index 000000000..c083c821f --- /dev/null +++ b/Documentation/devicetree/bindings/reset/sunplus,reset.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/sunplus,reset.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Sunplus SoC Reset Controller + +maintainers: + - Qin Jian + +properties: + compatible: + const: sunplus,sp7021-reset + + "#reset-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#reset-cells" + - reg + +additionalProperties: false + +examples: + - | + rstc: reset@9c000054 { + compatible = "sunplus,sp7021-reset"; + #reset-cells = <1>; + reg = <0x9c000054 0x28>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 6a5422f10..652f42cab 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2661,6 +2661,8 @@ L: linux-arm-kernel@lists.infradead.org (moderated for mon-subscribers) S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml +F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support M: Jisheng Zhang diff --git a/include/dt-bindings/reset/sp-sp7021.h b/include/dt-bindings/reset/sp-sp7021.h new file mode 100644 index 000000000..fd2a50327 --- /dev/null +++ b/include/dt-bindings/reset/sp-sp7021.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + */ +#ifndef _DT_BINDINGS_RST_SUNPLUS_SP7021_H +#define _DT_BINDINGS_RST_SUNPLUS_SP7021_H + +/* mo_reset0 ~ mo_reset9 */ +#define RST_SYSTEM 0x00 +#define RST_RTC 0x02 +#define RST_IOCTL 0x03 +#define RST_IOP 0x04 +#define RST_OTPRX 0x05 +#define RST_NOC 0x06 +#define RST_BR 0x07 +#define RST_RBUS_L00 0x08 +#define RST_SPIFL 0x09 +#define RST_SDCTRL0 0x0a +#define RST_PERI0 0x0b +#define RST_A926 0x0d +#define RST_UMCTL2 0x0e +#define RST_PERI1 0x0f + +#define RST_DDR_PHY0 0x10 +#define RST_ACHIP 0x12 +#define RST_STC0 0x14 +#define RST_STC_AV0 0x15 +#define RST_STC_AV1 0x16 +#define RST_STC_AV2 0x17 +#define RST_UA0 0x18 +#define RST_UA1 0x19 +#define RST_UA2 0x1a +#define RST_UA3 0x1b +#define RST_UA4 0x1c +#define RST_HWUA 0x1d +#define RST_DDC0 0x1e +#define RST_UADMA 0x1f + +#define RST_CBDMA0 0x20 +#define RST_CBDMA1 0x21 +#define RST_SPI_COMBO_0 0x22 +#define RST_SPI_COMBO_1 0x23 +#define RST_SPI_COMBO_2 0x24 +#define RST_SPI_COMBO_3 0x25 +#define RST_AUD 0x26 +#define RST_USBC0 0x2a +#define RST_USBC1 0x2b +#define RST_UPHY0 0x2d +#define RST_UPHY1 0x2e + +#define RST_I2CM0 0x30 +#define RST_I2CM1 0x31 +#define RST_I2CM2 0x32 +#define RST_I2CM3 0x33 +#define RST_PMC 0x3d +#define RST_CARD_CTL0 0x3e +#define RST_CARD_CTL1 0x3f + +#define RST_CARD_CTL4 0x42 +#define RST_BCH 0x44 +#define RST_DDFCH 0x4b +#define RST_CSIIW0 0x4c +#define RST_CSIIW1 0x4d +#define RST_MIPICSI0 0x4e +#define RST_MIPICSI1 0x4f + +#define RST_HDMI_TX 0x50 +#define RST_VPOST 0x55 + +#define RST_TGEN 0x60 +#define RST_DMIX 0x61 +#define RST_TCON 0x6a +#define RST_INTERRUPT 0x6f + +#define RST_RGST 0x70 +#define RST_GPIO 0x73 +#define RST_RBUS_TOP 0x74 + +#define RST_MAILBOX 0x86 +#define RST_SPIND 0x8a +#define RST_I2C2CBUS 0x8b +#define RST_SEC 0x8d +#define RST_DVE 0x8e +#define RST_GPOST0 0x8f + +#define RST_OSD0 0x90 +#define RST_DISP_PWM 0x92 +#define RST_UADBG 0x93 +#define RST_DUMMY_MASTER 0x94 +#define RST_FIO_CTL 0x95 +#define RST_FPGA 0x96 +#define RST_L2SW 0x97 +#define RST_ICM 0x98 +#define RST_AXI_GLOBAL 0x99 + +#endif From patchwork Fri Jan 21 07:53:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qin Jian X-Patchwork-Id: 1582461 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JgBYt3hnQz9s1l for ; Fri, 21 Jan 2022 18:57:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379244AbiAUH5g (ORCPT ); Fri, 21 Jan 2022 02:57:36 -0500 Received: from mx1.cqplus1.com ([113.204.237.245]:55772 "EHLO mx1.cqplus1.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236875AbiAUH4i (ORCPT ); Fri, 21 Jan 2022 02:56:38 -0500 X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by mx1.cqplus1.com with MailGates ESMTP Server V5.0(24938:0:AUTH_RELAY) (envelope-from ); Fri, 21 Jan 2022 15:53:24 +0800 (CST) From: Qin Jian To: robh+dt@kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, linux@armlinux.org.uk, broonie@kernel.org, arnd@arndb.de, stefan.wahren@i2se.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, wells.lu@sunplus.com, Qin Jian Subject: [PATCH v8 05/10] dt-bindings: clock: Add bindings for SP7021 clock driver Date: Fri, 21 Jan 2022 15:53:13 +0800 Message-Id: <504303c7cf92af8368dcda0cdde3b9c15a833418.1642751015.git.qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation to describe Sunplus SP7021 clock driver bindings. Signed-off-by: Qin Jian Reviewed-by: Stephen Boyd Reviewed-by: Rob Herring --- Add clocks & clock-names. --- .../bindings/clock/sunplus,sp7021-clkc.yaml | 52 ++++++++ MAINTAINERS | 2 + include/dt-bindings/clock/sp-sp7021.h | 112 ++++++++++++++++++ 3 files changed, 166 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml create mode 100644 include/dt-bindings/clock/sp-sp7021.h diff --git a/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml b/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml new file mode 100644 index 000000000..e6d098cf4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 SoC Clock Controller Binding + +maintainers: + - Qin Jian + +properties: + compatible: + const: sunplus,sp7021-clkc + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + + clocks: + items: + - description: External oscillator clock + - description: System clock + + clock-names: + items: + - const: extclk + - const: pllsys + +required: + - compatible + - "#clock-cells" + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + clkc: clock-controller@9c000000 { + compatible = "sunplus,sp7021-clkc"; + #clock-cells = <1>; + reg = <0x9c000000 0x280>; + clocks = <&extclk>, <&clkc PLL_SYS>; + clock-names = "extclk", "pllsys"; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 6caffd6d0..90ebb823f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2661,8 +2661,10 @@ L: linux-arm-kernel@lists.infradead.org (moderated for mon-subscribers) S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml +F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/reset/reset-sunplus.c +F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support diff --git a/include/dt-bindings/clock/sp-sp7021.h b/include/dt-bindings/clock/sp-sp7021.h new file mode 100644 index 000000000..45dac6de8 --- /dev/null +++ b/include/dt-bindings/clock/sp-sp7021.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + */ +#ifndef _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H +#define _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H + +#define XTAL 27000000 + +/* plls */ +#define PLL_A 0 +#define PLL_E 1 +#define PLL_E_2P5 2 +#define PLL_E_25 3 +#define PLL_E_112P5 4 +#define PLL_F 5 +#define PLL_TV 6 +#define PLL_TV_A 7 +#define PLL_SYS 8 + +/* gates: mo_clken0 ~ mo_clken9 */ +#define CLK_SYSTEM 0x10 +#define CLK_RTC 0x12 +#define CLK_IOCTL 0x13 +#define CLK_IOP 0x14 +#define CLK_OTPRX 0x15 +#define CLK_NOC 0x16 +#define CLK_BR 0x17 +#define CLK_RBUS_L00 0x18 +#define CLK_SPIFL 0x19 +#define CLK_SDCTRL0 0x1a +#define CLK_PERI0 0x1b +#define CLK_A926 0x1d +#define CLK_UMCTL2 0x1e +#define CLK_PERI1 0x1f + +#define CLK_DDR_PHY0 0x20 +#define CLK_ACHIP 0x22 +#define CLK_STC0 0x24 +#define CLK_STC_AV0 0x25 +#define CLK_STC_AV1 0x26 +#define CLK_STC_AV2 0x27 +#define CLK_UA0 0x28 +#define CLK_UA1 0x29 +#define CLK_UA2 0x2a +#define CLK_UA3 0x2b +#define CLK_UA4 0x2c +#define CLK_HWUA 0x2d +#define CLK_DDC0 0x2e +#define CLK_UADMA 0x2f + +#define CLK_CBDMA0 0x30 +#define CLK_CBDMA1 0x31 +#define CLK_SPI_COMBO_0 0x32 +#define CLK_SPI_COMBO_1 0x33 +#define CLK_SPI_COMBO_2 0x34 +#define CLK_SPI_COMBO_3 0x35 +#define CLK_AUD 0x36 +#define CLK_USBC0 0x3a +#define CLK_USBC1 0x3b +#define CLK_UPHY0 0x3d +#define CLK_UPHY1 0x3e + +#define CLK_I2CM0 0x40 +#define CLK_I2CM1 0x41 +#define CLK_I2CM2 0x42 +#define CLK_I2CM3 0x43 +#define CLK_PMC 0x4d +#define CLK_CARD_CTL0 0x4e +#define CLK_CARD_CTL1 0x4f + +#define CLK_CARD_CTL4 0x52 +#define CLK_BCH 0x54 +#define CLK_DDFCH 0x5b +#define CLK_CSIIW0 0x5c +#define CLK_CSIIW1 0x5d +#define CLK_MIPICSI0 0x5e +#define CLK_MIPICSI1 0x5f + +#define CLK_HDMI_TX 0x60 +#define CLK_VPOST 0x65 + +#define CLK_TGEN 0x70 +#define CLK_DMIX 0x71 +#define CLK_TCON 0x7a +#define CLK_INTERRUPT 0x7f + +#define CLK_RGST 0x80 +#define CLK_GPIO 0x83 +#define CLK_RBUS_TOP 0x84 + +#define CLK_MAILBOX 0x96 +#define CLK_SPIND 0x9a +#define CLK_I2C2CBUS 0x9b +#define CLK_SEC 0x9d +#define CLK_DVE 0x9e +#define CLK_GPOST0 0x9f + +#define CLK_OSD0 0xa0 +#define CLK_DISP_PWM 0xa2 +#define CLK_UADBG 0xa3 +#define CLK_DUMMY_MASTER 0xa4 +#define CLK_FIO_CTL 0xa5 +#define CLK_FPGA 0xa6 +#define CLK_L2SW 0xa7 +#define CLK_ICM 0xa8 +#define CLK_AXI_GLOBAL 0xa9 + +#define CLK_MAX 0xb0 + +#endif From patchwork Fri Jan 21 07:53:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qin Jian X-Patchwork-Id: 1582464 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JgBYw0FgPz9s1l for ; Fri, 21 Jan 2022 18:57:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379081AbiAUH5i (ORCPT ); Fri, 21 Jan 2022 02:57:38 -0500 Received: from mx1.cqplus1.com ([113.204.237.245]:55786 "EHLO mx1.cqplus1.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379247AbiAUH4q (ORCPT ); Fri, 21 Jan 2022 02:56:46 -0500 X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by mx1.cqplus1.com with MailGates ESMTP Server V5.0(24938:0:AUTH_RELAY) (envelope-from ); Fri, 21 Jan 2022 15:53:25 +0800 (CST) From: Qin Jian To: robh+dt@kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, linux@armlinux.org.uk, broonie@kernel.org, arnd@arndb.de, stefan.wahren@i2se.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, wells.lu@sunplus.com, Qin Jian , Rob Herring Subject: [PATCH v8 07/10] dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt controller Date: Fri, 21 Jan 2022 15:53:15 +0800 Message-Id: <5e7f28ecab70fbe39727ace4758a306afe723dd1.1642751015.git.qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation to describe Sunplus SP7021 interrupt controller bindings. Reviewed-by: Rob Herring Signed-off-by: Qin Jian --- .../sunplus,sp7021-intc.yaml | 62 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml new file mode 100644 index 000000000..5daeab63c --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sunplus,sp7021-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 SoC Interrupt Controller Device Tree Bindings + +maintainers: + - Qin Jian + +properties: + compatible: + items: + - const: sunplus,sp7021-intc + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + description: + The first cell is the IRQ number, the second cell is the trigger + type as defined in interrupt.txt in this directory. + + reg: + maxItems: 2 + description: + Specifies base physical address(s) and size of the controller regs. + The 1st region include type/polarity/priority/mask regs. + The 2nd region include clear/masked_ext0/masked_ext1/group regs. + + interrupts: + maxItems: 2 + description: + EXT_INT0 & EXT_INT1, 2 interrupts references to primary interrupt + controller. + +required: + - compatible + - interrupt-controller + - "#interrupt-cells" + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + + intc: interrupt-controller@9c000780 { + compatible = "sunplus,sp7021-intc"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x9c000780 0x80>, <0x9c000a80 0x80>; + interrupt-parent = <&gic>; + interrupts = , /* EXT_INT0 */ + ; /* EXT_INT1 */ + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 5069f552f..6b3bbe021 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2662,6 +2662,7 @@ S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml +F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/clk/clk-sp7021.c F: drivers/reset/reset-sunplus.c