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Fri, 14 Jan 2022 08:20:22 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng Cc: Atish Patra , Alistair Francis , Anup Patel , U-Boot Mailing List , Anup Patel , Philipp Tomsich Subject: [PATCH 1/3] serial: Add RISC-V HTIF console driver Date: Fri, 14 Jan 2022 21:50:06 +0530 Message-Id: <20220114162008.70468-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220114162008.70468-1-apatel@ventanamicro.com> References: <20220114162008.70468-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 14 Jan 2022 17:48:29 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Quite a few RISC-V emulators and ISS (including Spike) have host transfer interface (HTIF) based console. This patch adds HTIF based console driver for RISC-V platforms which depends totally on DT node for HTIF register base address. Signed-off-by: Anup Patel Reviewed-by: Philipp Tomsich Reviewed-by: Rick Chen --- drivers/serial/Kconfig | 8 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_htif.c | 178 +++++++++++++++++++++++++++++++++++ 3 files changed, 187 insertions(+) create mode 100644 drivers/serial/serial_htif.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 6c8fdda9a0..345d1881f5 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -866,6 +866,14 @@ config PXA_SERIAL If you have a machine based on a Marvell XScale PXA2xx CPU you can enable its onboard serial ports by enabling this option. +config HTIF_CONSOLE + bool "RISC-V HTIF console support" + depends on DM_SERIAL && 64BIT + help + Select this to enable host transfer interface (HTIF) based serial + console. The HTIF device is quite common in RISC-V emulators and + RISC-V ISS so this driver allows using U-Boot on such platforms. + config SIFIVE_SERIAL bool "SiFive UART support" depends on DM_SERIAL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 8168af640f..52e70aa191 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_OWL_SERIAL) += serial_owl.o obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o obj-$(CONFIG_MT7620_SERIAL) += serial_mt7620.o +obj-$(CONFIG_HTIF_CONSOLE) += serial_htif.o obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o obj-$(CONFIG_XEN_SERIAL) += serial_xen.o diff --git a/drivers/serial/serial_htif.c b/drivers/serial/serial_htif.c new file mode 100644 index 0000000000..5d2bf0aaeb --- /dev/null +++ b/drivers/serial/serial_htif.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define HTIF_DATA_BITS 48 +#define HTIF_DATA_MASK ((1ULL << HTIF_DATA_BITS) - 1) +#define HTIF_DATA_SHIFT 0 +#define HTIF_CMD_BITS 8 +#define HTIF_CMD_MASK ((1ULL << HTIF_CMD_BITS) - 1) +#define HTIF_CMD_SHIFT 48 +#define HTIF_DEV_BITS 8 +#define HTIF_DEV_MASK ((1ULL << HTIF_DEV_BITS) - 1) +#define HTIF_DEV_SHIFT 56 + +#define HTIF_DEV_SYSTEM 0 +#define HTIF_DEV_CONSOLE 1 + +#define HTIF_CONSOLE_CMD_GETC 0 +#define HTIF_CONSOLE_CMD_PUTC 1 + +#if __riscv_xlen == 64 +# define TOHOST_CMD(dev, cmd, payload) \ + (((u64)(dev) << HTIF_DEV_SHIFT) | \ + ((u64)(cmd) << HTIF_CMD_SHIFT) | \ + (u64)(payload)) +#else +# define TOHOST_CMD(dev, cmd, payload) ({ \ + if ((dev) || (cmd)) \ + __builtin_trap(); \ + (payload); }) +#endif +#define FROMHOST_DEV(fromhost_value) \ + ((u64)((fromhost_value) >> HTIF_DEV_SHIFT) & HTIF_DEV_MASK) +#define FROMHOST_CMD(fromhost_value) \ + ((u64)((fromhost_value) >> HTIF_CMD_SHIFT) & HTIF_CMD_MASK) +#define FROMHOST_DATA(fromhost_value) \ + ((u64)((fromhost_value) >> HTIF_DATA_SHIFT) & HTIF_DATA_MASK) + +struct htif_plat { + void *fromhost; + void *tohost; + int console_char; +}; + +static void __check_fromhost(struct htif_plat *plat) +{ + u64 fh = readq(plat->fromhost); + + if (!fh) + return; + writeq(0, plat->fromhost); + + /* this should be from the console */ + if (FROMHOST_DEV(fh) != HTIF_DEV_CONSOLE) + __builtin_trap(); + switch (FROMHOST_CMD(fh)) { + case HTIF_CONSOLE_CMD_GETC: + plat->console_char = 1 + (u8)FROMHOST_DATA(fh); + break; + case HTIF_CONSOLE_CMD_PUTC: + break; + default: + __builtin_trap(); + } +} + +static void __set_tohost(struct htif_plat *plat, + u64 dev, u64 cmd, u64 data) +{ + while (readq(plat->tohost)) + __check_fromhost(plat); + writeq(TOHOST_CMD(dev, cmd, data), plat->tohost); +} + +static int htif_serial_putc(struct udevice *dev, const char ch) +{ + struct htif_plat *plat = dev_get_plat(dev); + + __set_tohost(plat, HTIF_DEV_CONSOLE, HTIF_CONSOLE_CMD_PUTC, ch); + return 0; +} + +static int htif_serial_getc(struct udevice *dev) +{ + int ch; + struct htif_plat *plat = dev_get_plat(dev); + + if (plat->console_char < 0) + __check_fromhost(plat); + + if (plat->console_char >= 0) { + ch = plat->console_char; + plat->console_char = -1; + __set_tohost(plat, HTIF_DEV_CONSOLE, HTIF_CONSOLE_CMD_GETC, 0); + return (ch) ? ch - 1 : -EAGAIN; + } + + return -EAGAIN; +} + +static int htif_serial_pending(struct udevice *dev, bool input) +{ + struct htif_plat *plat = dev_get_plat(dev); + + if (!input) + return 0; + + if (plat->console_char < 0) + __check_fromhost(plat); + + return (plat->console_char >= 0) ? 1 : 0; +} + +static int htif_serial_probe(struct udevice *dev) +{ + struct htif_plat *plat = dev_get_plat(dev); + + /* Queue first getc request */ + __set_tohost(plat, HTIF_DEV_CONSOLE, HTIF_CONSOLE_CMD_GETC, 0); + + return 0; +} + +static int htif_serial_of_to_plat(struct udevice *dev) +{ + fdt_addr_t addr; + struct htif_plat *plat = dev_get_plat(dev); + + addr = dev_read_addr_index(dev, 0); + if (addr == FDT_ADDR_T_NONE) + return -ENODEV; + plat->fromhost = (void *)(uintptr_t)addr; + plat->tohost = plat->fromhost + sizeof(u64); + + addr = dev_read_addr_index(dev, 1); + if (addr != FDT_ADDR_T_NONE) + plat->tohost = (void *)(uintptr_t)addr; + + plat->console_char = -1; + + return 0; +} + +static const struct dm_serial_ops htif_serial_ops = { + .putc = htif_serial_putc, + .getc = htif_serial_getc, + .pending = htif_serial_pending, +}; + +static const struct udevice_id htif_serial_ids[] = { + { .compatible = "ucb,htif0" }, + { } +}; + +U_BOOT_DRIVER(serial_htif) = { + .name = "serial_htif", + .id = UCLASS_SERIAL, + .of_match = htif_serial_ids, + .of_to_plat = htif_serial_of_to_plat, + .plat_auto = sizeof(struct htif_plat), + .probe = htif_serial_probe, + .ops = &htif_serial_ops, +}; From patchwork Fri Jan 14 16:20:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1580203 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Fri, 14 Jan 2022 08:20:27 -0800 (PST) Received: from localhost.localdomain ([122.179.78.147]) by smtp.gmail.com with ESMTPSA id bi24sm10797930wmb.9.2022.01.14.08.20.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jan 2022 08:20:26 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng Cc: Atish Patra , Alistair Francis , Anup Patel , U-Boot Mailing List , Anup Patel , Philipp Tomsich Subject: [PATCH 2/3] riscv: qemu: Enable HTIF console support Date: Fri, 14 Jan 2022 21:50:07 +0530 Message-Id: <20220114162008.70468-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220114162008.70468-1-apatel@ventanamicro.com> References: <20220114162008.70468-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 14 Jan 2022 17:48:29 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Enable support for HTIF console so that we can use QEMU RISC-V U-Boot on RISC-V emulators and ISS having it. Signed-off-by: Anup Patel Reviewed-by: Philipp Tomsich Reviewed-by: Rick Chen --- board/emulation/qemu-riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 1bbf1bc84a..f7538bc496 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -56,6 +56,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply DM_SCSI imply SYS_NS16550 imply SIFIVE_SERIAL + imply HTIF_CONSOLE if 64BIT imply SYSRESET imply SYSRESET_CMD_POWEROFF imply SYSRESET_SYSCON From patchwork Fri Jan 14 16:20:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1580204 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=Mno99e9B; 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Fri, 14 Jan 2022 08:20:31 -0800 (PST) Received: from localhost.localdomain ([122.179.78.147]) by smtp.gmail.com with ESMTPSA id bi24sm10797930wmb.9.2022.01.14.08.20.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jan 2022 08:20:30 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng Cc: Atish Patra , Alistair Francis , Anup Patel , U-Boot Mailing List , Anup Patel Subject: [PATCH 3/3] riscv: qemu: Implement is_flash_available() for MTD NOR Date: Fri, 14 Jan 2022 21:50:08 +0530 Message-Id: <20220114162008.70468-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220114162008.70468-1-apatel@ventanamicro.com> References: <20220114162008.70468-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 14 Jan 2022 17:48:29 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Currently, if MTD NOR is enabled then U-Boot tries to issue flash commands even when CFI flash DT node is not present. This causes access fault on RISC-V emulators or ISS which do not emulate CFI flash. To handle this issue, we implement is_flash_available() for qemu-riscv board which will return 1 only if CFI flash DT node is present. Fixes: d248627f9d42 ("riscv: qemu: Enable MTD NOR flash support") Signed-off-by: Anup Patel Reviewed-by: Rick Chen --- board/emulation/qemu-riscv/qemu-riscv.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index b0d9dd59b1..cd02dae1ab 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -16,6 +17,22 @@ DECLARE_GLOBAL_DATA_PTR; +#if IS_ENABLED(CONFIG_MTD_NOR_FLASH) +int is_flash_available(void) +{ + if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) { + const void *fdt = + (const void *)(uintptr_t)gd->arch.firmware_fdt_addr; + int rc = fdt_node_offset_by_compatible(fdt, -1, "cfi-flash"); + + if (rc >= 0) + return 1; + } + + return 0; +} +#endif + int board_init(void) { /*