From patchwork Tue Dec 21 23:32:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiang W X-Patchwork-Id: 1572205 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=126.com header.i=@126.com header.a=rsa-sha256 header.s=s110527 header.b=p/F8PlgH; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JJw7Y1N3yz9sCD for ; Thu, 23 Dec 2021 01:04:57 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 55E268326F; Wed, 22 Dec 2021 15:04:29 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=126.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=126.com header.i=@126.com header.b="p/F8PlgH"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id EEF0482FAF; Wed, 22 Dec 2021 00:33:45 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-m964.mail.126.com (mail-m964.mail.126.com [123.126.96.4]) by phobos.denx.de (Postfix) with ESMTP id 135FD82F87 for ; Wed, 22 Dec 2021 00:33:41 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=126.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=wxjstz@126.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=126.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=wyLbR Le7BgaVaeZ0tyTsL+P4RFhN+sBlPMJNqsZHBLg=; b=p/F8PlgHLopvH7dNoejdA epq0eB4AObzvMWUma5Ur28HwlnFoXAKEPqhVP94woxOT4UTT2dJTLJ7UxOiO+uFW TE8rMvuSTiL+OQ2ZJDgZO4u64MlgSBVqNxF+3Af+2S2YKZsEVOSmwymyGa7Ai5rZ L8DDWJMCzEuuOtnQ5IZRN4= Received: from x390.lan (unknown [58.247.180.72]) by smtp9 (Coremail) with SMTP id NeRpCgC3Fj80ZMJhMzaKAw--.12865S2; Wed, 22 Dec 2021 07:33:09 +0800 (CST) From: Xiang W To: u-boot@lists.denx.de Cc: anup.patel@wdc.com, atish.patra@wdc.com, bmeng.cn@gmail.com, rick@andestech.com, lukas.auer@aisec.fraunhofer.de, Xiang W Subject: [PATCH v2] riscv: cancel the limitation that NR_CPUS is less than or equal to 32 Date: Wed, 22 Dec 2021 07:32:53 +0800 Message-Id: <20211221233253.123268-1-wxjstz@126.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CM-TRANSID: NeRpCgC3Fj80ZMJhMzaKAw--.12865S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxCw18XF4DGry5Jr4rZry7Wrg_yoW5Aw43pr 4DCrn5JFWY9F1fWr1ayryUur4jq3Z5Wr1a9r48uryUAF48ZrWjqr95Kr1UArnFqaykZayF kws3u3Wfu3y8ZwUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07UwTmhUUUUU= X-Originating-IP: [58.247.180.72] X-CM-SenderInfo: pz0m23b26rjloofrz/1tbi5BZwOlpECdPd1AAAs1 X-Mailman-Approved-At: Wed, 22 Dec 2021 15:04:22 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Various specifications of riscv allow the number of hart to be greater than 32. The limit of 32 is determined by gd->arch.available_harts. We can eliminate this limitation through bitmaps. Currently, the number of hart is limited to 4095, and 4095 is the limit of the RISC-V Advanced Core Local Interruptor Specification. Test on sifive unmatched. Signed-off-by: Xiang W Reviewed-by: Leo Yu-Chi Liang --- Changes since v1: * When NR_CPUS is very large, the value of GD_AVAILABLE_HARTS will overflow the immediate range of ld/lw. This patch fixes this problem arch/riscv/Kconfig | 4 ++-- arch/riscv/cpu/start.S | 21 ++++++++++++++++----- arch/riscv/include/asm/global_data.h | 4 +++- arch/riscv/lib/smp.c | 2 +- 4 files changed, 22 insertions(+), 9 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ba29e70acf..7b9c7f5bca 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -220,8 +220,8 @@ config SPL_SMP all, single processor machines. config NR_CPUS - int "Maximum number of CPUs (2-32)" - range 2 32 + int "Maximum number of CPUs (2-4095)" + range 2 4095 depends on SMP || SPL_SMP default 8 help diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 76850ec9be..92f3b78f29 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -166,11 +166,22 @@ wait_for_gd_init: mv gp, s0 /* register available harts in the available_harts mask */ - li t1, 1 - sll t1, t1, tp - LREG t2, GD_AVAILABLE_HARTS(gp) - or t2, t2, t1 - SREG t2, GD_AVAILABLE_HARTS(gp) + li t1, GD_AVAILABLE_HARTS + add t1, t1, gp + LREG t1, 0(t1) +#if defined(CONFIG_ARCH_RV64I) + srli t2, tp, 6 + slli t2, t2, 3 +#elif defined(CONFIG_ARCH_RV32I) + srli t2, tp, 5 + slli t2, t2, 2 +#endif + add t1, t1, t2 + LREG t2, 0(t1) + li t3, 1 + sll t3, t3, tp + or t2, t2, t3 + SREG t2, 0(t1) amoswap.w.rl zero, zero, 0(t0) diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 095484a635..6de2ee0b25 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -10,9 +10,11 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include #include #include #include +#include /* Architecture-specific global data */ struct arch_global_data { @@ -28,7 +30,7 @@ struct arch_global_data { struct ipi_data ipi[CONFIG_NR_CPUS]; #endif #ifndef CONFIG_XIP - ulong available_harts; + ulong available_harts[BITS_TO_LONGS(CONFIG_NR_CPUS)]; #endif }; diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index ba992100ad..e8e391fd41 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -47,7 +47,7 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) #ifndef CONFIG_XIP /* skip if hart is not available */ - if (!(gd->arch.available_harts & (1 << reg))) + if (!test_bit(reg, gd->arch.available_harts)) continue; #endif