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[121.44.67.22]) by smtp.gmail.com with ESMTPSA id p17sm20661731pfh.86.2021.12.20.04.23.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Dec 2021 04:23:04 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 20 Dec 2021 22:22:44 +1000 Message-Id: <20211220122252.986542-2-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211220122252.986542-1-npiggin@gmail.com> References: <20211220122252.986542-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v5 1/9] Introduce hwprobe facility to avoid hard-coding probe functions X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith hwprobe is a little system to have different hardware probing modules run in the dependency order they choose rather than hard coding that order in core/init.c. Reviewed-by: Dan Horák Signed-off-by: Stewart Smith --- core/Makefile.inc | 1 + core/hwprobe.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++ core/init.c | 3 ++ include/skiboot.h | 39 +++++++++++++++++++++++++- skiboot.lds.S | 6 ++++ 5 files changed, 118 insertions(+), 1 deletion(-) create mode 100644 core/hwprobe.c diff --git a/core/Makefile.inc b/core/Makefile.inc index 829800e5b..f80019b6a 100644 --- a/core/Makefile.inc +++ b/core/Makefile.inc @@ -13,6 +13,7 @@ CORE_OBJS += timer.o i2c.o rtc.o flash.o sensor.o ipmi-opal.o CORE_OBJS += flash-subpartition.o bitmap.o buddy.o pci-quirk.o powercap.o psr.o CORE_OBJS += pci-dt-slot.o direct-controls.o cpufeatures.o CORE_OBJS += flash-firmware-versions.o opal-dump.o +CORE_OBJS += hwprobe.o ifeq ($(SKIBOOT_GCOV),1) CORE_OBJS += gcov-profiling.o diff --git a/core/hwprobe.c b/core/hwprobe.c new file mode 100644 index 000000000..0a641ada5 --- /dev/null +++ b/core/hwprobe.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2021 Stewart Smith */ + +#define pr_fmt(fmt) "HWPROBE: " fmt +#include +#include + +static bool hwprobe_deps_satisfied(const struct hwprobe *hwp) +{ + struct hwprobe *hwprobe; + const char **dep; + unsigned int i; + + dep = hwp->deps; + if (dep == NULL) + return true; + + + prlog(PR_TRACE, "Checking deps for %s\n", hwp->name); + + while (*dep != NULL) { + prlog(PR_TRACE, "Checking %s dep %s\n", hwp->name, *dep); + hwprobe = &__hwprobes_start; + for (i = 0; &hwprobe[i] < &__hwprobes_end; i++) { + if(strcmp(hwprobe[i].name, *dep) == 0 && + !hwprobe[i].probed) + return false; + } + dep++; + } + + prlog(PR_TRACE, "deps for %s are satisfied!\n", hwp->name); + return true; + +} + +void probe_hardware(void) +{ + struct hwprobe *hwprobe; + unsigned int i; + bool work_todo = true; + bool did_something = true; + + while (work_todo) { + work_todo = false; + did_something = false; + hwprobe = &__hwprobes_start; + prlog(PR_DEBUG, "Begin loop\n"); + for (i = 0; &hwprobe[i] < &__hwprobes_end; i++) { + if (hwprobe[i].probed) + continue; + if (hwprobe_deps_satisfied(&hwprobe[i])) { + prlog(PR_DEBUG, "Probing %s...\n", hwprobe[i].name); + if (hwprobe[i].probe) + hwprobe[i].probe(); + did_something = true; + hwprobe[i].probed = true; + } else { + prlog(PR_DEBUG, "Dependencies for %s not yet satisfied, skipping\n", + hwprobe[i].name); + work_todo = true; + } + } + + if (work_todo && !did_something) { + prlog(PR_ERR, "Cannot satisfy dependencies! Bailing out\n"); + break; + } + } +} diff --git a/core/init.c b/core/init.c index aab0e9092..5c2bd7fdc 100644 --- a/core/init.c +++ b/core/init.c @@ -1374,6 +1374,9 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* Probe PAUs */ probe_pau(); + /* Probe all HWPROBE hardware we have code linked for*/ + probe_hardware(); + /* Initialize PCI */ pci_init_slots(); diff --git a/include/skiboot.h b/include/skiboot.h index 312a43654..d1553c4ef 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -1,5 +1,7 @@ // SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later -/* Copyright 2013-2019 IBM Corp. */ +/* Copyright 2013-2019 IBM Corp. + * Copyright 2021 Stewart Smith + */ #ifndef __SKIBOOT_H #define __SKIBOOT_H @@ -346,4 +348,39 @@ extern int fake_nvram_info(uint32_t *total_size); extern int fake_nvram_start_read(void *dst, uint32_t src, uint32_t len); extern int fake_nvram_write(uint32_t offset, void *src, uint32_t size); +/* + * A bunch of hardware needs to be probed, sometimes in a particular order. + * Very simple dependency graph, with a even simpler way to resolve it. + * But it means we can now at link time choose what hardware we support. + * This struct should not be defined directly but with the macros. + */ +struct hwprobe { + const char *name; + void (*probe)(void); + + bool probed; + + /* NULL or NULL-terminated array of strings */ + const char **deps; +}; + +#define DEFINE_HWPROBE(__name, __probe) \ +static const struct hwprobe __used __section(".hwprobes") hwprobe_##__name = { \ + .name = #__name, \ + .probe = __probe, \ + .deps = NULL, \ +} + +#define DEFINE_HWPROBE_DEPS(__name, __probe, ...) \ +static const struct hwprobe __used __section(".hwprobes") hwprobe_##__name = { \ + .name = #__name, \ + .probe = __probe, \ + .deps = (const char *[]){ __VA_ARGS__, NULL}, \ +} + +extern struct hwprobe __hwprobes_start; +extern struct hwprobe __hwprobes_end; + +extern void probe_hardware(void); + #endif /* __SKIBOOT_H */ diff --git a/skiboot.lds.S b/skiboot.lds.S index 11613842e..058848fa9 100644 --- a/skiboot.lds.S +++ b/skiboot.lds.S @@ -166,6 +166,12 @@ SECTIONS __platforms_end = .; } + .hwprobes : { + __hwprobes_start = .; + KEEP(*(.hwprobes)) + __hwprobes_end = .; + } + /* Relocations */ . = ALIGN(0x10); .dynamic : { From patchwork Mon Dec 20 12:22:45 2021 Content-Type: text/plain; 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[121.44.67.22]) by smtp.gmail.com with ESMTPSA id p17sm20661731pfh.86.2021.12.20.04.23.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Dec 2021 04:23:07 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 20 Dec 2021 22:22:45 +1000 Message-Id: <20211220122252.986542-3-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211220122252.986542-1-npiggin@gmail.com> References: <20211220122252.986542-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v5 2/9] hwprobe: convert PHB, NPU, PAU subsystems to hwprobe X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith Reviewed-by: Dan Horák [npiggin: split out from initial hwprobe pach] Signed-off-by: Stewart Smith --- core/init.c | 15 +-------------- hw/npu.c | 4 +++- hw/npu2-common.c | 4 +++- hw/pau.c | 3 ++- hw/phb3.c | 4 ++-- hw/phb4.c | 4 +++- include/skiboot.h | 5 ----- 7 files changed, 14 insertions(+), 25 deletions(-) diff --git a/core/init.c b/core/init.c index 5c2bd7fdc..c3e0c494d 100644 --- a/core/init.c +++ b/core/init.c @@ -1361,20 +1361,7 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* NX init */ nx_init(); - /* Probe PHB3 on P8 */ - probe_phb3(); - - /* Probe PHB4 on P9 and PHB5 on P10 */ - probe_phb4(); - - /* Probe NPUs */ - probe_npu(); - probe_npu2(); - - /* Probe PAUs */ - probe_pau(); - - /* Probe all HWPROBE hardware we have code linked for*/ + /* Probe all HWPROBE hardware we have code linked for */ probe_hardware(); /* Initialize PCI */ diff --git a/hw/npu.c b/hw/npu.c index dba7ee50f..35e6372d2 100644 --- a/hw/npu.c +++ b/hw/npu.c @@ -1679,7 +1679,7 @@ static void npu_create_phb(struct dt_node *dn) npu_hw_init(p); } -void probe_npu(void) +static void probe_npu(void) { struct dt_node *np; @@ -1691,3 +1691,5 @@ void probe_npu(void) dt_for_each_compatible(dt_root, np, "ibm,power8-npu-pciex") npu_create_phb(np); } + +DEFINE_HWPROBE_DEPS(npu, probe_npu, "phb3"); diff --git a/hw/npu2-common.c b/hw/npu2-common.c index b3f500f4b..02f102fe5 100644 --- a/hw/npu2-common.c +++ b/hw/npu2-common.c @@ -619,7 +619,7 @@ static void setup_devices(struct npu2 *npu) npu2_opencapi_init_npu(npu); } -void probe_npu2(void) +static void probe_npu2(void) { struct proc_chip *chip = next_chip(NULL); struct npu2 *npu; @@ -658,3 +658,5 @@ void probe_npu2(void) setup_devices(npu); } } + +DEFINE_HWPROBE_DEPS(npu2, probe_npu2, "phb4"); diff --git a/hw/pau.c b/hw/pau.c index a34d6dab1..1a3fbfaf7 100644 --- a/hw/pau.c +++ b/hw/pau.c @@ -2074,7 +2074,7 @@ static void pau_init(struct pau *pau) pau_opencapi_init(pau); } -void probe_pau(void) +static void probe_pau(void) { struct dt_node *dn; struct pau *pau; @@ -2093,3 +2093,4 @@ void probe_pau(void) pau_init(pau); } } +DEFINE_HWPROBE_DEPS(pau, probe_pau, "phb4"); diff --git a/hw/phb3.c b/hw/phb3.c index 09255a0a6..f46a43c9d 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -4993,7 +4993,7 @@ static void phb3_probe_pbcq(struct dt_node *pbcq) } -void probe_phb3(void) +static void probe_phb3(void) { struct dt_node *np; @@ -5006,4 +5006,4 @@ void probe_phb3(void) phb3_create(np); } - +DEFINE_HWPROBE(phb3, probe_phb3); diff --git a/hw/phb4.c b/hw/phb4.c index 4daad148a..f329e1309 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -6368,7 +6368,7 @@ static void phb4_probe_pbcq(struct dt_node *pbcq) } } -void probe_phb4(void) +static void probe_phb4(void) { struct dt_node *np; const char *s; @@ -6404,3 +6404,5 @@ void probe_phb4(void) phb4_create(np); } } + +DEFINE_HWPROBE(phb4, probe_phb4); diff --git a/include/skiboot.h b/include/skiboot.h index d1553c4ef..e2a1b5fc6 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -210,13 +210,8 @@ extern void copy_sreset_vector_fast_reboot(void); extern void patch_traps(bool enable); /* Various probe routines, to replace with an initcall system */ -extern void probe_phb3(void); -extern void probe_phb4(void); extern int preload_capp_ucode(void); extern void preload_io_vpd(void); -extern void probe_npu(void); -extern void probe_npu2(void); -extern void probe_pau(void); extern void uart_init(void); extern void mbox_init(void); extern void early_uart_init(void); From patchwork Mon Dec 20 12:22:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1571012 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[121.44.67.22]) by smtp.gmail.com with ESMTPSA id p17sm20661731pfh.86.2021.12.20.04.23.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Dec 2021 04:23:09 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 20 Dec 2021 22:22:46 +1000 Message-Id: <20211220122252.986542-4-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211220122252.986542-1-npiggin@gmail.com> References: <20211220122252.986542-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v5 3/9] Add CONFIG_P8 with PHB3 behind it X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith We can use a base CPU of POWER9 if we don't have P8. We can also hide PHB3 code behind this, and shave 12kb off skiboot.lid.xz Reviewed-by: Dan Horák [npiggin: add cpp define, fail gracefully on P8] Signed-off-by: Stewart Smith --- Makefile | 2 ++ Makefile.main | 15 ++++++++++++++- core/cpu.c | 11 +++++++++-- hw/Makefile.inc | 5 ++++- 4 files changed, 29 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index d236df9ec..625f212ea 100644 --- a/Makefile +++ b/Makefile @@ -59,6 +59,8 @@ ELF_ABI_v2 ?= $(LITTLE_ENDIAN) DEAD_CODE_ELIMINATION ?= 0 # Try to build without FSP code CONFIG_FSP?=1 +# Try to build without POWER8 support +CONFIG_P8?=1 # # Where is the source directory, must be a full path (no ~) diff --git a/Makefile.main b/Makefile.main index c8a63e8b1..2a346a6c9 100644 --- a/Makefile.main +++ b/Makefile.main @@ -96,7 +96,11 @@ CPPFLAGS += -DDEBUG -DCCAN_LIST_DEBUG endif CFLAGS := -fno-strict-aliasing -pie -fpie -fno-pic -m64 -fno-asynchronous-unwind-tables +ifeq ($(CONFIG_P8),1) CFLAGS += -mcpu=power8 +else +CFLAGS += -mcpu=power9 +endif CFLAGS += -Wl,--oformat,elf64-powerpc -ggdb # r13,r14,r15 are preserved for OS to use as fixed registers. # These could be saved and restored in and out of skiboot, but it's more @@ -156,6 +160,10 @@ else CFLAGS += -fno-stack-protector endif +# Add preprocessor defines for CONFIG_ options here +ifeq ($(CONFIG_P8),1) +CFLAGS += -DCONFIG_P8=1 +endif CFLAGS += $(call try-cflag,$(CC),-Wjump-misses-init) \ $(call try-cflag,$(CC),-Wsuggest-attribute=const) \ @@ -173,7 +181,12 @@ LDFLAGS := -m64 -static -nostdlib -pie LDFLAGS += -Wl,-pie LDFLAGS += -Wl,-Ttext-segment,$(LD_TEXT) -Wl,-N -Wl,--build-id=none LDFLAGS += -Wl,--no-multi-toc -LDFLAGS += -mcpu=power8 -Wl,--oformat,elf64-powerpc +ifeq ($(CONFIG_P8),1) +LDFLAGS += -mcpu=power8 +else +LDFLAGS += -mcpu=power9 +endif +LDFLAGS += -Wl,--oformat,elf64-powerpc LDFLAGS_FINAL = -m elf64lppc --no-multi-toc -N --build-id=none --whole-archive LDFLAGS_FINAL += -static -nostdlib -pie -Ttext-segment=$(LD_TEXT) --oformat=elf64-powerpc LDFLAGS_FINAL += --orphan-handling=warn diff --git a/core/cpu.c b/core/cpu.c index 6756ab164..f0be58059 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -1066,9 +1066,16 @@ void init_boot_cpu(void) cpu_thread_count = 1; } - if (proc_gen == proc_gen_p8 && (PVR_VERS_MAJ(mfspr(SPR_PVR)) == 1)) { - prerror("CPU: POWER8 DD1 is not supported\n"); + if (proc_gen == proc_gen_p8) { +#ifdef CONFIG_P8 + if (PVR_VERS_MAJ(mfspr(SPR_PVR)) == 1) { + prerror("CPU: POWER8 DD1 is not supported\n"); + abort(); + } +#else + prerror("CPU: POWER8 detected but CONFIG_P8 not set\n"); abort(); +#endif } if (is_power9n(pvr) && (PVR_VERS_MAJ(pvr) == 1)) { diff --git a/hw/Makefile.inc b/hw/Makefile.inc index 9fcbb63be..e273e898c 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -3,12 +3,15 @@ SUBDIRS += hw HW_OBJS = xscom.o chiptod.o lpc.o lpc-uart.o psi.o HW_OBJS += homer.o slw.o occ.o fsi-master.o centaur.o imc.o HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-compress.o nx-842.o nx-gzip.o -HW_OBJS += phb3.o sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o +HW_OBJS += sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o HW_OBJS += npu-opal.o ocmb.o xive2.o pau.o pau-hw-procedures.o +ifeq ($(CONFIG_P8),1) +HW_OBJS += phb3.o +endif HW=hw/built-in.a include $(SRC)/hw/fsp/Makefile.inc From patchwork Mon Dec 20 12:22:47 2021 Content-Type: text/plain; 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[121.44.67.22]) by smtp.gmail.com with ESMTPSA id p17sm20661731pfh.86.2021.12.20.04.23.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Dec 2021 04:23:12 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 20 Dec 2021 22:22:47 +1000 Message-Id: <20211220122252.986542-5-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211220122252.986542-1-npiggin@gmail.com> References: <20211220122252.986542-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v5 4/9] SBE: create processor-independent timer APIs X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Rather than have code call processor-specific SBE routines depending on version, hide those details in SBE APIs. Signed-off-by: Nicholas Piggin --- core/interrupts.c | 5 ++--- core/timer.c | 13 ++++--------- hw/Makefile.inc | 2 +- hw/sbe-p8.c | 9 ++------- hw/sbe-p9.c | 9 ++------- hw/sbe.c | 31 +++++++++++++++++++++++++++++++ include/sbe-p8.h | 5 ++--- include/sbe-p9.h | 3 --- include/sbe.h | 17 +++++++++++++++++ 9 files changed, 61 insertions(+), 33 deletions(-) create mode 100644 hw/sbe.c create mode 100644 include/sbe.h diff --git a/core/interrupts.c b/core/interrupts.c index c39c2801c..35571f289 100644 --- a/core/interrupts.c +++ b/core/interrupts.c @@ -16,8 +16,7 @@ #include #include #include -#include -#include +#include #include /* ICP registers */ @@ -491,7 +490,7 @@ static int64_t opal_handle_interrupt(uint32_t isn, __be64 *outstanding_event_mas is->ops->interrupt(is, isn); /* Check timers if SBE timer isn't working */ - if (!p8_sbe_timer_ok() && !p9_sbe_timer_ok()) + if (!sbe_timer_ok()) check_timers(true); /* Update output events */ diff --git a/core/timer.c b/core/timer.c index 43c388314..f803b7f28 100644 --- a/core/timer.c +++ b/core/timer.c @@ -15,8 +15,7 @@ #include #include #include -#include -#include +#include #ifdef __TEST__ #define this_cpu() ((void *)-1) @@ -36,10 +35,8 @@ static uint64_t timer_poll_gen; static inline void update_timer_expiry(uint64_t target) { - if (proc_gen < proc_gen_p9) - p8_sbe_update_timer_expiry(target); - else - p9_sbe_update_timer_expiry(target); + if (sbe_timer_ok()) + sbe_update_timer_expiry(target); } void init_timer(struct timer *t, timer_func_t expiry, void *data) @@ -287,9 +284,7 @@ void late_init_timers(void) */ if (platform.heartbeat_time) { heartbeat = platform.heartbeat_time(); - } else if (p9_sbe_timer_ok()) { - heartbeat = HEARTBEAT_DEFAULT_MS * 10; - } else if (p8_sbe_timer_ok()) { + } else if (sbe_timer_ok()) { heartbeat = HEARTBEAT_DEFAULT_MS * 10; } diff --git a/hw/Makefile.inc b/hw/Makefile.inc index e273e898c..a6732b7bc 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -1,6 +1,6 @@ # -*-Makefile-*- SUBDIRS += hw -HW_OBJS = xscom.o chiptod.o lpc.o lpc-uart.o psi.o +HW_OBJS = xscom.o chiptod.o lpc.o lpc-uart.o psi.o sbe.o HW_OBJS += homer.o slw.o occ.o fsi-master.o centaur.o imc.o HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-compress.o nx-842.o nx-gzip.o HW_OBJS += sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o diff --git a/hw/sbe-p8.c b/hw/sbe-p8.c index 73fa5f1f2..70edec65e 100644 --- a/hw/sbe-p8.c +++ b/hw/sbe-p8.c @@ -6,13 +6,13 @@ */ #include +#include #include #include #include #include /* SLW timer related stuff */ -static bool sbe_has_timer; static uint64_t sbe_timer_inc; static uint64_t sbe_timer_target; static uint32_t sbe_timer_chip; @@ -65,7 +65,7 @@ void p8_sbe_update_timer_expiry(uint64_t new_target) uint64_t count, gen, gen2, req, now; int64_t rc; - if (!sbe_has_timer || new_target == sbe_timer_target) + if (new_target == sbe_timer_target) return; sbe_timer_target = new_target; @@ -162,11 +162,6 @@ void p8_sbe_update_timer_expiry(uint64_t new_target) prlog(PR_TRACE, "SLW: gen: %llx\n", gen); } -bool p8_sbe_timer_ok(void) -{ - return sbe_has_timer; -} - void p8_sbe_init_timer(void) { struct dt_node *np; diff --git a/hw/sbe-p9.c b/hw/sbe-p9.c index 898a1fb56..3b0f8b06e 100644 --- a/hw/sbe-p9.c +++ b/hw/sbe-p9.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include #include @@ -73,7 +74,6 @@ struct p9_sbe { static int sbe_default_chip_id = -1; /* Is SBE timer running? */ -static bool sbe_has_timer = false; static bool sbe_timer_in_progress = false; static bool has_new_target = false; @@ -843,7 +843,7 @@ static void p9_sbe_timer_schedule(void) */ void p9_sbe_update_timer_expiry(uint64_t new_target) { - if (!sbe_has_timer || new_target == sbe_timer_target) + if (new_target == sbe_timer_target) return; lock(&sbe_timer_lock); @@ -874,11 +874,6 @@ static void p9_sbe_timer_init(void) prlog(PR_INFO, "Timer facility on chip %x\n", sbe_default_chip_id); } -bool p9_sbe_timer_ok(void) -{ - return sbe_has_timer; -} - static void p9_sbe_stash_chipop_resp(struct p9_sbe_msg *msg) { int rc = p9_sbe_get_primary_rc(msg->resp); diff --git a/hw/sbe.c b/hw/sbe.c new file mode 100644 index 000000000..991485e5b --- /dev/null +++ b/hw/sbe.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + +/* + * SBE communication driver (common code) + */ + +#define pr_fmt(fmt) "SBE: " fmt + +#include +#include +#include +#include +#include + +bool sbe_has_timer = false; + +void sbe_update_timer_expiry(uint64_t target) +{ + assert(sbe_timer_ok); + + if (proc_gen == proc_gen_p9 || proc_gen == proc_gen_p10) + p9_sbe_update_timer_expiry(target); + + if (proc_gen == proc_gen_p8) + p8_sbe_update_timer_expiry(target); +} + +bool sbe_timer_ok(void) +{ + return sbe_has_timer; +} diff --git a/include/sbe-p8.h b/include/sbe-p8.h index 66f702514..d6f0d3179 100644 --- a/include/sbe-p8.h +++ b/include/sbe-p8.h @@ -4,12 +4,11 @@ #ifndef __SBE_P8_H #define __SBE_P8_H +#include + /* P8 SBE update timer function */ extern void p8_sbe_update_timer_expiry(uint64_t new_target); -/* Is SBE timer available ? */ -extern bool p8_sbe_timer_ok(void); - /* Initialize SBE timer */ extern void p8_sbe_init_timer(void); diff --git a/include/sbe-p9.h b/include/sbe-p9.h index 289c28ba5..5f236f02f 100644 --- a/include/sbe-p9.h +++ b/include/sbe-p9.h @@ -228,9 +228,6 @@ extern void p9_sbe_init(void); /* SBE interrupt */ extern void p9_sbe_interrupt(uint32_t chip_id); -/* Is SBE timer available ? */ -extern bool p9_sbe_timer_ok(void); - /* Update SBE timer expiry */ extern void p9_sbe_update_timer_expiry(uint64_t new_target); diff --git a/include/sbe.h b/include/sbe.h new file mode 100644 index 000000000..24d21fa0b --- /dev/null +++ b/include/sbe.h @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2017-2019 IBM Corp. */ + +#ifndef __SBE_H +#define __SBE_H + +#include + +/* SBE update timer function */ +extern void sbe_update_timer_expiry(uint64_t target); + +/* Is SBE timer available ? */ +extern bool sbe_timer_ok(void); + +extern bool sbe_has_timer; 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[121.44.67.22]) by smtp.gmail.com with ESMTPSA id p17sm20661731pfh.86.2021.12.20.04.23.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Dec 2021 04:23:14 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 20 Dec 2021 22:22:48 +1000 Message-Id: <20211220122252.986542-6-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211220122252.986542-1-npiggin@gmail.com> References: <20211220122252.986542-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v5 5/9] hw/slw: Move P8 bits behind CONFIG_P8 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This saves about 10kB from skiboot.lid.xz Reviewed-by: Dan Horák Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 2 + hw/Makefile.inc | 4 +- hw/sbe.c | 2 + hw/slw.c | 176 ++++++++++++++++++++++--------------------- libpore/Makefile.inc | 8 +- 5 files changed, 104 insertions(+), 88 deletions(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 9f92525a9..2696348af 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -272,6 +272,7 @@ static void cleanup_cpu_state(void) /* XXX Update the SLW copies ! Also dbl check HIDs etc... */ init_shared_sprs(); +#ifdef CONFIG_P8 if (proc_gen == proc_gen_p8) { /* If somebody was in fast_sleep, we may have a * workaround to undo @@ -287,6 +288,7 @@ static void cleanup_cpu_state(void) */ cleanup_local_tlb(); } +#endif /* And we might have lost TB sync */ chiptod_wakeup_resync(); diff --git a/hw/Makefile.inc b/hw/Makefile.inc index a6732b7bc..8f509739d 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -7,10 +7,10 @@ HW_OBJS += sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o -HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o +HW_OBJS += occ-sensor.o vas.o dio-p9.o lpc-port80h.o cache-p9.o HW_OBJS += npu-opal.o ocmb.o xive2.o pau.o pau-hw-procedures.o ifeq ($(CONFIG_P8),1) -HW_OBJS += phb3.o +HW_OBJS += phb3.o sbe-p8.o endif HW=hw/built-in.a diff --git a/hw/sbe.c b/hw/sbe.c index 991485e5b..859581662 100644 --- a/hw/sbe.c +++ b/hw/sbe.c @@ -21,8 +21,10 @@ void sbe_update_timer_expiry(uint64_t target) if (proc_gen == proc_gen_p9 || proc_gen == proc_gen_p10) p9_sbe_update_timer_expiry(target); +#ifdef CONFIG_P8 if (proc_gen == proc_gen_p8) p8_sbe_update_timer_expiry(target); +#endif } bool sbe_timer_ok(void) diff --git a/hw/slw.c b/hw/slw.c index eb67998d1..bc53960b7 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -32,19 +32,20 @@ enum wakeup_engine_states wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; bool has_deep_states = false; -DEFINE_LOG_ENTRY(OPAL_RC_SLW_INIT, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, - OPAL_PLATFORM_FIRMWARE, OPAL_PREDICTIVE_ERR_GENERAL, - OPAL_NA); - DEFINE_LOG_ENTRY(OPAL_RC_SLW_SET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_INFO, OPAL_NA); -DEFINE_LOG_ENTRY(OPAL_RC_SLW_GET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, +DEFINE_LOG_ENTRY(OPAL_RC_SLW_REG, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_INFO, OPAL_NA); -DEFINE_LOG_ENTRY(OPAL_RC_SLW_REG, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, +#ifdef CONFIG_P8 +DEFINE_LOG_ENTRY(OPAL_RC_SLW_INIT, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, + OPAL_PLATFORM_FIRMWARE, OPAL_PREDICTIVE_ERR_GENERAL, + OPAL_NA); + +DEFINE_LOG_ENTRY(OPAL_RC_SLW_GET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_INFO, OPAL_NA); @@ -98,59 +99,6 @@ static bool slw_set_overrides(struct proc_chip *chip, struct cpu_thread *c) return true; } -static bool slw_set_overrides_p10(struct proc_chip *chip, struct cpu_thread *c) -{ - uint64_t tmp; - int rc; - uint32_t core = pir_to_core_id(c->pir); - - /* Special wakeup bits that could hold power mgt */ - rc = xscom_read(chip->id, - XSCOM_ADDR_P10_QME_CORE(core, P10_QME_SPWU_HYP), - &tmp); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_SET), - "SLW: Failed to read P10_QME_SPWU_HYP\n"); - return false; - } - if (tmp & P10_SPWU_REQ) - prlog(PR_WARNING, - "SLW: core %d P10_QME_SPWU_HYP requested 0x%016llx\n", - core, tmp); - - return true; -} - - -static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c) -{ - uint64_t tmp; - int rc; - uint32_t core = pir_to_core_id(c->pir); - - /* Special wakeup bits that could hold power mgt */ - rc = xscom_read(chip->id, - XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP), - &tmp); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_SET), - "SLW: Failed to read EC_PPM_SPECIAL_WKUP_HYP\n"); - return false; - } - if (tmp) - prlog(PR_WARNING, - "SLW: core %d EC_PPM_SPECIAL_WKUP_HYP read 0x%016llx\n", - core, tmp); - rc = xscom_read(chip->id, - XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_OTR), - &tmp); - if (tmp) - prlog(PR_WARNING, - "SLW: core %d EC_PPM_SPECIAL_WKUP_OTR read 0x%016llx\n", - core, tmp); - return true; -} - static bool slw_set_idle_mode(struct proc_chip *chip, struct cpu_thread *c) { uint32_t core = pir_to_core_id(c->pir); @@ -242,6 +190,60 @@ static bool idle_prepare_core(struct proc_chip *chip, struct cpu_thread *c) return true; } +#endif + +static bool slw_set_overrides_p10(struct proc_chip *chip, struct cpu_thread *c) +{ + uint64_t tmp; + int rc; + uint32_t core = pir_to_core_id(c->pir); + + /* Special wakeup bits that could hold power mgt */ + rc = xscom_read(chip->id, + XSCOM_ADDR_P10_QME_CORE(core, P10_QME_SPWU_HYP), + &tmp); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_SET), + "SLW: Failed to read P10_QME_SPWU_HYP\n"); + return false; + } + if (tmp & P10_SPWU_REQ) + prlog(PR_WARNING, + "SLW: core %d P10_QME_SPWU_HYP requested 0x%016llx\n", + core, tmp); + + return true; +} + + +static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c) +{ + uint64_t tmp; + int rc; + uint32_t core = pir_to_core_id(c->pir); + + /* Special wakeup bits that could hold power mgt */ + rc = xscom_read(chip->id, + XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP), + &tmp); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_SET), + "SLW: Failed to read EC_PPM_SPECIAL_WKUP_HYP\n"); + return false; + } + if (tmp) + prlog(PR_WARNING, + "SLW: core %d EC_PPM_SPECIAL_WKUP_HYP read 0x%016llx\n", + core, tmp); + rc = xscom_read(chip->id, + XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_OTR), + &tmp); + if (tmp) + prlog(PR_WARNING, + "SLW: core %d EC_PPM_SPECIAL_WKUP_OTR read 0x%016llx\n", + core, tmp); + return true; +} /* Define device-tree fields */ #define MAX_NAME_LEN 16 @@ -1069,31 +1071,6 @@ void add_cpu_idle_state_properties(void) free(pm_ctrl_reg_mask_buf); } -static void slw_patch_regs(struct proc_chip *chip) -{ - struct cpu_thread *c; - void *image = (void *)chip->slw_base; - int rc; - - for_each_available_cpu(c) { - if (c->chip_id != chip->id) - continue; - - /* Clear HRMOR */ - rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, - P8_SPR_HRMOR, 0, - cpu_get_core_index(c), - cpu_get_thread_index(c)); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: Failed to set HRMOR for CPU %x\n", - c->pir); - } - - /* XXX Add HIDs etc... */ - } -} - static void slw_init_chip_p9(struct proc_chip *chip) { struct cpu_thread *c; @@ -1135,6 +1112,32 @@ static bool slw_image_check_p9(struct proc_chip *chip) } +#ifdef CONFIG_P8 +static void slw_patch_regs(struct proc_chip *chip) +{ + struct cpu_thread *c; + void *image = (void *)chip->slw_base; + int rc; + + for_each_available_cpu(c) { + if (c->chip_id != chip->id) + continue; + + /* Clear HRMOR */ + rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, + P8_SPR_HRMOR, 0, + cpu_get_core_index(c), + cpu_get_thread_index(c)); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: Failed to set HRMOR for CPU %x\n", + c->pir); + } + + /* XXX Add HIDs etc... */ + } +} + static bool slw_image_check_p8(struct proc_chip *chip) { int64_t rc; @@ -1284,6 +1287,7 @@ static int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t enter) } opal_call(OPAL_CONFIG_CPU_IDLE_STATE, opal_config_cpu_idle_state, 2); +#endif int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) { @@ -1324,6 +1328,7 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) sprn, val, cpu_pir); } +#ifdef CONFIG_P8 } else if (proc_gen == proc_gen_p8) { int spr_is_supported = 0; void *image; @@ -1347,6 +1352,7 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) sprn, val, cpu_get_core_index(c), cpu_get_thread_index(c)); +#endif } else { log_simple_error(&e_info(OPAL_RC_SLW_REG), "SLW: proc_gen not supported\n"); @@ -1381,6 +1387,7 @@ void slw_init(void) } if (proc_gen == proc_gen_p8) { +#ifdef CONFIG_P8 for_each_chip(chip) { slw_init_chip_p8(chip); if(slw_image_check_p8(chip)) @@ -1389,6 +1396,7 @@ void slw_init(void) slw_late_init_p8(chip); } p8_sbe_init_timer(); +#endif } else if (proc_gen == proc_gen_p9) { for_each_chip(chip) { slw_init_chip_p9(chip); diff --git a/libpore/Makefile.inc b/libpore/Makefile.inc index 06d9c8902..76c30d426 100644 --- a/libpore/Makefile.inc +++ b/libpore/Makefile.inc @@ -1,5 +1,9 @@ -LIBPORE_SRCS = p8_pore_table_gen_api_fixed.C p9_stop_api.C p9_stop_util.C p10_stop_api.C p10_stop_util.C -LIBPORE_SRCS += p8_pore_table_static_data.c sbe_xip_image.c pore_inline_assembler.c +LIBPORE_SRCS = p9_stop_api.C p9_stop_util.C p10_stop_api.C p10_stop_util.C +ifeq ($(CONFIG_P8),1) +LIBPORE_SRCS += sbe_xip_image.c pore_inline_assembler.c +LIBPORE_SRCS += p8_pore_table_gen_api_fixed.C p8_pore_table_static_data.c +endif + LIBPORE_OBJS_1 = $(LIBPORE_SRCS:%.c=%.o) LIBPORE_OBJS = $(LIBPORE_OBJS_1:%.C=%.o) SUBDIRS += libpore From patchwork Mon Dec 20 12:22:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1571015 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[121.44.67.22]) by smtp.gmail.com with ESMTPSA id p17sm20661731pfh.86.2021.12.20.04.23.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Dec 2021 04:23:17 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 20 Dec 2021 22:22:49 +1000 Message-Id: <20211220122252.986542-7-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211220122252.986542-1-npiggin@gmail.com> References: <20211220122252.986542-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v5 6/9] hw/slw: split P8 specific code into its own file X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" POWER8 support is large and significantly different than P9/10 code. This change prepares to make P8 support configurable. Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 1 + core/init.c | 1 + hw/Makefile.inc | 2 +- hw/imc.c | 1 + hw/nx.c | 1 + hw/slw-p8.c | 508 +++++++++++++++++++++++++++++++++++++++++++++ hw/slw.c | 491 +------------------------------------------ hw/xive.c | 1 + hw/xive2.c | 1 + include/skiboot.h | 12 -- include/slw.h | 48 +++++ 11 files changed, 574 insertions(+), 493 deletions(-) create mode 100644 hw/slw-p8.c create mode 100644 include/slw.h diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 2696348af..fedfa88cc 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/core/init.c b/core/init.c index c3e0c494d..deead5ecc 100644 --- a/core/init.c +++ b/core/init.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/hw/Makefile.inc b/hw/Makefile.inc index 8f509739d..7327cec35 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -10,7 +10,7 @@ HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o HW_OBJS += occ-sensor.o vas.o dio-p9.o lpc-port80h.o cache-p9.o HW_OBJS += npu-opal.o ocmb.o xive2.o pau.o pau-hw-procedures.o ifeq ($(CONFIG_P8),1) -HW_OBJS += phb3.o sbe-p8.o +HW_OBJS += phb3.o sbe-p8.o slw-p8.o endif HW=hw/built-in.a diff --git a/hw/imc.c b/hw/imc.c index cbd68edc4..97e0809f0 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -8,6 +8,7 @@ #define pr_fmt(fmt) "IMC: " fmt #include +#include #include #include #include diff --git a/hw/nx.c b/hw/nx.c index fdadf53c7..13c681b2c 100644 --- a/hw/nx.c +++ b/hw/nx.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/hw/slw-p8.c b/hw/slw-p8.c new file mode 100644 index 000000000..0a27a8fcc --- /dev/null +++ b/hw/slw-p8.c @@ -0,0 +1,508 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* + * It would be nice to be able to define non-static log entry types and share + * these with slw.c + */ +DEFINE_LOG_ENTRY(OPAL_RC_SLW_INIT, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, + OPAL_PLATFORM_FIRMWARE, OPAL_PREDICTIVE_ERR_GENERAL, + OPAL_NA); + +DEFINE_LOG_ENTRY(OPAL_RC_SLW_SET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, + OPAL_PLATFORM_FIRMWARE, OPAL_INFO, + OPAL_NA); + +DEFINE_LOG_ENTRY(OPAL_RC_SLW_GET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, + OPAL_PLATFORM_FIRMWARE, OPAL_INFO, + OPAL_NA); + +DEFINE_LOG_ENTRY(OPAL_RC_SLW_REG, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, + OPAL_PLATFORM_FIRMWARE, OPAL_INFO, + OPAL_NA); + +static bool slw_general_init(struct proc_chip *chip, struct cpu_thread *c) +{ + uint32_t core = pir_to_core_id(c->pir); + uint64_t tmp; + int rc; + + /* PowerManagement GP0 clear PM_DISABLE */ + rc = xscom_read(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_GP0), &tmp); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_INIT), + "SLW: Failed to read PM_GP0\n"); + return false; + } + tmp = tmp & ~0x8000000000000000ULL; + rc = xscom_write(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_GP0), tmp); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_INIT), + "SLW: Failed to write PM_GP0\n"); + return false; + } + prlog(PR_TRACE, "SLW: PMGP0 set to 0x%016llx\n", tmp); + + /* Read back for debug */ + rc = xscom_read(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_GP0), &tmp); + if (rc) + log_simple_error(&e_info(OPAL_RC_SLW_INIT), + "SLW: Failed to re-read PM_GP0. Continuing...\n"); + + prlog(PR_TRACE, "SLW: PMGP0 read 0x%016llx\n", tmp); + + return true; +} + +static bool slw_set_overrides(struct proc_chip *chip, struct cpu_thread *c) +{ + uint32_t core = pir_to_core_id(c->pir); + int rc; + + rc = xscom_write(chip->id, + XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_SPECIAL_WAKEUP_PHYP), + 0); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_SET), + "SLW: Failed to write PM_SPECIAL_WAKEUP_PHYP\n"); + return false; + } + + return true; +} + +static bool slw_set_idle_mode(struct proc_chip *chip, struct cpu_thread *c) +{ + uint32_t core = pir_to_core_id(c->pir); + uint64_t tmp; + int rc; + + /* + * PM GP1 allows fast/deep mode to be selected independently for sleep + * and winkle. Init PM GP1 so that sleep happens in fast mode and + * winkle happens in deep mode. + * Make use of the OR XSCOM for this since the OCC might be manipulating + * the PM_GP1 register as well. Before doing this ensure that the bits + * managing idle states are cleared so as to override any bits set at + * init time. + */ + + tmp = ~EX_PM_GP1_SLEEP_WINKLE_MASK; + rc = xscom_write(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_CLEAR_GP1), + tmp); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_SET), + "SLW: Failed to write PM_GP1\n"); + return false; + } + + rc = xscom_write(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_SET_GP1), + EX_PM_SETUP_GP1_FAST_SLEEP_DEEP_WINKLE); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_SET), + "SLW: Failed to write PM_GP1\n"); + return false; + } + + /* Read back for debug */ + xscom_read(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_GP1), &tmp); + prlog(PR_TRACE, "SLW: PMGP1 read 0x%016llx\n", tmp); + return true; +} + +static bool slw_get_idle_state_history(struct proc_chip *chip, struct cpu_thread *c) +{ + uint32_t core = pir_to_core_id(c->pir); + uint64_t tmp; + int rc; + + /* Cleanup history */ + rc = xscom_read(chip->id, + XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_IDLE_STATE_HISTORY_PHYP), + &tmp); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_GET), + "SLW: Failed to read PM_IDLE_STATE_HISTORY\n"); + return false; + } + + prlog(PR_TRACE, "SLW: core %x:%x history: 0x%016llx (old1)\n", + chip->id, core, tmp); + + rc = xscom_read(chip->id, + XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_IDLE_STATE_HISTORY_PHYP), + &tmp); + + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_GET), + "SLW: Failed to read PM_IDLE_STATE_HISTORY\n"); + return false; + } + + prlog(PR_TRACE, "SLW: core %x:%x history: 0x%016llx (old2)\n", + chip->id, core, tmp); + + return true; +} + +static bool idle_prepare_core(struct proc_chip *chip, struct cpu_thread *c) +{ + prlog(PR_TRACE, "FASTSLEEP: Prepare core %x:%x\n", + chip->id, pir_to_core_id(c->pir)); + + if(!slw_general_init(chip, c)) + return false; + if(!slw_set_overrides(chip, c)) + return false; + if(!slw_set_idle_mode(chip, c)) + return false; + if(!slw_get_idle_state_history(chip, c)) + return false; + + return true; + +} + +static struct cpu_idle_states nap_only_cpu_idle_states[] = { + { /* nap */ + .name = "nap", + .latency_ns = 4000, + .residency_ns = 100000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_NAP_ENABLED \ + | 0*OPAL_PM_SLEEP_ENABLED \ + | 0*OPAL_PM_WINKLE_ENABLED \ + | 0*OPAL_USE_PMICR, + .pm_ctrl_reg_val = 0, + .pm_ctrl_reg_mask = 0 }, +}; + +static struct cpu_idle_states power8_cpu_idle_states[] = { + { /* nap */ + .name = "nap", + .latency_ns = 4000, + .residency_ns = 100000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_NAP_ENABLED \ + | 0*OPAL_USE_PMICR, + .pm_ctrl_reg_val = 0, + .pm_ctrl_reg_mask = 0 }, + { /* fast sleep (with workaround) */ + .name = "fastsleep_", + .latency_ns = 40000, + .residency_ns = 300000000, + .flags = 1*OPAL_PM_DEC_STOP \ + | 1*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_SLEEP_ENABLED_ER1 \ + | 0*OPAL_USE_PMICR, /* Not enabled until deep + states are available */ + .pm_ctrl_reg_val = OPAL_PM_FASTSLEEP_PMICR, + .pm_ctrl_reg_mask = OPAL_PM_SLEEP_PMICR_MASK }, + { /* Winkle */ + .name = "winkle", + .latency_ns = 10000000, + .residency_ns = 1000000000, /* Educated guess (not measured). + * Winkle is not currently used by + * linux cpuidle subsystem so we + * don't have real world user. + * However, this should be roughly + * accurate for when linux does + * use it. */ + .flags = 1*OPAL_PM_DEC_STOP \ + | 1*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 1*OPAL_PM_LOSE_HYP_CONTEXT \ + | 1*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_WINKLE_ENABLED \ + | 0*OPAL_USE_PMICR, /* Currently choosing deep vs + fast via EX_PM_GP1 reg */ + .pm_ctrl_reg_val = 0, + .pm_ctrl_reg_mask = 0 }, +}; + +void find_cpu_idle_state_properties_p8(struct cpu_idle_states **states, + int *nr_states, bool *can_sleep) +{ + struct proc_chip *chip; + + chip = next_chip(NULL); + assert(chip); + + *can_sleep = true; + + if (chip->type == PROC_CHIP_P8_MURANO || + chip->type == PROC_CHIP_P8_VENICE || + chip->type == PROC_CHIP_P8_NAPLES) { + const struct dt_property *p; + + p = dt_find_property(dt_root, "ibm,enabled-idle-states"); + if (p) + prlog(PR_NOTICE, + "SLW: HB-provided idle states property found\n"); + *states = power8_cpu_idle_states; + *nr_states = ARRAY_SIZE(power8_cpu_idle_states); + + /* Check if hostboot say we can sleep */ + if (!p || !dt_prop_find_string(p, "fast-sleep")) { + prlog(PR_WARNING, "SLW: Sleep not enabled by HB" + " on this platform\n"); + *can_sleep = false; + } + + /* Clip to NAP only on Murano and Venice DD1.x */ + if ((chip->type == PROC_CHIP_P8_MURANO || + chip->type == PROC_CHIP_P8_VENICE) && + chip->ec_level < 0x20) { + prlog(PR_NOTICE, "SLW: Sleep not enabled on P8 DD1.x\n"); + *can_sleep = false; + } + + } else { + *states = nap_only_cpu_idle_states; + *nr_states = ARRAY_SIZE(nap_only_cpu_idle_states); + } +} + +static void slw_patch_regs(struct proc_chip *chip) +{ + struct cpu_thread *c; + void *image = (void *)chip->slw_base; + int rc; + + for_each_available_cpu(c) { + if (c->chip_id != chip->id) + continue; + + /* Clear HRMOR */ + rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, + P8_SPR_HRMOR, 0, + cpu_get_core_index(c), + cpu_get_thread_index(c)); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: Failed to set HRMOR for CPU %x\n", + c->pir); + } + + /* XXX Add HIDs etc... */ + } +} + +static bool slw_image_check_p8(struct proc_chip *chip) +{ + int64_t rc; + + prlog(PR_DEBUG, "SLW: slw_check chip 0x%x\n", chip->id); + if (!chip->slw_base) { + prerror("SLW: No image found !\n"); + return false; + } + + /* Check actual image size */ + rc = sbe_xip_get_scalar((void *)chip->slw_base, "image_size", + &chip->slw_image_size); + if (rc != 0) { + log_simple_error(&e_info(OPAL_RC_SLW_INIT), + "SLW: Error %lld reading SLW image size\n", rc); + /* XXX Panic ? */ + chip->slw_base = 0; + chip->slw_bar_size = 0; + chip->slw_image_size = 0; + return false; + } + prlog(PR_DEBUG, "SLW: Image size from image: 0x%llx\n", + chip->slw_image_size); + + if (chip->slw_image_size > chip->slw_bar_size) { + log_simple_error(&e_info(OPAL_RC_SLW_INIT), + "SLW: Built-in image size larger than BAR size !\n"); + /* XXX Panic ? */ + return false; + } + return true; + +} + +static void slw_late_init_p8(struct proc_chip *chip) +{ + + prlog(PR_DEBUG, "SLW: late Init chip 0x%x\n", chip->id); + + /* Patch SLW image */ + slw_patch_regs(chip); + +} +static void slw_init_chip_p8(struct proc_chip *chip) +{ + struct cpu_thread *c; + + prlog(PR_DEBUG, "SLW: Init chip 0x%x\n", chip->id); + /* At power ON setup inits for fast-sleep */ + for_each_available_core_in_chip(c, chip->id) { + idle_prepare_core(chip, c); + } +} + +/* Workarounds while entering fast-sleep */ + +static void fast_sleep_enter(void) +{ + uint32_t core = pir_to_core_id(this_cpu()->pir); + uint32_t chip_id = this_cpu()->chip_id; + struct cpu_thread *primary_thread; + uint64_t tmp; + int rc; + + primary_thread = this_cpu()->primary; + + rc = xscom_read(chip_id, XSCOM_ADDR_P8_EX(core, L2_FIR_ACTION1), + &tmp); + if (rc) { + prlog(PR_WARNING, "fast_sleep_enter XSCOM failed(1):" + " rc=%d chip_id=%d core=%d\n", + rc, chip_id, core); + return; + } + + primary_thread->save_l2_fir_action1 = tmp; + primary_thread->in_fast_sleep = true; + + tmp = tmp & ~0x0200000000000000ULL; + rc = xscom_write(chip_id, XSCOM_ADDR_P8_EX(core, L2_FIR_ACTION1), + tmp); + if (rc) { + prlog(PR_WARNING, "fast_sleep_enter XSCOM failed(2):" + " rc=%d chip_id=%d core=%d\n", + rc, chip_id, core); + return; + } + rc = xscom_read(chip_id, XSCOM_ADDR_P8_EX(core, L2_FIR_ACTION1), + &tmp); + if (rc) { + prlog(PR_WARNING, "fast_sleep_enter XSCOM failed(3):" + " rc=%d chip_id=%d core=%d\n", + rc, chip_id, core); + return; + } + +} + +/* Workarounds while exiting fast-sleep */ + +void fast_sleep_exit(void) +{ + uint32_t core = pir_to_core_id(this_cpu()->pir); + uint32_t chip_id = this_cpu()->chip_id; + struct cpu_thread *primary_thread; + int rc; + + primary_thread = this_cpu()->primary; + primary_thread->in_fast_sleep = false; + + rc = xscom_write(chip_id, XSCOM_ADDR_P8_EX(core, L2_FIR_ACTION1), + primary_thread->save_l2_fir_action1); + if (rc) { + prlog(PR_WARNING, "fast_sleep_exit XSCOM failed:" + " rc=%d chip_id=%d core=%d\n", + rc, chip_id, core); + return; + } +} + +/* + * Setup and cleanup method for fast-sleep workarounds + * state = 1 fast-sleep + * enter = 1 Enter state + * exit = 0 Exit state + */ + +static int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t enter) +{ + /* Only fast-sleep for now */ + if (state != 1) + return OPAL_PARAMETER; + + switch(enter) { + case 1: + fast_sleep_enter(); + break; + case 0: + fast_sleep_exit(); + break; + default: + return OPAL_PARAMETER; + } + + return OPAL_SUCCESS; +} + +opal_call(OPAL_CONFIG_CPU_IDLE_STATE, opal_config_cpu_idle_state, 2); + +int64_t opal_slw_set_reg_p8(struct cpu_thread *c, struct proc_chip *chip, + uint64_t sprn, uint64_t val) +{ + int spr_is_supported = 0; + void *image; + int i; + int rc; + + /* Check of the SPR is supported by libpore */ + for (i = 0; i < SLW_SPR_REGS_SIZE ; i++) { + if (sprn == SLW_SPR_REGS[i].value) { + spr_is_supported = 1; + break; + } + } + if (!spr_is_supported) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: Trying to set unsupported spr for CPU %x\n", + c->pir); + return OPAL_UNSUPPORTED; + } + image = (void *)chip->slw_base; + rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, + sprn, val, + cpu_get_core_index(c), + cpu_get_thread_index(c)); + return rc; +} + +void slw_p8_init(void) +{ + struct proc_chip *chip; + + for_each_chip(chip) { + slw_init_chip_p8(chip); + if (slw_image_check_p8(chip)) + wakeup_engine_state = WAKEUP_ENGINE_PRESENT; + if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) + slw_late_init_p8(chip); + } + p8_sbe_init_timer(); +} diff --git a/hw/slw.c b/hw/slw.c index bc53960b7..6d7c8619c 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -7,8 +7,8 @@ */ #include +#include #include -#include #include #include #include @@ -22,12 +22,10 @@ #include #include #include -#include #include #include -#include -#include +//#include enum wakeup_engine_states wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; bool has_deep_states = false; @@ -40,158 +38,6 @@ DEFINE_LOG_ENTRY(OPAL_RC_SLW_REG, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_INFO, OPAL_NA); -#ifdef CONFIG_P8 -DEFINE_LOG_ENTRY(OPAL_RC_SLW_INIT, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, - OPAL_PLATFORM_FIRMWARE, OPAL_PREDICTIVE_ERR_GENERAL, - OPAL_NA); - -DEFINE_LOG_ENTRY(OPAL_RC_SLW_GET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, - OPAL_PLATFORM_FIRMWARE, OPAL_INFO, - OPAL_NA); - -static bool slw_general_init(struct proc_chip *chip, struct cpu_thread *c) -{ - uint32_t core = pir_to_core_id(c->pir); - uint64_t tmp; - int rc; - - /* PowerManagement GP0 clear PM_DISABLE */ - rc = xscom_read(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_GP0), &tmp); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_INIT), - "SLW: Failed to read PM_GP0\n"); - return false; - } - tmp = tmp & ~0x8000000000000000ULL; - rc = xscom_write(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_GP0), tmp); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_INIT), - "SLW: Failed to write PM_GP0\n"); - return false; - } - prlog(PR_TRACE, "SLW: PMGP0 set to 0x%016llx\n", tmp); - - /* Read back for debug */ - rc = xscom_read(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_GP0), &tmp); - if (rc) - log_simple_error(&e_info(OPAL_RC_SLW_INIT), - "SLW: Failed to re-read PM_GP0. Continuing...\n"); - - prlog(PR_TRACE, "SLW: PMGP0 read 0x%016llx\n", tmp); - - return true; -} - -static bool slw_set_overrides(struct proc_chip *chip, struct cpu_thread *c) -{ - uint32_t core = pir_to_core_id(c->pir); - int rc; - - rc = xscom_write(chip->id, - XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_SPECIAL_WAKEUP_PHYP), - 0); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_SET), - "SLW: Failed to write PM_SPECIAL_WAKEUP_PHYP\n"); - return false; - } - - return true; -} - -static bool slw_set_idle_mode(struct proc_chip *chip, struct cpu_thread *c) -{ - uint32_t core = pir_to_core_id(c->pir); - uint64_t tmp; - int rc; - - /* - * PM GP1 allows fast/deep mode to be selected independently for sleep - * and winkle. Init PM GP1 so that sleep happens in fast mode and - * winkle happens in deep mode. - * Make use of the OR XSCOM for this since the OCC might be manipulating - * the PM_GP1 register as well. Before doing this ensure that the bits - * managing idle states are cleared so as to override any bits set at - * init time. - */ - - tmp = ~EX_PM_GP1_SLEEP_WINKLE_MASK; - rc = xscom_write(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_CLEAR_GP1), - tmp); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_SET), - "SLW: Failed to write PM_GP1\n"); - return false; - } - - rc = xscom_write(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_SET_GP1), - EX_PM_SETUP_GP1_FAST_SLEEP_DEEP_WINKLE); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_SET), - "SLW: Failed to write PM_GP1\n"); - return false; - } - - /* Read back for debug */ - xscom_read(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_GP1), &tmp); - prlog(PR_TRACE, "SLW: PMGP1 read 0x%016llx\n", tmp); - return true; -} - -static bool slw_get_idle_state_history(struct proc_chip *chip, struct cpu_thread *c) -{ - uint32_t core = pir_to_core_id(c->pir); - uint64_t tmp; - int rc; - - /* Cleanup history */ - rc = xscom_read(chip->id, - XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_IDLE_STATE_HISTORY_PHYP), - &tmp); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_GET), - "SLW: Failed to read PM_IDLE_STATE_HISTORY\n"); - return false; - } - - prlog(PR_TRACE, "SLW: core %x:%x history: 0x%016llx (old1)\n", - chip->id, core, tmp); - - rc = xscom_read(chip->id, - XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_IDLE_STATE_HISTORY_PHYP), - &tmp); - - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_GET), - "SLW: Failed to read PM_IDLE_STATE_HISTORY\n"); - return false; - } - - prlog(PR_TRACE, "SLW: core %x:%x history: 0x%016llx (old2)\n", - chip->id, core, tmp); - - return true; -} - -static bool idle_prepare_core(struct proc_chip *chip, struct cpu_thread *c) -{ - prlog(PR_TRACE, "FASTSLEEP: Prepare core %x:%x\n", - chip->id, pir_to_core_id(c->pir)); - - if(!slw_general_init(chip, c)) - return false; - if(!slw_set_overrides(chip, c)) - return false; - if(!slw_set_idle_mode(chip, c)) - return false; - if(!slw_get_idle_state_history(chip, c)) - return false; - - return true; - -} -#endif - static bool slw_set_overrides_p10(struct proc_chip *chip, struct cpu_thread *c) { uint64_t tmp; @@ -245,89 +91,6 @@ static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c) return true; } -/* Define device-tree fields */ -#define MAX_NAME_LEN 16 -struct cpu_idle_states { - char name[MAX_NAME_LEN]; - u32 latency_ns; - u32 residency_ns; - /* - * Register value/mask used to select different idle states. - * PMICR in POWER8 and PSSCR in POWER9 - */ - u64 pm_ctrl_reg_val; - u64 pm_ctrl_reg_mask; - u32 flags; -}; - -static struct cpu_idle_states nap_only_cpu_idle_states[] = { - { /* nap */ - .name = "nap", - .latency_ns = 4000, - .residency_ns = 100000, - .flags = 0*OPAL_PM_DEC_STOP \ - | 0*OPAL_PM_TIMEBASE_STOP \ - | 1*OPAL_PM_LOSE_USER_CONTEXT \ - | 0*OPAL_PM_LOSE_HYP_CONTEXT \ - | 0*OPAL_PM_LOSE_FULL_CONTEXT \ - | 1*OPAL_PM_NAP_ENABLED \ - | 0*OPAL_PM_SLEEP_ENABLED \ - | 0*OPAL_PM_WINKLE_ENABLED \ - | 0*OPAL_USE_PMICR, - .pm_ctrl_reg_val = 0, - .pm_ctrl_reg_mask = 0 }, -}; - -static struct cpu_idle_states power8_cpu_idle_states[] = { - { /* nap */ - .name = "nap", - .latency_ns = 4000, - .residency_ns = 100000, - .flags = 0*OPAL_PM_DEC_STOP \ - | 0*OPAL_PM_TIMEBASE_STOP \ - | 1*OPAL_PM_LOSE_USER_CONTEXT \ - | 0*OPAL_PM_LOSE_HYP_CONTEXT \ - | 0*OPAL_PM_LOSE_FULL_CONTEXT \ - | 1*OPAL_PM_NAP_ENABLED \ - | 0*OPAL_USE_PMICR, - .pm_ctrl_reg_val = 0, - .pm_ctrl_reg_mask = 0 }, - { /* fast sleep (with workaround) */ - .name = "fastsleep_", - .latency_ns = 40000, - .residency_ns = 300000000, - .flags = 1*OPAL_PM_DEC_STOP \ - | 1*OPAL_PM_TIMEBASE_STOP \ - | 1*OPAL_PM_LOSE_USER_CONTEXT \ - | 0*OPAL_PM_LOSE_HYP_CONTEXT \ - | 0*OPAL_PM_LOSE_FULL_CONTEXT \ - | 1*OPAL_PM_SLEEP_ENABLED_ER1 \ - | 0*OPAL_USE_PMICR, /* Not enabled until deep - states are available */ - .pm_ctrl_reg_val = OPAL_PM_FASTSLEEP_PMICR, - .pm_ctrl_reg_mask = OPAL_PM_SLEEP_PMICR_MASK }, - { /* Winkle */ - .name = "winkle", - .latency_ns = 10000000, - .residency_ns = 1000000000, /* Educated guess (not measured). - * Winkle is not currently used by - * linux cpuidle subsystem so we - * don't have real world user. - * However, this should be roughly - * accurate for when linux does - * use it. */ - .flags = 1*OPAL_PM_DEC_STOP \ - | 1*OPAL_PM_TIMEBASE_STOP \ - | 1*OPAL_PM_LOSE_USER_CONTEXT \ - | 1*OPAL_PM_LOSE_HYP_CONTEXT \ - | 1*OPAL_PM_LOSE_FULL_CONTEXT \ - | 1*OPAL_PM_WINKLE_ENABLED \ - | 0*OPAL_USE_PMICR, /* Currently choosing deep vs - fast via EX_PM_GP1 reg */ - .pm_ctrl_reg_val = 0, - .pm_ctrl_reg_mask = 0 }, -}; - /* * cpu_idle_states for key idle states of POWER9 that we want to * exploit. @@ -796,9 +559,9 @@ static void slw_late_init_p10(struct proc_chip *chip) void add_cpu_idle_state_properties(void) { struct dt_node *power_mgt; - struct cpu_idle_states *states; + struct cpu_idle_states *states = NULL; struct proc_chip *chip; - int nr_states; + int nr_states = 0; bool can_sleep = true; bool has_stop_inst = false; @@ -897,39 +660,12 @@ void add_cpu_idle_state_properties(void) } if (wakeup_engine_state != WAKEUP_ENGINE_PRESENT) has_deep_states = false; - } else if (chip->type == PROC_CHIP_P8_MURANO || - chip->type == PROC_CHIP_P8_VENICE || - chip->type == PROC_CHIP_P8_NAPLES) { - const struct dt_property *p; - - p = dt_find_property(dt_root, "ibm,enabled-idle-states"); - if (p) - prlog(PR_NOTICE, - "SLW: HB-provided idle states property found\n"); - states = power8_cpu_idle_states; - nr_states = ARRAY_SIZE(power8_cpu_idle_states); - - /* Check if hostboot say we can sleep */ - if (!p || !dt_prop_find_string(p, "fast-sleep")) { - prlog(PR_WARNING, "SLW: Sleep not enabled by HB" - " on this platform\n"); - can_sleep = false; - } - - /* Clip to NAP only on Murano and Venice DD1.x */ - if ((chip->type == PROC_CHIP_P8_MURANO || - chip->type == PROC_CHIP_P8_VENICE) && - chip->ec_level < 0x20) { - prlog(PR_NOTICE, "SLW: Sleep not enabled on P8 DD1.x\n"); - can_sleep = false; - } - +#ifdef CONFIG_P8 } else { - states = nap_only_cpu_idle_states; - nr_states = ARRAY_SIZE(nap_only_cpu_idle_states); + find_cpu_idle_state_properties_p8(&states, &nr_states, &can_sleep); +#endif } - /* * Currently we can't append strings and cells to dt properties. * So create buffers to which you can append values, then create @@ -1112,183 +848,6 @@ static bool slw_image_check_p9(struct proc_chip *chip) } -#ifdef CONFIG_P8 -static void slw_patch_regs(struct proc_chip *chip) -{ - struct cpu_thread *c; - void *image = (void *)chip->slw_base; - int rc; - - for_each_available_cpu(c) { - if (c->chip_id != chip->id) - continue; - - /* Clear HRMOR */ - rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, - P8_SPR_HRMOR, 0, - cpu_get_core_index(c), - cpu_get_thread_index(c)); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: Failed to set HRMOR for CPU %x\n", - c->pir); - } - - /* XXX Add HIDs etc... */ - } -} - -static bool slw_image_check_p8(struct proc_chip *chip) -{ - int64_t rc; - - prlog(PR_DEBUG, "SLW: slw_check chip 0x%x\n", chip->id); - if (!chip->slw_base) { - prerror("SLW: No image found !\n"); - return false; - } - - /* Check actual image size */ - rc = sbe_xip_get_scalar((void *)chip->slw_base, "image_size", - &chip->slw_image_size); - if (rc != 0) { - log_simple_error(&e_info(OPAL_RC_SLW_INIT), - "SLW: Error %lld reading SLW image size\n", rc); - /* XXX Panic ? */ - chip->slw_base = 0; - chip->slw_bar_size = 0; - chip->slw_image_size = 0; - return false; - } - prlog(PR_DEBUG, "SLW: Image size from image: 0x%llx\n", - chip->slw_image_size); - - if (chip->slw_image_size > chip->slw_bar_size) { - log_simple_error(&e_info(OPAL_RC_SLW_INIT), - "SLW: Built-in image size larger than BAR size !\n"); - /* XXX Panic ? */ - return false; - } - return true; - -} - -static void slw_late_init_p8(struct proc_chip *chip) -{ - - prlog(PR_DEBUG, "SLW: late Init chip 0x%x\n", chip->id); - - /* Patch SLW image */ - slw_patch_regs(chip); - -} -static void slw_init_chip_p8(struct proc_chip *chip) -{ - struct cpu_thread *c; - - prlog(PR_DEBUG, "SLW: Init chip 0x%x\n", chip->id); - /* At power ON setup inits for fast-sleep */ - for_each_available_core_in_chip(c, chip->id) { - idle_prepare_core(chip, c); - } -} - -/* Workarounds while entering fast-sleep */ - -static void fast_sleep_enter(void) -{ - uint32_t core = pir_to_core_id(this_cpu()->pir); - uint32_t chip_id = this_cpu()->chip_id; - struct cpu_thread *primary_thread; - uint64_t tmp; - int rc; - - primary_thread = this_cpu()->primary; - - rc = xscom_read(chip_id, XSCOM_ADDR_P8_EX(core, L2_FIR_ACTION1), - &tmp); - if (rc) { - prlog(PR_WARNING, "fast_sleep_enter XSCOM failed(1):" - " rc=%d chip_id=%d core=%d\n", - rc, chip_id, core); - return; - } - - primary_thread->save_l2_fir_action1 = tmp; - primary_thread->in_fast_sleep = true; - - tmp = tmp & ~0x0200000000000000ULL; - rc = xscom_write(chip_id, XSCOM_ADDR_P8_EX(core, L2_FIR_ACTION1), - tmp); - if (rc) { - prlog(PR_WARNING, "fast_sleep_enter XSCOM failed(2):" - " rc=%d chip_id=%d core=%d\n", - rc, chip_id, core); - return; - } - rc = xscom_read(chip_id, XSCOM_ADDR_P8_EX(core, L2_FIR_ACTION1), - &tmp); - if (rc) { - prlog(PR_WARNING, "fast_sleep_enter XSCOM failed(3):" - " rc=%d chip_id=%d core=%d\n", - rc, chip_id, core); - return; - } - -} - -/* Workarounds while exiting fast-sleep */ - -void fast_sleep_exit(void) -{ - uint32_t core = pir_to_core_id(this_cpu()->pir); - uint32_t chip_id = this_cpu()->chip_id; - struct cpu_thread *primary_thread; - int rc; - - primary_thread = this_cpu()->primary; - primary_thread->in_fast_sleep = false; - - rc = xscom_write(chip_id, XSCOM_ADDR_P8_EX(core, L2_FIR_ACTION1), - primary_thread->save_l2_fir_action1); - if (rc) { - prlog(PR_WARNING, "fast_sleep_exit XSCOM failed:" - " rc=%d chip_id=%d core=%d\n", - rc, chip_id, core); - return; - } -} - -/* - * Setup and cleanup method for fast-sleep workarounds - * state = 1 fast-sleep - * enter = 1 Enter state - * exit = 0 Exit state - */ - -static int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t enter) -{ - /* Only fast-sleep for now */ - if (state != 1) - return OPAL_PARAMETER; - - switch(enter) { - case 1: - fast_sleep_enter(); - break; - case 0: - fast_sleep_exit(); - break; - default: - return OPAL_PARAMETER; - } - - return OPAL_SUCCESS; -} - -opal_call(OPAL_CONFIG_CPU_IDLE_STATE, opal_config_cpu_idle_state, 2); -#endif - int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) { @@ -1330,28 +889,7 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) #ifdef CONFIG_P8 } else if (proc_gen == proc_gen_p8) { - int spr_is_supported = 0; - void *image; - int i; - - /* Check of the SPR is supported by libpore */ - for (i = 0; i < SLW_SPR_REGS_SIZE ; i++) { - if (sprn == SLW_SPR_REGS[i].value) { - spr_is_supported = 1; - break; - } - } - if (!spr_is_supported) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: Trying to set unsupported spr for CPU %x\n", - c->pir); - return OPAL_UNSUPPORTED; - } - image = (void *)chip->slw_base; - rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, - sprn, val, - cpu_get_core_index(c), - cpu_get_thread_index(c)); + rc = opal_slw_set_reg_p8(c, chip, sprn, val); #endif } else { log_simple_error(&e_info(OPAL_RC_SLW_REG), @@ -1386,18 +924,11 @@ void slw_init(void) return; } - if (proc_gen == proc_gen_p8) { #ifdef CONFIG_P8 - for_each_chip(chip) { - slw_init_chip_p8(chip); - if(slw_image_check_p8(chip)) - wakeup_engine_state = WAKEUP_ENGINE_PRESENT; - if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) - slw_late_init_p8(chip); - } - p8_sbe_init_timer(); + if (proc_gen == proc_gen_p8) + slw_p8_init(); #endif - } else if (proc_gen == proc_gen_p9) { + if (proc_gen == proc_gen_p9) { for_each_chip(chip) { slw_init_chip_p9(chip); if(slw_image_check_p9(chip)) diff --git a/hw/xive.c b/hw/xive.c index 51b03549a..34b92f1e9 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/hw/xive2.c b/hw/xive2.c index 30293cdf1..ea55423bb 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -9,6 +9,7 @@ #define pr_fmt(fmt) "XIVE: " fmt #include +#include #include #include #include diff --git a/include/skiboot.h b/include/skiboot.h index e2a1b5fc6..db08f45f4 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -216,7 +216,6 @@ extern void uart_init(void); extern void mbox_init(void); extern void early_uart_init(void); extern void homer_init(void); -extern void slw_init(void); extern void add_cpu_idle_state_properties(void); extern void lpc_rtc_init(void); @@ -303,19 +302,8 @@ extern int prd_hbrt_fsp_msg_notify(void *data, u32 dsize); /* Flatten device-tree */ extern void *create_dtb(const struct dt_node *root, bool exclusive); -/* Track failure in Wakup engine */ -enum wakeup_engine_states { - WAKEUP_ENGINE_NOT_PRESENT, - WAKEUP_ENGINE_PRESENT, - WAKEUP_ENGINE_FAILED -}; -extern enum wakeup_engine_states wakeup_engine_state; -extern bool has_deep_states; extern void nx_p9_rng_late_init(void); -/* Patch SPR in SLW image */ -extern int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val); - extern void fast_sleep_exit(void); /* Fallback fake RTC */ diff --git a/include/slw.h b/include/slw.h new file mode 100644 index 000000000..299cbf191 --- /dev/null +++ b/include/slw.h @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + +#ifndef __SLW_H +#define __SLW_H + +#include +#include + +#include + +/* Define device-tree fields */ +#define MAX_NAME_LEN 16 +struct cpu_idle_states { + char name[MAX_NAME_LEN]; + u32 latency_ns; + u32 residency_ns; + /* + * Register value/mask used to select different idle states. + * PMICR in POWER8 and PSSCR in POWER9 + */ + u64 pm_ctrl_reg_val; + u64 pm_ctrl_reg_mask; + u32 flags; +}; + +/* Track failure in Wakup engine */ +enum wakeup_engine_states { + WAKEUP_ENGINE_NOT_PRESENT, + WAKEUP_ENGINE_PRESENT, + WAKEUP_ENGINE_FAILED +}; +extern enum wakeup_engine_states wakeup_engine_state; +extern bool has_deep_states; + +/* Patch SPR in SLW image */ +extern int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val); + +extern void slw_init(void); + +/* P8 specific */ +struct cpu_thread; +struct proc_chip; +extern int64_t opal_slw_set_reg_p8(struct cpu_thread *c, struct proc_chip *chip, + uint64_t sprn, uint64_t val); +extern void slw_p8_init(void); +extern void find_cpu_idle_state_properties_p8(struct cpu_idle_states **states, int *nr_states, bool *can_sleep); + +#endif /* __SKIBOOT_H */ From patchwork Mon Dec 20 12:22:50 2021 Content-Type: text/plain; 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[121.44.67.22]) by smtp.gmail.com with ESMTPSA id p17sm20661731pfh.86.2021.12.20.04.23.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Dec 2021 04:23:20 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 20 Dec 2021 22:22:50 +1000 Message-Id: <20211220122252.986542-8-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211220122252.986542-1-npiggin@gmail.com> References: <20211220122252.986542-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v5 7/9] hwprobe: convert vas_init(), nx_init() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith Convert VAS and NX to use the hwprobe facility for init. Reviewed-by: Dan Horák [npiggin: remove imc_init because it moved later in boot (fbcbd4e47c)] Signed-off-by: Stewart Smith --- core/init.c | 6 ------ hw/nx.c | 2 ++ hw/vas.c | 2 ++ 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/core/init.c b/core/init.c index deead5ecc..b4d33518d 100644 --- a/core/init.c +++ b/core/init.c @@ -1356,12 +1356,6 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* Catalog decompression routine */ imc_decompress_catalog(); - /* Virtual Accelerator Switchboard */ - vas_init(); - - /* NX init */ - nx_init(); - /* Probe all HWPROBE hardware we have code linked for */ probe_hardware(); diff --git a/hw/nx.c b/hw/nx.c index 13c681b2c..8766cef29 100644 --- a/hw/nx.c +++ b/hw/nx.c @@ -137,3 +137,5 @@ void nx_init(void) if (proc_gen >= proc_gen_p9) darn_init(); } + +DEFINE_HWPROBE_DEPS(nx, nx_init, "vas"); diff --git a/hw/vas.c b/hw/vas.c index 0dbe0bcda..96ca055cc 100644 --- a/hw/vas.c +++ b/hw/vas.c @@ -637,3 +637,5 @@ out: vas_err("Disabled (failed initialization)\n"); return; } + +DEFINE_HWPROBE(vas, vas_init); From patchwork Mon Dec 20 12:22:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1571017 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=dl9h36Cj; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JHf0564CFz9s3q for ; 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[121.44.67.22]) by smtp.gmail.com with ESMTPSA id p17sm20661731pfh.86.2021.12.20.04.23.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Dec 2021 04:23:23 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 20 Dec 2021 22:22:51 +1000 Message-Id: <20211220122252.986542-9-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211220122252.986542-1-npiggin@gmail.com> References: <20211220122252.986542-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v5 8/9] npu: Move npu.o and npu-hw-procedules.o under CONIFG_P8 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith Make the P8 NPU code depend on CONFIG_P8. This requires converting a low level function to a no-op because the HMI NPU handling is not so cleanly layered. This saves an extra 6kb of skiboot.lid.xz. Reviewed-by: Dan Horák Signed-off-by: Stewart Smith --- hw/Makefile.inc | 3 ++- include/npu.h | 7 +++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/Makefile.inc b/hw/Makefile.inc index 7327cec35..ca548799d 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -4,13 +4,14 @@ HW_OBJS = xscom.o chiptod.o lpc.o lpc-uart.o psi.o sbe.o HW_OBJS += homer.o slw.o occ.o fsi-master.o centaur.o imc.o HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-compress.o nx-842.o nx-gzip.o HW_OBJS += sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o -HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o +HW_OBJS += dts.o lpc-rtc.o xive.o phb4.o HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o HW_OBJS += occ-sensor.o vas.o dio-p9.o lpc-port80h.o cache-p9.o HW_OBJS += npu-opal.o ocmb.o xive2.o pau.o pau-hw-procedures.o ifeq ($(CONFIG_P8),1) HW_OBJS += phb3.o sbe-p8.o slw-p8.o +HW_OBJS += npu.o npu-hw-procedures.o endif HW=hw/built-in.a diff --git a/include/npu.h b/include/npu.h index 50cc9c9fc..f5707282c 100644 --- a/include/npu.h +++ b/include/npu.h @@ -153,7 +153,14 @@ int64_t npu_dev_procedure(void *dev, struct pci_cfg_reg_filter *pcrf, uint32_t offset, uint32_t len, uint32_t *data, bool write); +#ifdef CONFIG_P8 void npu_set_fence_state(struct npu *p, bool fence); +#else +static inline void npu_set_fence_state(struct npu *p __unused, bool fence __unused) +{ + /* Should never be called */ +} +#endif void npu_dev_procedure_reset(struct npu_dev *dev); #define NPUDBG(p, fmt, a...) prlog(PR_DEBUG, "NPU%d: " fmt, \ From patchwork Mon Dec 20 12:22:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1571018 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=J9uGvMZv; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; 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[121.44.67.22]) by smtp.gmail.com with ESMTPSA id p17sm20661731pfh.86.2021.12.20.04.23.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Dec 2021 04:23:25 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 20 Dec 2021 22:22:52 +1000 Message-Id: <20211220122252.986542-10-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211220122252.986542-1-npiggin@gmail.com> References: <20211220122252.986542-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v5 9/9] platforms: put P8 platforms behind CONFIG_P8 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith Shaves an additional 4kb off skiboot.lid.xz. Reviewed-by: Dan Horák Signed-off-by: Stewart Smith --- platforms/astbmc/Makefile.inc | 12 ++++++++---- platforms/ibm-fsp/Makefile.inc | 7 ++++++- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/platforms/astbmc/Makefile.inc b/platforms/astbmc/Makefile.inc index 070813231..1cdf37f2a 100644 --- a/platforms/astbmc/Makefile.inc +++ b/platforms/astbmc/Makefile.inc @@ -1,13 +1,17 @@ SUBDIRS += $(PLATDIR)/astbmc ASTBMC_OBJS = pnor.o common.o slots.o \ - palmetto.o habanero.o firestone.o \ - p8dtu.o p8dnu.o \ - garrison.o barreleye.o \ witherspoon.o zaius.o romulus.o p9dsu.o \ - vesnin.o nicole.o mihawk.o mowgli.o \ + nicole.o mihawk.o mowgli.o \ talos.o blackbird.o \ swift.o rainier.o +ifeq ($(CONFIG_P8),1) +ASTBMC_OBJS += palmetto.o habanero.o firestone.o \ + p8dtu.o p8dnu.o \ + garrison.o barreleye.o \ + vesnin.o +endif + ASTBMC = $(PLATDIR)/astbmc/built-in.a $(ASTBMC): $(ASTBMC_OBJS:%=$(PLATDIR)/astbmc/%) diff --git a/platforms/ibm-fsp/Makefile.inc b/platforms/ibm-fsp/Makefile.inc index 8883f09c1..fd80a79a9 100644 --- a/platforms/ibm-fsp/Makefile.inc +++ b/platforms/ibm-fsp/Makefile.inc @@ -1,7 +1,12 @@ SUBDIRS += $(PLATDIR)/ibm-fsp IBM_FSP_OBJS = common.o lxvpd.o hostservices.o fsp-vpd.o \ - firenze.o firenze-pci.o zz.o + firenze-pci.o zz.o + +ifeq ($(CONFIG_P8),1) +IBM_FSP_OBJS += firenze.o +endif + IBM_FSP = $(PLATDIR)/ibm-fsp/built-in.a ifeq ($(CONFIG_FSP),1)