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[203.219.139.206]) by smtp.gmail.com with ESMTPSA id z13sm7835249pfj.160.2021.12.16.18.36.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 18:36:59 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Fri, 17 Dec 2021 12:36:39 +1000 Message-Id: <20211217023647.715283-2-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211217023647.715283-1-npiggin@gmail.com> References: <20211217023647.715283-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 1/9] Introduce hwprobe facility to avoid hard-coding probe functions X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith hwprobe is a little system to have different hardware probing modules run in the dependency order they choose rather than hard coding that order in core/init.c. Reviewed-by: Dan Horák Signed-off-by: Stewart Smith --- core/Makefile.inc | 1 + core/hwprobe.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++ core/init.c | 3 ++ include/skiboot.h | 39 +++++++++++++++++++++++++- skiboot.lds.S | 6 ++++ 5 files changed, 118 insertions(+), 1 deletion(-) create mode 100644 core/hwprobe.c diff --git a/core/Makefile.inc b/core/Makefile.inc index 829800e5b..f80019b6a 100644 --- a/core/Makefile.inc +++ b/core/Makefile.inc @@ -13,6 +13,7 @@ CORE_OBJS += timer.o i2c.o rtc.o flash.o sensor.o ipmi-opal.o CORE_OBJS += flash-subpartition.o bitmap.o buddy.o pci-quirk.o powercap.o psr.o CORE_OBJS += pci-dt-slot.o direct-controls.o cpufeatures.o CORE_OBJS += flash-firmware-versions.o opal-dump.o +CORE_OBJS += hwprobe.o ifeq ($(SKIBOOT_GCOV),1) CORE_OBJS += gcov-profiling.o diff --git a/core/hwprobe.c b/core/hwprobe.c new file mode 100644 index 000000000..0a641ada5 --- /dev/null +++ b/core/hwprobe.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2021 Stewart Smith */ + +#define pr_fmt(fmt) "HWPROBE: " fmt +#include +#include + +static bool hwprobe_deps_satisfied(const struct hwprobe *hwp) +{ + struct hwprobe *hwprobe; + const char **dep; + unsigned int i; + + dep = hwp->deps; + if (dep == NULL) + return true; + + + prlog(PR_TRACE, "Checking deps for %s\n", hwp->name); + + while (*dep != NULL) { + prlog(PR_TRACE, "Checking %s dep %s\n", hwp->name, *dep); + hwprobe = &__hwprobes_start; + for (i = 0; &hwprobe[i] < &__hwprobes_end; i++) { + if(strcmp(hwprobe[i].name, *dep) == 0 && + !hwprobe[i].probed) + return false; + } + dep++; + } + + prlog(PR_TRACE, "deps for %s are satisfied!\n", hwp->name); + return true; + +} + +void probe_hardware(void) +{ + struct hwprobe *hwprobe; + unsigned int i; + bool work_todo = true; + bool did_something = true; + + while (work_todo) { + work_todo = false; + did_something = false; + hwprobe = &__hwprobes_start; + prlog(PR_DEBUG, "Begin loop\n"); + for (i = 0; &hwprobe[i] < &__hwprobes_end; i++) { + if (hwprobe[i].probed) + continue; + if (hwprobe_deps_satisfied(&hwprobe[i])) { + prlog(PR_DEBUG, "Probing %s...\n", hwprobe[i].name); + if (hwprobe[i].probe) + hwprobe[i].probe(); + did_something = true; + hwprobe[i].probed = true; + } else { + prlog(PR_DEBUG, "Dependencies for %s not yet satisfied, skipping\n", + hwprobe[i].name); + work_todo = true; + } + } + + if (work_todo && !did_something) { + prlog(PR_ERR, "Cannot satisfy dependencies! Bailing out\n"); + break; + } + } +} diff --git a/core/init.c b/core/init.c index aab0e9092..5c2bd7fdc 100644 --- a/core/init.c +++ b/core/init.c @@ -1374,6 +1374,9 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* Probe PAUs */ probe_pau(); + /* Probe all HWPROBE hardware we have code linked for*/ + probe_hardware(); + /* Initialize PCI */ pci_init_slots(); diff --git a/include/skiboot.h b/include/skiboot.h index 312a43654..d1553c4ef 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -1,5 +1,7 @@ // SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later -/* Copyright 2013-2019 IBM Corp. */ +/* Copyright 2013-2019 IBM Corp. + * Copyright 2021 Stewart Smith + */ #ifndef __SKIBOOT_H #define __SKIBOOT_H @@ -346,4 +348,39 @@ extern int fake_nvram_info(uint32_t *total_size); extern int fake_nvram_start_read(void *dst, uint32_t src, uint32_t len); extern int fake_nvram_write(uint32_t offset, void *src, uint32_t size); +/* + * A bunch of hardware needs to be probed, sometimes in a particular order. + * Very simple dependency graph, with a even simpler way to resolve it. + * But it means we can now at link time choose what hardware we support. + * This struct should not be defined directly but with the macros. + */ +struct hwprobe { + const char *name; + void (*probe)(void); + + bool probed; + + /* NULL or NULL-terminated array of strings */ + const char **deps; +}; + +#define DEFINE_HWPROBE(__name, __probe) \ +static const struct hwprobe __used __section(".hwprobes") hwprobe_##__name = { \ + .name = #__name, \ + .probe = __probe, \ + .deps = NULL, \ +} + +#define DEFINE_HWPROBE_DEPS(__name, __probe, ...) \ +static const struct hwprobe __used __section(".hwprobes") hwprobe_##__name = { \ + .name = #__name, \ + .probe = __probe, \ + .deps = (const char *[]){ __VA_ARGS__, NULL}, \ +} + +extern struct hwprobe __hwprobes_start; +extern struct hwprobe __hwprobes_end; + +extern void probe_hardware(void); + #endif /* __SKIBOOT_H */ diff --git a/skiboot.lds.S b/skiboot.lds.S index 11613842e..058848fa9 100644 --- a/skiboot.lds.S +++ b/skiboot.lds.S @@ -166,6 +166,12 @@ SECTIONS __platforms_end = .; } + .hwprobes : { + __hwprobes_start = .; + KEEP(*(.hwprobes)) + __hwprobes_end = .; + } + /* Relocations */ . = ALIGN(0x10); .dynamic : { From patchwork Fri Dec 17 02:36:40 2021 Content-Type: text/plain; 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[203.219.139.206]) by smtp.gmail.com with ESMTPSA id z13sm7835249pfj.160.2021.12.16.18.37.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 18:37:02 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Fri, 17 Dec 2021 12:36:40 +1000 Message-Id: <20211217023647.715283-3-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211217023647.715283-1-npiggin@gmail.com> References: <20211217023647.715283-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 2/9] hwprobe: convert PHB, NPU, PAU subsystems to hwprobe X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith Reviewed-by: Dan Horák [npiggin: split out from initial hwprobe pach] Signed-off-by: Stewart Smith --- core/init.c | 15 +-------------- hw/npu.c | 4 +++- hw/npu2-common.c | 4 +++- hw/pau.c | 3 ++- hw/phb3.c | 4 ++-- hw/phb4.c | 4 +++- include/skiboot.h | 5 ----- 7 files changed, 14 insertions(+), 25 deletions(-) diff --git a/core/init.c b/core/init.c index 5c2bd7fdc..c3e0c494d 100644 --- a/core/init.c +++ b/core/init.c @@ -1361,20 +1361,7 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* NX init */ nx_init(); - /* Probe PHB3 on P8 */ - probe_phb3(); - - /* Probe PHB4 on P9 and PHB5 on P10 */ - probe_phb4(); - - /* Probe NPUs */ - probe_npu(); - probe_npu2(); - - /* Probe PAUs */ - probe_pau(); - - /* Probe all HWPROBE hardware we have code linked for*/ + /* Probe all HWPROBE hardware we have code linked for */ probe_hardware(); /* Initialize PCI */ diff --git a/hw/npu.c b/hw/npu.c index dba7ee50f..35e6372d2 100644 --- a/hw/npu.c +++ b/hw/npu.c @@ -1679,7 +1679,7 @@ static void npu_create_phb(struct dt_node *dn) npu_hw_init(p); } -void probe_npu(void) +static void probe_npu(void) { struct dt_node *np; @@ -1691,3 +1691,5 @@ void probe_npu(void) dt_for_each_compatible(dt_root, np, "ibm,power8-npu-pciex") npu_create_phb(np); } + +DEFINE_HWPROBE_DEPS(npu, probe_npu, "phb3"); diff --git a/hw/npu2-common.c b/hw/npu2-common.c index b3f500f4b..02f102fe5 100644 --- a/hw/npu2-common.c +++ b/hw/npu2-common.c @@ -619,7 +619,7 @@ static void setup_devices(struct npu2 *npu) npu2_opencapi_init_npu(npu); } -void probe_npu2(void) +static void probe_npu2(void) { struct proc_chip *chip = next_chip(NULL); struct npu2 *npu; @@ -658,3 +658,5 @@ void probe_npu2(void) setup_devices(npu); } } + +DEFINE_HWPROBE_DEPS(npu2, probe_npu2, "phb4"); diff --git a/hw/pau.c b/hw/pau.c index a34d6dab1..1a3fbfaf7 100644 --- a/hw/pau.c +++ b/hw/pau.c @@ -2074,7 +2074,7 @@ static void pau_init(struct pau *pau) pau_opencapi_init(pau); } -void probe_pau(void) +static void probe_pau(void) { struct dt_node *dn; struct pau *pau; @@ -2093,3 +2093,4 @@ void probe_pau(void) pau_init(pau); } } +DEFINE_HWPROBE_DEPS(pau, probe_pau, "phb4"); diff --git a/hw/phb3.c b/hw/phb3.c index 09255a0a6..f46a43c9d 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -4993,7 +4993,7 @@ static void phb3_probe_pbcq(struct dt_node *pbcq) } -void probe_phb3(void) +static void probe_phb3(void) { struct dt_node *np; @@ -5006,4 +5006,4 @@ void probe_phb3(void) phb3_create(np); } - +DEFINE_HWPROBE(phb3, probe_phb3); diff --git a/hw/phb4.c b/hw/phb4.c index 4daad148a..f329e1309 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -6368,7 +6368,7 @@ static void phb4_probe_pbcq(struct dt_node *pbcq) } } -void probe_phb4(void) +static void probe_phb4(void) { struct dt_node *np; const char *s; @@ -6404,3 +6404,5 @@ void probe_phb4(void) phb4_create(np); } } + +DEFINE_HWPROBE(phb4, probe_phb4); diff --git a/include/skiboot.h b/include/skiboot.h index d1553c4ef..e2a1b5fc6 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -210,13 +210,8 @@ extern void copy_sreset_vector_fast_reboot(void); extern void patch_traps(bool enable); /* Various probe routines, to replace with an initcall system */ -extern void probe_phb3(void); -extern void probe_phb4(void); extern int preload_capp_ucode(void); extern void preload_io_vpd(void); -extern void probe_npu(void); -extern void probe_npu2(void); -extern void probe_pau(void); extern void uart_init(void); extern void mbox_init(void); extern void early_uart_init(void); From patchwork Fri Dec 17 02:36:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1569690 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[203.219.139.206]) by smtp.gmail.com with ESMTPSA id z13sm7835249pfj.160.2021.12.16.18.37.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 18:37:04 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Fri, 17 Dec 2021 12:36:41 +1000 Message-Id: <20211217023647.715283-4-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211217023647.715283-1-npiggin@gmail.com> References: <20211217023647.715283-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 3/9] Add CONFIG_P8 with PHB3 behind it X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith We can use a base CPU of POWER9 if we don't have P8. We can also hide PHB3 code behind this, and shave 12kb off skiboot.lid.xz Reviewed-by: Dan Horák [npiggin: add cpp define, fail gracefully on P8] Signed-off-by: Stewart Smith --- Makefile | 2 ++ Makefile.main | 15 ++++++++++++++- core/cpu.c | 11 +++++++++-- hw/Makefile.inc | 5 ++++- 4 files changed, 29 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index d236df9ec..625f212ea 100644 --- a/Makefile +++ b/Makefile @@ -59,6 +59,8 @@ ELF_ABI_v2 ?= $(LITTLE_ENDIAN) DEAD_CODE_ELIMINATION ?= 0 # Try to build without FSP code CONFIG_FSP?=1 +# Try to build without POWER8 support +CONFIG_P8?=1 # # Where is the source directory, must be a full path (no ~) diff --git a/Makefile.main b/Makefile.main index c8a63e8b1..2a346a6c9 100644 --- a/Makefile.main +++ b/Makefile.main @@ -96,7 +96,11 @@ CPPFLAGS += -DDEBUG -DCCAN_LIST_DEBUG endif CFLAGS := -fno-strict-aliasing -pie -fpie -fno-pic -m64 -fno-asynchronous-unwind-tables +ifeq ($(CONFIG_P8),1) CFLAGS += -mcpu=power8 +else +CFLAGS += -mcpu=power9 +endif CFLAGS += -Wl,--oformat,elf64-powerpc -ggdb # r13,r14,r15 are preserved for OS to use as fixed registers. # These could be saved and restored in and out of skiboot, but it's more @@ -156,6 +160,10 @@ else CFLAGS += -fno-stack-protector endif +# Add preprocessor defines for CONFIG_ options here +ifeq ($(CONFIG_P8),1) +CFLAGS += -DCONFIG_P8=1 +endif CFLAGS += $(call try-cflag,$(CC),-Wjump-misses-init) \ $(call try-cflag,$(CC),-Wsuggest-attribute=const) \ @@ -173,7 +181,12 @@ LDFLAGS := -m64 -static -nostdlib -pie LDFLAGS += -Wl,-pie LDFLAGS += -Wl,-Ttext-segment,$(LD_TEXT) -Wl,-N -Wl,--build-id=none LDFLAGS += -Wl,--no-multi-toc -LDFLAGS += -mcpu=power8 -Wl,--oformat,elf64-powerpc +ifeq ($(CONFIG_P8),1) +LDFLAGS += -mcpu=power8 +else +LDFLAGS += -mcpu=power9 +endif +LDFLAGS += -Wl,--oformat,elf64-powerpc LDFLAGS_FINAL = -m elf64lppc --no-multi-toc -N --build-id=none --whole-archive LDFLAGS_FINAL += -static -nostdlib -pie -Ttext-segment=$(LD_TEXT) --oformat=elf64-powerpc LDFLAGS_FINAL += --orphan-handling=warn diff --git a/core/cpu.c b/core/cpu.c index 95b780866..98a03db75 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -1066,9 +1066,16 @@ void init_boot_cpu(void) cpu_thread_count = 1; } - if (proc_gen == proc_gen_p8 && (PVR_VERS_MAJ(mfspr(SPR_PVR)) == 1)) { - prerror("CPU: POWER8 DD1 is not supported\n"); + if (proc_gen == proc_gen_p8) { +#ifdef CONFIG_P8 + if (PVR_VERS_MAJ(mfspr(SPR_PVR)) == 1) { + prerror("CPU: POWER8 DD1 is not supported\n"); + abort(); + } +#else + prerror("CPU: POWER8 detected but CONFIG_P8 not set\n"); abort(); +#endif } if (is_power9n(pvr) && (PVR_VERS_MAJ(pvr) == 1)) { diff --git a/hw/Makefile.inc b/hw/Makefile.inc index 9fcbb63be..e273e898c 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -3,12 +3,15 @@ SUBDIRS += hw HW_OBJS = xscom.o chiptod.o lpc.o lpc-uart.o psi.o HW_OBJS += homer.o slw.o occ.o fsi-master.o centaur.o imc.o HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-compress.o nx-842.o nx-gzip.o -HW_OBJS += phb3.o sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o +HW_OBJS += sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o HW_OBJS += npu-opal.o ocmb.o xive2.o pau.o pau-hw-procedures.o +ifeq ($(CONFIG_P8),1) +HW_OBJS += phb3.o +endif HW=hw/built-in.a include $(SRC)/hw/fsp/Makefile.inc From patchwork Fri Dec 17 02:36:42 2021 Content-Type: text/plain; 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[203.219.139.206]) by smtp.gmail.com with ESMTPSA id z13sm7835249pfj.160.2021.12.16.18.37.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 18:37:07 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Fri, 17 Dec 2021 12:36:42 +1000 Message-Id: <20211217023647.715283-5-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211217023647.715283-1-npiggin@gmail.com> References: <20211217023647.715283-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 4/9] hw/slw: Move P8 bits behind CONFIG_P8 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This saves about 3kB from skiboot.lid.xz Reviewed-by: Dan Horák Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 2 + hw/slw.c | 176 ++++++++++++++++++++++--------------------- libpore/Makefile.inc | 8 +- 3 files changed, 100 insertions(+), 86 deletions(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 9f92525a9..2696348af 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -272,6 +272,7 @@ static void cleanup_cpu_state(void) /* XXX Update the SLW copies ! Also dbl check HIDs etc... */ init_shared_sprs(); +#ifdef CONFIG_P8 if (proc_gen == proc_gen_p8) { /* If somebody was in fast_sleep, we may have a * workaround to undo @@ -287,6 +288,7 @@ static void cleanup_cpu_state(void) */ cleanup_local_tlb(); } +#endif /* And we might have lost TB sync */ chiptod_wakeup_resync(); diff --git a/hw/slw.c b/hw/slw.c index eb67998d1..bc53960b7 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -32,19 +32,20 @@ enum wakeup_engine_states wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; bool has_deep_states = false; -DEFINE_LOG_ENTRY(OPAL_RC_SLW_INIT, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, - OPAL_PLATFORM_FIRMWARE, OPAL_PREDICTIVE_ERR_GENERAL, - OPAL_NA); - DEFINE_LOG_ENTRY(OPAL_RC_SLW_SET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_INFO, OPAL_NA); -DEFINE_LOG_ENTRY(OPAL_RC_SLW_GET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, +DEFINE_LOG_ENTRY(OPAL_RC_SLW_REG, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_INFO, OPAL_NA); -DEFINE_LOG_ENTRY(OPAL_RC_SLW_REG, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, +#ifdef CONFIG_P8 +DEFINE_LOG_ENTRY(OPAL_RC_SLW_INIT, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, + OPAL_PLATFORM_FIRMWARE, OPAL_PREDICTIVE_ERR_GENERAL, + OPAL_NA); + +DEFINE_LOG_ENTRY(OPAL_RC_SLW_GET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_INFO, OPAL_NA); @@ -98,59 +99,6 @@ static bool slw_set_overrides(struct proc_chip *chip, struct cpu_thread *c) return true; } -static bool slw_set_overrides_p10(struct proc_chip *chip, struct cpu_thread *c) -{ - uint64_t tmp; - int rc; - uint32_t core = pir_to_core_id(c->pir); - - /* Special wakeup bits that could hold power mgt */ - rc = xscom_read(chip->id, - XSCOM_ADDR_P10_QME_CORE(core, P10_QME_SPWU_HYP), - &tmp); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_SET), - "SLW: Failed to read P10_QME_SPWU_HYP\n"); - return false; - } - if (tmp & P10_SPWU_REQ) - prlog(PR_WARNING, - "SLW: core %d P10_QME_SPWU_HYP requested 0x%016llx\n", - core, tmp); - - return true; -} - - -static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c) -{ - uint64_t tmp; - int rc; - uint32_t core = pir_to_core_id(c->pir); - - /* Special wakeup bits that could hold power mgt */ - rc = xscom_read(chip->id, - XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP), - &tmp); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_SET), - "SLW: Failed to read EC_PPM_SPECIAL_WKUP_HYP\n"); - return false; - } - if (tmp) - prlog(PR_WARNING, - "SLW: core %d EC_PPM_SPECIAL_WKUP_HYP read 0x%016llx\n", - core, tmp); - rc = xscom_read(chip->id, - XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_OTR), - &tmp); - if (tmp) - prlog(PR_WARNING, - "SLW: core %d EC_PPM_SPECIAL_WKUP_OTR read 0x%016llx\n", - core, tmp); - return true; -} - static bool slw_set_idle_mode(struct proc_chip *chip, struct cpu_thread *c) { uint32_t core = pir_to_core_id(c->pir); @@ -242,6 +190,60 @@ static bool idle_prepare_core(struct proc_chip *chip, struct cpu_thread *c) return true; } +#endif + +static bool slw_set_overrides_p10(struct proc_chip *chip, struct cpu_thread *c) +{ + uint64_t tmp; + int rc; + uint32_t core = pir_to_core_id(c->pir); + + /* Special wakeup bits that could hold power mgt */ + rc = xscom_read(chip->id, + XSCOM_ADDR_P10_QME_CORE(core, P10_QME_SPWU_HYP), + &tmp); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_SET), + "SLW: Failed to read P10_QME_SPWU_HYP\n"); + return false; + } + if (tmp & P10_SPWU_REQ) + prlog(PR_WARNING, + "SLW: core %d P10_QME_SPWU_HYP requested 0x%016llx\n", + core, tmp); + + return true; +} + + +static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c) +{ + uint64_t tmp; + int rc; + uint32_t core = pir_to_core_id(c->pir); + + /* Special wakeup bits that could hold power mgt */ + rc = xscom_read(chip->id, + XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP), + &tmp); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_SET), + "SLW: Failed to read EC_PPM_SPECIAL_WKUP_HYP\n"); + return false; + } + if (tmp) + prlog(PR_WARNING, + "SLW: core %d EC_PPM_SPECIAL_WKUP_HYP read 0x%016llx\n", + core, tmp); + rc = xscom_read(chip->id, + XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_OTR), + &tmp); + if (tmp) + prlog(PR_WARNING, + "SLW: core %d EC_PPM_SPECIAL_WKUP_OTR read 0x%016llx\n", + core, tmp); + return true; +} /* Define device-tree fields */ #define MAX_NAME_LEN 16 @@ -1069,31 +1071,6 @@ void add_cpu_idle_state_properties(void) free(pm_ctrl_reg_mask_buf); } -static void slw_patch_regs(struct proc_chip *chip) -{ - struct cpu_thread *c; - void *image = (void *)chip->slw_base; - int rc; - - for_each_available_cpu(c) { - if (c->chip_id != chip->id) - continue; - - /* Clear HRMOR */ - rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, - P8_SPR_HRMOR, 0, - cpu_get_core_index(c), - cpu_get_thread_index(c)); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: Failed to set HRMOR for CPU %x\n", - c->pir); - } - - /* XXX Add HIDs etc... */ - } -} - static void slw_init_chip_p9(struct proc_chip *chip) { struct cpu_thread *c; @@ -1135,6 +1112,32 @@ static bool slw_image_check_p9(struct proc_chip *chip) } +#ifdef CONFIG_P8 +static void slw_patch_regs(struct proc_chip *chip) +{ + struct cpu_thread *c; + void *image = (void *)chip->slw_base; + int rc; + + for_each_available_cpu(c) { + if (c->chip_id != chip->id) + continue; + + /* Clear HRMOR */ + rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, + P8_SPR_HRMOR, 0, + cpu_get_core_index(c), + cpu_get_thread_index(c)); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: Failed to set HRMOR for CPU %x\n", + c->pir); + } + + /* XXX Add HIDs etc... */ + } +} + static bool slw_image_check_p8(struct proc_chip *chip) { int64_t rc; @@ -1284,6 +1287,7 @@ static int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t enter) } opal_call(OPAL_CONFIG_CPU_IDLE_STATE, opal_config_cpu_idle_state, 2); +#endif int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) { @@ -1324,6 +1328,7 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) sprn, val, cpu_pir); } +#ifdef CONFIG_P8 } else if (proc_gen == proc_gen_p8) { int spr_is_supported = 0; void *image; @@ -1347,6 +1352,7 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) sprn, val, cpu_get_core_index(c), cpu_get_thread_index(c)); +#endif } else { log_simple_error(&e_info(OPAL_RC_SLW_REG), "SLW: proc_gen not supported\n"); @@ -1381,6 +1387,7 @@ void slw_init(void) } if (proc_gen == proc_gen_p8) { +#ifdef CONFIG_P8 for_each_chip(chip) { slw_init_chip_p8(chip); if(slw_image_check_p8(chip)) @@ -1389,6 +1396,7 @@ void slw_init(void) slw_late_init_p8(chip); } p8_sbe_init_timer(); +#endif } else if (proc_gen == proc_gen_p9) { for_each_chip(chip) { slw_init_chip_p9(chip); diff --git a/libpore/Makefile.inc b/libpore/Makefile.inc index 06d9c8902..a60674856 100644 --- a/libpore/Makefile.inc +++ b/libpore/Makefile.inc @@ -1,5 +1,9 @@ -LIBPORE_SRCS = p8_pore_table_gen_api_fixed.C p9_stop_api.C p9_stop_util.C p10_stop_api.C p10_stop_util.C -LIBPORE_SRCS += p8_pore_table_static_data.c sbe_xip_image.c pore_inline_assembler.c +LIBPORE_SRCS = p9_stop_api.C p9_stop_util.C p10_stop_api.C p10_stop_util.C +LIBPORE_SRCS += sbe_xip_image.c pore_inline_assembler.c +ifeq ($(CONFIG_P8),1) +LIBPORE_SRCS += p8_pore_table_gen_api_fixed.C p8_pore_table_static_data.c +endif + LIBPORE_OBJS_1 = $(LIBPORE_SRCS:%.c=%.o) LIBPORE_OBJS = $(LIBPORE_OBJS_1:%.C=%.o) SUBDIRS += libpore From patchwork Fri Dec 17 02:36:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1569693 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[203.219.139.206]) by smtp.gmail.com with ESMTPSA id z13sm7835249pfj.160.2021.12.16.18.37.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 18:37:09 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Fri, 17 Dec 2021 12:36:43 +1000 Message-Id: <20211217023647.715283-6-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211217023647.715283-1-npiggin@gmail.com> References: <20211217023647.715283-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 5/9] hwprobe: convert vas_init(), nx_init() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith Reviewed-by: Dan Horák [npiggin: remove imc_init because it moved later in boot (fbcbd4e47c)] Signed-off-by: Stewart Smith --- core/init.c | 6 ------ hw/nx.c | 2 ++ hw/vas.c | 2 ++ 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/core/init.c b/core/init.c index c3e0c494d..6a1c3f034 100644 --- a/core/init.c +++ b/core/init.c @@ -1355,12 +1355,6 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* Catalog decompression routine */ imc_decompress_catalog(); - /* Virtual Accelerator Switchboard */ - vas_init(); - - /* NX init */ - nx_init(); - /* Probe all HWPROBE hardware we have code linked for */ probe_hardware(); diff --git a/hw/nx.c b/hw/nx.c index fdadf53c7..b1cab5774 100644 --- a/hw/nx.c +++ b/hw/nx.c @@ -136,3 +136,5 @@ void nx_init(void) if (proc_gen >= proc_gen_p9) darn_init(); } + +DEFINE_HWPROBE_DEPS(nx, nx_init, "vas"); diff --git a/hw/vas.c b/hw/vas.c index 0dbe0bcda..96ca055cc 100644 --- a/hw/vas.c +++ b/hw/vas.c @@ -637,3 +637,5 @@ out: vas_err("Disabled (failed initialization)\n"); return; } + +DEFINE_HWPROBE(vas, vas_init); From patchwork Fri Dec 17 02:36:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1569694 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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[203.219.139.206]) by smtp.gmail.com with ESMTPSA id z13sm7835249pfj.160.2021.12.16.18.37.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 18:37:12 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Fri, 17 Dec 2021 12:36:44 +1000 Message-Id: <20211217023647.715283-7-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211217023647.715283-1-npiggin@gmail.com> References: <20211217023647.715283-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 6/9] npu: move npu_set_fence_state() to phb_ops X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith This lets us consider not building in npu.o Reviewed-by: Dan Horák Signed-off-by: Stewart Smith --- core/hmi.c | 2 +- hw/npu.c | 7 +++++-- include/npu.h | 1 - include/pci.h | 3 +++ 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/core/hmi.c b/core/hmi.c index ce5abd7d6..fe3d82529 100644 --- a/core/hmi.c +++ b/core/hmi.c @@ -908,7 +908,7 @@ static void find_npu_checkstop_reason(int flat_chip_id, if (phb->phb_type == phb_type_pcie_v3) { /* Set the NPU to fenced since it can't recover. */ - npu_set_fence_state(phb_to_npu(phb), true); + phb->ops->set_fence_state(phb, true); } /* Set up the HMI event */ diff --git a/hw/npu.c b/hw/npu.c index 35e6372d2..542f37397 100644 --- a/hw/npu.c +++ b/hw/npu.c @@ -925,7 +925,9 @@ static int64_t npu_eeh_next_error(struct phb *phb, } /* For use in error injection and handling. */ -void npu_set_fence_state(struct npu *p, bool fence) { +static void npu_set_fence_state(struct phb *phb, bool fence) { + struct npu *p = phb_to_npu(phb); + p->fenced = fence; if (fence) @@ -968,7 +970,7 @@ static int64_t npu_err_inject(struct phb *phb, uint64_t pe_number, return OPAL_PARAMETER; } else if (type == 1) { /* Emulate fence mode. */ - npu_set_fence_state(p, true); + npu_set_fence_state(phb, true); } else { /* Cause a freeze with an invalid MMIO read. If the BAR is not * enabled, this will checkstop the machine. @@ -1012,6 +1014,7 @@ static const struct phb_ops npu_ops = { .get_diag_data2 = NULL, .set_capi_mode = NULL, .set_capp_recovery = NULL, + .set_fence_state = npu_set_fence_state, }; static void assign_mmio_bars(uint32_t gcid, uint32_t xscom, diff --git a/include/npu.h b/include/npu.h index 50cc9c9fc..45818a28f 100644 --- a/include/npu.h +++ b/include/npu.h @@ -153,7 +153,6 @@ int64_t npu_dev_procedure(void *dev, struct pci_cfg_reg_filter *pcrf, uint32_t offset, uint32_t len, uint32_t *data, bool write); -void npu_set_fence_state(struct npu *p, bool fence); void npu_dev_procedure_reset(struct npu_dev *dev); #define NPUDBG(p, fmt, a...) prlog(PR_DEBUG, "NPU%d: " fmt, \ diff --git a/include/pci.h b/include/pci.h index caae74431..101442490 100644 --- a/include/pci.h +++ b/include/pci.h @@ -340,6 +340,9 @@ struct phb_ops { /* Get/set PBCQ Tunnel BAR register */ void (*get_tunnel_bar)(struct phb *phb, uint64_t *addr); int64_t (*set_tunnel_bar)(struct phb *phb, uint64_t addr); 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[203.219.139.206]) by smtp.gmail.com with ESMTPSA id z13sm7835249pfj.160.2021.12.16.18.37.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 18:37:15 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Fri, 17 Dec 2021 12:36:45 +1000 Message-Id: <20211217023647.715283-8-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211217023647.715283-1-npiggin@gmail.com> References: <20211217023647.715283-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 7/9] npu: Move npu.o and npu-hw-procedules.o under CONIFG_P8 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith This saves an extra 6kb of skiboot.lid.xz. Reviewed-by: Dan Horák Signed-off-by: Stewart Smith --- hw/Makefile.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/Makefile.inc b/hw/Makefile.inc index e273e898c..302718885 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -4,13 +4,14 @@ HW_OBJS = xscom.o chiptod.o lpc.o lpc-uart.o psi.o HW_OBJS += homer.o slw.o occ.o fsi-master.o centaur.o imc.o HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-compress.o nx-842.o nx-gzip.o HW_OBJS += sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o -HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o +HW_OBJS += dts.o lpc-rtc.o xive.o phb4.o HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o HW_OBJS += npu-opal.o ocmb.o xive2.o pau.o pau-hw-procedures.o ifeq ($(CONFIG_P8),1) HW_OBJS += phb3.o +HW_OBJS += npu.o npu-hw-procedures.o endif HW=hw/built-in.a From patchwork Fri Dec 17 02:36:46 2021 Content-Type: text/plain; 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[203.219.139.206]) by smtp.gmail.com with ESMTPSA id z13sm7835249pfj.160.2021.12.16.18.37.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 18:37:18 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Fri, 17 Dec 2021 12:36:46 +1000 Message-Id: <20211217023647.715283-9-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211217023647.715283-1-npiggin@gmail.com> References: <20211217023647.715283-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 8/9] platforms: put P8 platforms behind CONFIG_P8 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith Shaves an additional 4kb off skiboot.lid.xz. Reviewed-by: Dan Horák Signed-off-by: Stewart Smith --- platforms/astbmc/Makefile.inc | 12 ++++++++---- platforms/ibm-fsp/Makefile.inc | 7 ++++++- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/platforms/astbmc/Makefile.inc b/platforms/astbmc/Makefile.inc index 070813231..1cdf37f2a 100644 --- a/platforms/astbmc/Makefile.inc +++ b/platforms/astbmc/Makefile.inc @@ -1,13 +1,17 @@ SUBDIRS += $(PLATDIR)/astbmc ASTBMC_OBJS = pnor.o common.o slots.o \ - palmetto.o habanero.o firestone.o \ - p8dtu.o p8dnu.o \ - garrison.o barreleye.o \ witherspoon.o zaius.o romulus.o p9dsu.o \ - vesnin.o nicole.o mihawk.o mowgli.o \ + nicole.o mihawk.o mowgli.o \ talos.o blackbird.o \ swift.o rainier.o +ifeq ($(CONFIG_P8),1) +ASTBMC_OBJS += palmetto.o habanero.o firestone.o \ + p8dtu.o p8dnu.o \ + garrison.o barreleye.o \ + vesnin.o +endif + ASTBMC = $(PLATDIR)/astbmc/built-in.a $(ASTBMC): $(ASTBMC_OBJS:%=$(PLATDIR)/astbmc/%) diff --git a/platforms/ibm-fsp/Makefile.inc b/platforms/ibm-fsp/Makefile.inc index 8883f09c1..fd80a79a9 100644 --- a/platforms/ibm-fsp/Makefile.inc +++ b/platforms/ibm-fsp/Makefile.inc @@ -1,7 +1,12 @@ SUBDIRS += $(PLATDIR)/ibm-fsp IBM_FSP_OBJS = common.o lxvpd.o hostservices.o fsp-vpd.o \ - firenze.o firenze-pci.o zz.o + firenze-pci.o zz.o + +ifeq ($(CONFIG_P8),1) +IBM_FSP_OBJS += firenze.o +endif + IBM_FSP = $(PLATDIR)/ibm-fsp/built-in.a ifeq ($(CONFIG_FSP),1) From patchwork Fri Dec 17 02:36:47 2021 Content-Type: text/plain; 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[203.219.139.206]) by smtp.gmail.com with ESMTPSA id z13sm7835249pfj.160.2021.12.16.18.37.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 18:37:20 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Fri, 17 Dec 2021 12:36:47 +1000 Message-Id: <20211217023647.715283-10-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211217023647.715283-1-npiggin@gmail.com> References: <20211217023647.715283-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 9/9] npu: Add CONFIG_NPU to optionally skip NPU code X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith Saves a whopping 39kb of skiboot.lid.xz. Reviewed-by: Dan Horák Signed-off-by: Stewart Smith --- Makefile | 2 ++ Makefile.main | 4 ++++ core/hmi.c | 10 +++++++++- core/platform.c | 1 - hw/Makefile.inc | 18 ++++++++++++++---- hw/npu2-common.c | 3 ++- hw/npu2.c | 1 + include/npu2.h | 8 +++++++- include/pci.h | 3 +++ platforms/astbmc/Makefile.inc | 15 +++++++++++---- 10 files changed, 53 insertions(+), 12 deletions(-) diff --git a/Makefile b/Makefile index 625f212ea..ce61e3af0 100644 --- a/Makefile +++ b/Makefile @@ -61,6 +61,8 @@ DEAD_CODE_ELIMINATION ?= 0 CONFIG_FSP?=1 # Try to build without POWER8 support CONFIG_P8?=1 +# Try and build without any NPU support +CONFIG_NPU?=1 # # Where is the source directory, must be a full path (no ~) diff --git a/Makefile.main b/Makefile.main index 2a346a6c9..dce0338da 100644 --- a/Makefile.main +++ b/Makefile.main @@ -165,6 +165,10 @@ ifeq ($(CONFIG_P8),1) CFLAGS += -DCONFIG_P8=1 endif +ifeq ($(CONFIG_NPU),1) +CFLAGS += -DCONFIG_NPU=1 +endif + CFLAGS += $(call try-cflag,$(CC),-Wjump-misses-init) \ $(call try-cflag,$(CC),-Wsuggest-attribute=const) \ $(call try-cflag,$(CC),-Wsuggest-attribute=noreturn) \ diff --git a/core/hmi.c b/core/hmi.c index fe3d82529..1af9971d2 100644 --- a/core/hmi.c +++ b/core/hmi.c @@ -719,6 +719,7 @@ static void find_nx_checkstop_reason(int flat_chip_id, queue_hmi_event(hmi_evt, 0, out_flags); } +#ifdef CONFIG_NPU static void add_npu_xstop_reason(uint32_t *xstop_reason, uint8_t reason) { int i, reason_count; @@ -854,7 +855,7 @@ static bool npu_fir_errors(struct phb *phb, int flat_chip_id, switch (phb->phb_type) { case phb_type_npu_v2: case phb_type_npu_v2_opencapi: - npu2_dump_scoms(npu2, flat_chip_id); + phb->ops->dump_debug_data(phb, flat_chip_id); break; case phb_type_pau_opencapi: pau_opencapi_dump_scoms(pau); @@ -922,6 +923,13 @@ static void find_npu_checkstop_reason(int flat_chip_id, queue_hmi_event(hmi_evt, 1, out_flags); } } +#else +static void find_npu_checkstop_reason(int flat_chip_id __unused, + struct OpalHMIEvent *hmi_evt __unused, + uint64_t *out_flags __unused) +{ +} +#endif static void decode_malfunction(struct OpalHMIEvent *hmi_evt, uint64_t *out_flags) { diff --git a/core/platform.c b/core/platform.c index 320fdea03..3f4c8bdd5 100644 --- a/core/platform.c +++ b/core/platform.c @@ -226,7 +226,6 @@ static struct platform generic_platform = { .start_preload_resource = generic_start_preload_resource, .resource_loaded = generic_resource_loaded, .ocapi = &generic_ocapi, - .npu2_device_detect = npu2_i2c_presence_detect, /* Assumes ZZ */ }; const struct bmc_platform *bmc_platform = &generic_bmc; diff --git a/hw/Makefile.inc b/hw/Makefile.inc index 302718885..7fb7c38f8 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -5,14 +5,24 @@ HW_OBJS += homer.o slw.o occ.o fsi-master.o centaur.o imc.o HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-compress.o nx-842.o nx-gzip.o HW_OBJS += sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o HW_OBJS += dts.o lpc-rtc.o xive.o phb4.o -HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o -HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o +HW_OBJS += fake-nvram.o lpc-mbox.o +HW_OBJS += phys-map.o sbe-p9.o capp.o HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o -HW_OBJS += npu-opal.o ocmb.o xive2.o pau.o pau-hw-procedures.o +HW_OBJS += ocmb.o xive2.o pau.o pau-hw-procedures.o + +ifeq ($(CONFIG_NPU),1) +HW_OBJS += npu2.o npu2-hw-procedures.o +HW_OBJS += npu2-common.o npu2-opencapi.o +HW_OBJS += npu-opal.o ifeq ($(CONFIG_P8),1) -HW_OBJS += phb3.o HW_OBJS += npu.o npu-hw-procedures.o endif +endif + +ifeq ($(CONFIG_P8),1) +HW_OBJS += phb3.o +endif + HW=hw/built-in.a include $(SRC)/hw/fsp/Makefile.inc diff --git a/hw/npu2-common.c b/hw/npu2-common.c index 02f102fe5..33339ffa1 100644 --- a/hw/npu2-common.c +++ b/hw/npu2-common.c @@ -296,8 +296,9 @@ static void show_all_regs(struct npu2 *npu, int brick_index) } } -void npu2_dump_scoms(struct npu2 *npu, int chip_id) +void npu2_dump_scoms(struct phb *phb, int chip_id) { + struct npu2 *npu = phb_to_npu2_nvlink(phb); if (npu && npu->chip_id == chip_id) show_all_regs(npu, -1 /* all bricks */); } diff --git a/hw/npu2.c b/hw/npu2.c index cf57eeb0c..e18a1b7b1 100644 --- a/hw/npu2.c +++ b/hw/npu2.c @@ -1316,6 +1316,7 @@ static const struct phb_ops npu_ops = { .set_capi_mode = NULL, .set_capp_recovery = NULL, .tce_kill = npu2_tce_kill, + .dump_debug_data = npu2_dump_scoms, }; static void assign_mmio_bars(uint64_t gcid, uint32_t scom, uint64_t reg[2], uint64_t mm_win[2]) diff --git a/include/npu2.h b/include/npu2.h index b302108b9..374c20779 100644 --- a/include/npu2.h +++ b/include/npu2.h @@ -212,7 +212,13 @@ static inline struct phb *npu2_dev_to_phb(struct npu2_dev *ndev) } } +#ifdef CONFIG_NPU void npu2_i2c_presence_detect(struct npu2 *npu); +#else +static inline void npu2_i2c_presence_detect(struct npu2 *npu __unused) +{ +} +#endif int npu2_opencapi_init_npu(struct npu2 *npu); int npu2_nvlink_init_npu(struct npu2 *npu); void npu2_nvlink_create_phb(struct npu2 *npu, struct dt_node *dn); @@ -241,7 +247,7 @@ int64_t npu2_freeze_status(struct phb *phb __unused, uint8_t *freeze_state, uint16_t *pci_error_type __unused, uint16_t *severity __unused); -void npu2_dump_scoms(struct npu2 *npu, int chip_id); +void npu2_dump_scoms(struct phb *phb, int chip_id); int64_t npu2_init_context(struct phb *phb, uint64_t msr, uint64_t bdf); int64_t npu2_destroy_context(struct phb *phb, uint64_t bdf); diff --git a/include/pci.h b/include/pci.h index 101442490..46d3d0ace 100644 --- a/include/pci.h +++ b/include/pci.h @@ -343,6 +343,9 @@ struct phb_ops { /* Currently only used by NPU HMI code */ void (*set_fence_state)(struct phb *phb, bool fence); + + /* The most terrible of situtions, dump debug data to console. */ + void (*dump_debug_data)(struct phb *phb, int flat_chip_id); }; enum phb_type { diff --git a/platforms/astbmc/Makefile.inc b/platforms/astbmc/Makefile.inc index 1cdf37f2a..be2267d3f 100644 --- a/platforms/astbmc/Makefile.inc +++ b/platforms/astbmc/Makefile.inc @@ -1,16 +1,23 @@ SUBDIRS += $(PLATDIR)/astbmc ASTBMC_OBJS = pnor.o common.o slots.o \ - witherspoon.o zaius.o romulus.o p9dsu.o \ - nicole.o mihawk.o mowgli.o \ + witherspoon.o romulus.o p9dsu.o \ + nicole.o mowgli.o \ talos.o blackbird.o \ - swift.o rainier.o + rainier.o + +ifeq ($(CONFIG_NPU),1) +ASTBMC_OBJS += zaius.o mihawk.o swift.o +endif ifeq ($(CONFIG_P8),1) ASTBMC_OBJS += palmetto.o habanero.o firestone.o \ p8dtu.o p8dnu.o \ - garrison.o barreleye.o \ + barreleye.o \ vesnin.o +ifeq ($(CONFIG_NPU),1) +ASTBMC_OBJS += garrison.o +endif endif ASTBMC = $(PLATDIR)/astbmc/built-in.a